161b8ac9bSSudeep Holla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 261b8ac9bSSudeep Holla# Copyright 2021 ARM Ltd. 361b8ac9bSSudeep Holla%YAML 1.2 461b8ac9bSSudeep Holla--- 561b8ac9bSSudeep Holla$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# 661b8ac9bSSudeep Holla$schema: http://devicetree.org/meta-schemas/core.yaml# 761b8ac9bSSudeep Holla 884e85359SKrzysztof Kozlowskititle: System Control and Management Interface (SCMI) Message Protocol 961b8ac9bSSudeep Holla 1061b8ac9bSSudeep Hollamaintainers: 1161b8ac9bSSudeep Holla - Sudeep Holla <sudeep.holla@arm.com> 1261b8ac9bSSudeep Holla 1361b8ac9bSSudeep Holladescription: | 1461b8ac9bSSudeep Holla The SCMI is intended to allow agents such as OSPM to manage various functions 1561b8ac9bSSudeep Holla that are provided by the hardware platform it is running on, including power 1661b8ac9bSSudeep Holla and performance functions. 1761b8ac9bSSudeep Holla 1861b8ac9bSSudeep Holla This binding is intended to define the interface the firmware implementing 1961b8ac9bSSudeep Holla the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control 2061b8ac9bSSudeep Holla and Management Interface Platform Design Document")[0] provide for OSPM in 2161b8ac9bSSudeep Holla the device tree. 2261b8ac9bSSudeep Holla 2361b8ac9bSSudeep Holla [0] https://developer.arm.com/documentation/den0056/latest 2461b8ac9bSSudeep Holla 2561b8ac9bSSudeep Hollaproperties: 2661b8ac9bSSudeep Holla $nodename: 2761b8ac9bSSudeep Holla const: scmi 2861b8ac9bSSudeep Holla 2961b8ac9bSSudeep Holla compatible: 3061b8ac9bSSudeep Holla oneOf: 3161b8ac9bSSudeep Holla - description: SCMI compliant firmware with mailbox transport 3261b8ac9bSSudeep Holla items: 3361b8ac9bSSudeep Holla - const: arm,scmi 3461b8ac9bSSudeep Holla - description: SCMI compliant firmware with ARM SMC/HVC transport 3561b8ac9bSSudeep Holla items: 3661b8ac9bSSudeep Holla - const: arm,scmi-smc 3760625667SIgor Skalkin - description: SCMI compliant firmware with SCMI Virtio transport. 3860625667SIgor Skalkin The virtio transport only supports a single device. 3960625667SIgor Skalkin items: 4060625667SIgor Skalkin - const: arm,scmi-virtio 41b7d2cf7cSEtienne Carriere - description: SCMI compliant firmware with OP-TEE transport 42b7d2cf7cSEtienne Carriere items: 43b7d2cf7cSEtienne Carriere - const: linaro,scmi-optee 4461b8ac9bSSudeep Holla 4561b8ac9bSSudeep Holla interrupts: 4661b8ac9bSSudeep Holla description: 4761b8ac9bSSudeep Holla The interrupt that indicates message completion by the platform 4861b8ac9bSSudeep Holla rather than by the return of the smc call. This should not be used 4961b8ac9bSSudeep Holla except when the platform requires such behavior. 5061b8ac9bSSudeep Holla maxItems: 1 5161b8ac9bSSudeep Holla 5261b8ac9bSSudeep Holla interrupt-names: 5361b8ac9bSSudeep Holla const: a2p 5461b8ac9bSSudeep Holla 5561b8ac9bSSudeep Holla mbox-names: 5661b8ac9bSSudeep Holla description: 5761b8ac9bSSudeep Holla Specifies the mailboxes used to communicate with SCMI compliant 5861b8ac9bSSudeep Holla firmware. 5961b8ac9bSSudeep Holla items: 6061b8ac9bSSudeep Holla - const: tx 6161b8ac9bSSudeep Holla - const: rx 6261b8ac9bSSudeep Holla 6361b8ac9bSSudeep Holla mboxes: 6461b8ac9bSSudeep Holla description: 6561b8ac9bSSudeep Holla List of phandle and mailbox channel specifiers. It should contain 6661b8ac9bSSudeep Holla exactly one or two mailboxes, one for transmitting messages("tx") 6761b8ac9bSSudeep Holla and another optional for receiving the notifications("rx") if supported. 6861b8ac9bSSudeep Holla minItems: 1 6961b8ac9bSSudeep Holla maxItems: 2 7061b8ac9bSSudeep Holla 7161b8ac9bSSudeep Holla shmem: 7261b8ac9bSSudeep Holla description: 7361b8ac9bSSudeep Holla List of phandle pointing to the shared memory(SHM) area, for each 7461b8ac9bSSudeep Holla transport channel specified. 7561b8ac9bSSudeep Holla minItems: 1 7661b8ac9bSSudeep Holla maxItems: 2 7761b8ac9bSSudeep Holla 7861b8ac9bSSudeep Holla '#address-cells': 7961b8ac9bSSudeep Holla const: 1 8061b8ac9bSSudeep Holla 8161b8ac9bSSudeep Holla '#size-cells': 8261b8ac9bSSudeep Holla const: 0 8361b8ac9bSSudeep Holla 840539884cSCristian Marussi atomic-threshold-us: 850539884cSCristian Marussi description: 860539884cSCristian Marussi An optional time value, expressed in microseconds, representing, on this 870539884cSCristian Marussi platform, the threshold above which any SCMI command, advertised to have 880539884cSCristian Marussi an higher-than-threshold execution latency, should not be considered for 890539884cSCristian Marussi atomic mode of operation, even if requested. 900539884cSCristian Marussi default: 0 910539884cSCristian Marussi 9261b8ac9bSSudeep Holla arm,smc-id: 9361b8ac9bSSudeep Holla $ref: /schemas/types.yaml#/definitions/uint32 9461b8ac9bSSudeep Holla description: 9561b8ac9bSSudeep Holla SMC id required when using smc or hvc transports 9661b8ac9bSSudeep Holla 97b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 98b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 99b7d2cf7cSEtienne Carriere description: 100b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport. 101b7d2cf7cSEtienne Carriere 10261b8ac9bSSudeep Holla protocol@11: 103*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 104*df4fdd0dSRob Herring unevaluatedProperties: false 105*df4fdd0dSRob Herring 10661b8ac9bSSudeep Holla properties: 10761b8ac9bSSudeep Holla reg: 10861b8ac9bSSudeep Holla const: 0x11 10961b8ac9bSSudeep Holla 11061b8ac9bSSudeep Holla '#power-domain-cells': 11161b8ac9bSSudeep Holla const: 1 11261b8ac9bSSudeep Holla 11361b8ac9bSSudeep Holla required: 11461b8ac9bSSudeep Holla - '#power-domain-cells' 11561b8ac9bSSudeep Holla 11661b8ac9bSSudeep Holla protocol@13: 117*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 118*df4fdd0dSRob Herring unevaluatedProperties: false 119*df4fdd0dSRob Herring 12061b8ac9bSSudeep Holla properties: 12161b8ac9bSSudeep Holla reg: 12261b8ac9bSSudeep Holla const: 0x13 12361b8ac9bSSudeep Holla 12461b8ac9bSSudeep Holla '#clock-cells': 12561b8ac9bSSudeep Holla const: 1 12661b8ac9bSSudeep Holla 12761b8ac9bSSudeep Holla required: 12861b8ac9bSSudeep Holla - '#clock-cells' 12961b8ac9bSSudeep Holla 13061b8ac9bSSudeep Holla protocol@14: 131*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 132*df4fdd0dSRob Herring unevaluatedProperties: false 133*df4fdd0dSRob Herring 13461b8ac9bSSudeep Holla properties: 13561b8ac9bSSudeep Holla reg: 13661b8ac9bSSudeep Holla const: 0x14 13761b8ac9bSSudeep Holla 13861b8ac9bSSudeep Holla '#clock-cells': 13961b8ac9bSSudeep Holla const: 1 14061b8ac9bSSudeep Holla 14161b8ac9bSSudeep Holla required: 14261b8ac9bSSudeep Holla - '#clock-cells' 14361b8ac9bSSudeep Holla 14461b8ac9bSSudeep Holla protocol@15: 145*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 146*df4fdd0dSRob Herring unevaluatedProperties: false 147*df4fdd0dSRob Herring 14861b8ac9bSSudeep Holla properties: 14961b8ac9bSSudeep Holla reg: 15061b8ac9bSSudeep Holla const: 0x15 15161b8ac9bSSudeep Holla 15261b8ac9bSSudeep Holla '#thermal-sensor-cells': 15361b8ac9bSSudeep Holla const: 1 15461b8ac9bSSudeep Holla 15561b8ac9bSSudeep Holla required: 15661b8ac9bSSudeep Holla - '#thermal-sensor-cells' 15761b8ac9bSSudeep Holla 15861b8ac9bSSudeep Holla protocol@16: 159*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 160*df4fdd0dSRob Herring unevaluatedProperties: false 161*df4fdd0dSRob Herring 16261b8ac9bSSudeep Holla properties: 16361b8ac9bSSudeep Holla reg: 16461b8ac9bSSudeep Holla const: 0x16 16561b8ac9bSSudeep Holla 16661b8ac9bSSudeep Holla '#reset-cells': 16761b8ac9bSSudeep Holla const: 1 16861b8ac9bSSudeep Holla 16961b8ac9bSSudeep Holla required: 17061b8ac9bSSudeep Holla - '#reset-cells' 17161b8ac9bSSudeep Holla 17261b8ac9bSSudeep Holla protocol@17: 173*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 174*df4fdd0dSRob Herring unevaluatedProperties: false 175*df4fdd0dSRob Herring 17661b8ac9bSSudeep Holla properties: 17761b8ac9bSSudeep Holla reg: 17861b8ac9bSSudeep Holla const: 0x17 17961b8ac9bSSudeep Holla 18061b8ac9bSSudeep Holla regulators: 18161b8ac9bSSudeep Holla type: object 182*df4fdd0dSRob Herring additionalProperties: false 18361b8ac9bSSudeep Holla description: 18461b8ac9bSSudeep Holla The list of all regulators provided by this SCMI controller. 18561b8ac9bSSudeep Holla 186*df4fdd0dSRob Herring properties: 187*df4fdd0dSRob Herring '#address-cells': 188*df4fdd0dSRob Herring const: 1 189*df4fdd0dSRob Herring 190*df4fdd0dSRob Herring '#size-cells': 191*df4fdd0dSRob Herring const: 0 192*df4fdd0dSRob Herring 19361b8ac9bSSudeep Holla patternProperties: 194*df4fdd0dSRob Herring '^regulator@[0-9a-f]+$': 19561b8ac9bSSudeep Holla type: object 19661b8ac9bSSudeep Holla $ref: "../regulator/regulator.yaml#" 197*df4fdd0dSRob Herring unevaluatedProperties: false 19861b8ac9bSSudeep Holla 19961b8ac9bSSudeep Holla properties: 20061b8ac9bSSudeep Holla reg: 20161b8ac9bSSudeep Holla maxItems: 1 20261b8ac9bSSudeep Holla description: Identifier for the voltage regulator. 20361b8ac9bSSudeep Holla 20461b8ac9bSSudeep Holla required: 20561b8ac9bSSudeep Holla - reg 20661b8ac9bSSudeep Holla 207451d8457SCristian Marussi protocol@18: 208*df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 209*df4fdd0dSRob Herring unevaluatedProperties: false 210*df4fdd0dSRob Herring 211451d8457SCristian Marussi properties: 212451d8457SCristian Marussi reg: 213451d8457SCristian Marussi const: 0x18 214451d8457SCristian Marussi 21561b8ac9bSSudeep HollaadditionalProperties: false 21661b8ac9bSSudeep Holla 217*df4fdd0dSRob Herring$defs: 218*df4fdd0dSRob Herring protocol-node: 21961b8ac9bSSudeep Holla type: object 22061b8ac9bSSudeep Holla description: 22161b8ac9bSSudeep Holla Each sub-node represents a protocol supported. If the platform 22261b8ac9bSSudeep Holla supports a dedicated communication channel for a particular protocol, 22361b8ac9bSSudeep Holla then the corresponding transport properties must be present. 22460625667SIgor Skalkin The virtio transport does not support a dedicated communication channel. 22561b8ac9bSSudeep Holla 22661b8ac9bSSudeep Holla properties: 22761b8ac9bSSudeep Holla reg: 22861b8ac9bSSudeep Holla maxItems: 1 22961b8ac9bSSudeep Holla 23061b8ac9bSSudeep Holla mbox-names: 23161b8ac9bSSudeep Holla items: 23261b8ac9bSSudeep Holla - const: tx 23361b8ac9bSSudeep Holla - const: rx 23461b8ac9bSSudeep Holla 23561b8ac9bSSudeep Holla mboxes: 23661b8ac9bSSudeep Holla minItems: 1 23761b8ac9bSSudeep Holla maxItems: 2 23861b8ac9bSSudeep Holla 23961b8ac9bSSudeep Holla shmem: 24061b8ac9bSSudeep Holla minItems: 1 24161b8ac9bSSudeep Holla maxItems: 2 24261b8ac9bSSudeep Holla 243b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 244b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 245b7d2cf7cSEtienne Carriere description: 246b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport and 247b7d2cf7cSEtienne Carriere protocol has a dedicated communication channel. 248b7d2cf7cSEtienne Carriere 24961b8ac9bSSudeep Holla required: 25061b8ac9bSSudeep Holla - reg 25161b8ac9bSSudeep Holla 25261b8ac9bSSudeep Hollarequired: 25361b8ac9bSSudeep Holla - compatible 25461b8ac9bSSudeep Holla 25561b8ac9bSSudeep Hollaif: 25661b8ac9bSSudeep Holla properties: 25761b8ac9bSSudeep Holla compatible: 25861b8ac9bSSudeep Holla contains: 25961b8ac9bSSudeep Holla const: arm,scmi 26061b8ac9bSSudeep Hollathen: 26161b8ac9bSSudeep Holla properties: 26261b8ac9bSSudeep Holla interrupts: false 26361b8ac9bSSudeep Holla interrupt-names: false 26461b8ac9bSSudeep Holla 26561b8ac9bSSudeep Holla required: 26661b8ac9bSSudeep Holla - mboxes 26760625667SIgor Skalkin - shmem 26861b8ac9bSSudeep Holla 26961b8ac9bSSudeep Hollaelse: 27061b8ac9bSSudeep Holla if: 27161b8ac9bSSudeep Holla properties: 27261b8ac9bSSudeep Holla compatible: 27361b8ac9bSSudeep Holla contains: 27461b8ac9bSSudeep Holla const: arm,scmi-smc 27561b8ac9bSSudeep Holla then: 27661b8ac9bSSudeep Holla required: 27761b8ac9bSSudeep Holla - arm,smc-id 27860625667SIgor Skalkin - shmem 27961b8ac9bSSudeep Holla 280b7d2cf7cSEtienne Carriere else: 281b7d2cf7cSEtienne Carriere if: 282b7d2cf7cSEtienne Carriere properties: 283b7d2cf7cSEtienne Carriere compatible: 284b7d2cf7cSEtienne Carriere contains: 285b7d2cf7cSEtienne Carriere const: linaro,scmi-optee 286b7d2cf7cSEtienne Carriere then: 287b7d2cf7cSEtienne Carriere required: 288b7d2cf7cSEtienne Carriere - linaro,optee-channel-id 289b7d2cf7cSEtienne Carriere 29061b8ac9bSSudeep Hollaexamples: 29161b8ac9bSSudeep Holla - | 29261b8ac9bSSudeep Holla firmware { 29361b8ac9bSSudeep Holla scmi { 29461b8ac9bSSudeep Holla compatible = "arm,scmi"; 29561b8ac9bSSudeep Holla mboxes = <&mhuB 0 0>, 29661b8ac9bSSudeep Holla <&mhuB 0 1>; 29761b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 29861b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0>, 29961b8ac9bSSudeep Holla <&cpu_scp_lpri1>; 30061b8ac9bSSudeep Holla 30161b8ac9bSSudeep Holla #address-cells = <1>; 30261b8ac9bSSudeep Holla #size-cells = <0>; 30361b8ac9bSSudeep Holla 3040539884cSCristian Marussi atomic-threshold-us = <10000>; 3050539884cSCristian Marussi 30661b8ac9bSSudeep Holla scmi_devpd: protocol@11 { 30761b8ac9bSSudeep Holla reg = <0x11>; 30861b8ac9bSSudeep Holla #power-domain-cells = <1>; 30961b8ac9bSSudeep Holla }; 31061b8ac9bSSudeep Holla 31161b8ac9bSSudeep Holla scmi_dvfs: protocol@13 { 31261b8ac9bSSudeep Holla reg = <0x13>; 31361b8ac9bSSudeep Holla #clock-cells = <1>; 31461b8ac9bSSudeep Holla 31561b8ac9bSSudeep Holla mboxes = <&mhuB 1 0>, 31661b8ac9bSSudeep Holla <&mhuB 1 1>; 31761b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 31861b8ac9bSSudeep Holla shmem = <&cpu_scp_hpri0>, 31961b8ac9bSSudeep Holla <&cpu_scp_hpri1>; 32061b8ac9bSSudeep Holla }; 32161b8ac9bSSudeep Holla 32261b8ac9bSSudeep Holla scmi_clk: protocol@14 { 32361b8ac9bSSudeep Holla reg = <0x14>; 32461b8ac9bSSudeep Holla #clock-cells = <1>; 32561b8ac9bSSudeep Holla }; 32661b8ac9bSSudeep Holla 32761b8ac9bSSudeep Holla scmi_sensors: protocol@15 { 32861b8ac9bSSudeep Holla reg = <0x15>; 32961b8ac9bSSudeep Holla #thermal-sensor-cells = <1>; 33061b8ac9bSSudeep Holla }; 33161b8ac9bSSudeep Holla 33261b8ac9bSSudeep Holla scmi_reset: protocol@16 { 33361b8ac9bSSudeep Holla reg = <0x16>; 33461b8ac9bSSudeep Holla #reset-cells = <1>; 33561b8ac9bSSudeep Holla }; 33661b8ac9bSSudeep Holla 33761b8ac9bSSudeep Holla scmi_voltage: protocol@17 { 33861b8ac9bSSudeep Holla reg = <0x17>; 33961b8ac9bSSudeep Holla regulators { 34061b8ac9bSSudeep Holla #address-cells = <1>; 34161b8ac9bSSudeep Holla #size-cells = <0>; 34261b8ac9bSSudeep Holla 34361b8ac9bSSudeep Holla regulator_devX: regulator@0 { 34461b8ac9bSSudeep Holla reg = <0x0>; 34561b8ac9bSSudeep Holla regulator-max-microvolt = <3300000>; 34661b8ac9bSSudeep Holla }; 34761b8ac9bSSudeep Holla 34861b8ac9bSSudeep Holla regulator_devY: regulator@9 { 34961b8ac9bSSudeep Holla reg = <0x9>; 35061b8ac9bSSudeep Holla regulator-min-microvolt = <500000>; 35161b8ac9bSSudeep Holla regulator-max-microvolt = <4200000>; 35261b8ac9bSSudeep Holla }; 35361b8ac9bSSudeep Holla }; 35461b8ac9bSSudeep Holla }; 355451d8457SCristian Marussi 356451d8457SCristian Marussi scmi_powercap: protocol@18 { 357451d8457SCristian Marussi reg = <0x18>; 358451d8457SCristian Marussi }; 35961b8ac9bSSudeep Holla }; 36061b8ac9bSSudeep Holla }; 36161b8ac9bSSudeep Holla 36261b8ac9bSSudeep Holla soc { 36361b8ac9bSSudeep Holla #address-cells = <2>; 36461b8ac9bSSudeep Holla #size-cells = <2>; 36561b8ac9bSSudeep Holla 36661b8ac9bSSudeep Holla sram@50000000 { 36761b8ac9bSSudeep Holla compatible = "mmio-sram"; 36861b8ac9bSSudeep Holla reg = <0x0 0x50000000 0x0 0x10000>; 36961b8ac9bSSudeep Holla 37061b8ac9bSSudeep Holla #address-cells = <1>; 37161b8ac9bSSudeep Holla #size-cells = <1>; 37261b8ac9bSSudeep Holla ranges = <0 0x0 0x50000000 0x10000>; 37361b8ac9bSSudeep Holla 37461b8ac9bSSudeep Holla cpu_scp_lpri0: scp-sram-section@0 { 37561b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 37661b8ac9bSSudeep Holla reg = <0x0 0x80>; 37761b8ac9bSSudeep Holla }; 37861b8ac9bSSudeep Holla 37961b8ac9bSSudeep Holla cpu_scp_lpri1: scp-sram-section@80 { 38061b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 38161b8ac9bSSudeep Holla reg = <0x80 0x80>; 38261b8ac9bSSudeep Holla }; 38361b8ac9bSSudeep Holla 38461b8ac9bSSudeep Holla cpu_scp_hpri0: scp-sram-section@100 { 38561b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 38661b8ac9bSSudeep Holla reg = <0x100 0x80>; 38761b8ac9bSSudeep Holla }; 38861b8ac9bSSudeep Holla 38961b8ac9bSSudeep Holla cpu_scp_hpri2: scp-sram-section@180 { 39061b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 39161b8ac9bSSudeep Holla reg = <0x180 0x80>; 39261b8ac9bSSudeep Holla }; 39361b8ac9bSSudeep Holla }; 39461b8ac9bSSudeep Holla }; 39561b8ac9bSSudeep Holla 39661b8ac9bSSudeep Holla - | 39761b8ac9bSSudeep Holla firmware { 39861b8ac9bSSudeep Holla scmi { 39961b8ac9bSSudeep Holla compatible = "arm,scmi-smc"; 40039bd2b6aSRob Herring shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 40161b8ac9bSSudeep Holla arm,smc-id = <0xc3000001>; 40261b8ac9bSSudeep Holla 40361b8ac9bSSudeep Holla #address-cells = <1>; 40461b8ac9bSSudeep Holla #size-cells = <0>; 40561b8ac9bSSudeep Holla 40661b8ac9bSSudeep Holla scmi_devpd1: protocol@11 { 40761b8ac9bSSudeep Holla reg = <0x11>; 40861b8ac9bSSudeep Holla #power-domain-cells = <1>; 40961b8ac9bSSudeep Holla }; 410b7d2cf7cSEtienne Carriere }; 411b7d2cf7cSEtienne Carriere }; 41261b8ac9bSSudeep Holla 413b7d2cf7cSEtienne Carriere - | 414b7d2cf7cSEtienne Carriere firmware { 415b7d2cf7cSEtienne Carriere scmi { 416b7d2cf7cSEtienne Carriere compatible = "linaro,scmi-optee"; 417b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <0>; 418b7d2cf7cSEtienne Carriere 419b7d2cf7cSEtienne Carriere #address-cells = <1>; 420b7d2cf7cSEtienne Carriere #size-cells = <0>; 421b7d2cf7cSEtienne Carriere 422b7d2cf7cSEtienne Carriere scmi_dvfs1: protocol@13 { 423b7d2cf7cSEtienne Carriere reg = <0x13>; 424b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <1>; 425b7d2cf7cSEtienne Carriere shmem = <&cpu_optee_lpri0>; 426b7d2cf7cSEtienne Carriere #clock-cells = <1>; 427b7d2cf7cSEtienne Carriere }; 428b7d2cf7cSEtienne Carriere 429b7d2cf7cSEtienne Carriere scmi_clk0: protocol@14 { 430b7d2cf7cSEtienne Carriere reg = <0x14>; 431b7d2cf7cSEtienne Carriere #clock-cells = <1>; 432b7d2cf7cSEtienne Carriere }; 433b7d2cf7cSEtienne Carriere }; 434b7d2cf7cSEtienne Carriere }; 435b7d2cf7cSEtienne Carriere 436b7d2cf7cSEtienne Carriere soc { 437b7d2cf7cSEtienne Carriere #address-cells = <2>; 438b7d2cf7cSEtienne Carriere #size-cells = <2>; 439b7d2cf7cSEtienne Carriere 440b7d2cf7cSEtienne Carriere sram@51000000 { 441b7d2cf7cSEtienne Carriere compatible = "mmio-sram"; 442b7d2cf7cSEtienne Carriere reg = <0x0 0x51000000 0x0 0x10000>; 443b7d2cf7cSEtienne Carriere 444b7d2cf7cSEtienne Carriere #address-cells = <1>; 445b7d2cf7cSEtienne Carriere #size-cells = <1>; 446b7d2cf7cSEtienne Carriere ranges = <0 0x0 0x51000000 0x10000>; 447b7d2cf7cSEtienne Carriere 448b7d2cf7cSEtienne Carriere cpu_optee_lpri0: optee-sram-section@0 { 449b7d2cf7cSEtienne Carriere compatible = "arm,scmi-shmem"; 450b7d2cf7cSEtienne Carriere reg = <0x0 0x80>; 451b7d2cf7cSEtienne Carriere }; 45261b8ac9bSSudeep Holla }; 45361b8ac9bSSudeep Holla }; 45461b8ac9bSSudeep Holla 45561b8ac9bSSudeep Holla... 456