161b8ac9bSSudeep Holla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 261b8ac9bSSudeep Holla# Copyright 2021 ARM Ltd. 361b8ac9bSSudeep Holla%YAML 1.2 461b8ac9bSSudeep Holla--- 561b8ac9bSSudeep Holla$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# 661b8ac9bSSudeep Holla$schema: http://devicetree.org/meta-schemas/core.yaml# 761b8ac9bSSudeep Holla 861b8ac9bSSudeep Hollatitle: System Control and Management Interface (SCMI) Message Protocol bindings 961b8ac9bSSudeep Holla 1061b8ac9bSSudeep Hollamaintainers: 1161b8ac9bSSudeep Holla - Sudeep Holla <sudeep.holla@arm.com> 1261b8ac9bSSudeep Holla 1361b8ac9bSSudeep Holladescription: | 1461b8ac9bSSudeep Holla The SCMI is intended to allow agents such as OSPM to manage various functions 1561b8ac9bSSudeep Holla that are provided by the hardware platform it is running on, including power 1661b8ac9bSSudeep Holla and performance functions. 1761b8ac9bSSudeep Holla 1861b8ac9bSSudeep Holla This binding is intended to define the interface the firmware implementing 1961b8ac9bSSudeep Holla the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control 2061b8ac9bSSudeep Holla and Management Interface Platform Design Document")[0] provide for OSPM in 2161b8ac9bSSudeep Holla the device tree. 2261b8ac9bSSudeep Holla 2361b8ac9bSSudeep Holla [0] https://developer.arm.com/documentation/den0056/latest 2461b8ac9bSSudeep Holla 2561b8ac9bSSudeep Hollaproperties: 2661b8ac9bSSudeep Holla $nodename: 2761b8ac9bSSudeep Holla const: scmi 2861b8ac9bSSudeep Holla 2961b8ac9bSSudeep Holla compatible: 3061b8ac9bSSudeep Holla oneOf: 3161b8ac9bSSudeep Holla - description: SCMI compliant firmware with mailbox transport 3261b8ac9bSSudeep Holla items: 3361b8ac9bSSudeep Holla - const: arm,scmi 3461b8ac9bSSudeep Holla - description: SCMI compliant firmware with ARM SMC/HVC transport 3561b8ac9bSSudeep Holla items: 3661b8ac9bSSudeep Holla - const: arm,scmi-smc 3760625667SIgor Skalkin - description: SCMI compliant firmware with SCMI Virtio transport. 3860625667SIgor Skalkin The virtio transport only supports a single device. 3960625667SIgor Skalkin items: 4060625667SIgor Skalkin - const: arm,scmi-virtio 41*b7d2cf7cSEtienne Carriere - description: SCMI compliant firmware with OP-TEE transport 42*b7d2cf7cSEtienne Carriere items: 43*b7d2cf7cSEtienne Carriere - const: linaro,scmi-optee 4461b8ac9bSSudeep Holla 4561b8ac9bSSudeep Holla interrupts: 4661b8ac9bSSudeep Holla description: 4761b8ac9bSSudeep Holla The interrupt that indicates message completion by the platform 4861b8ac9bSSudeep Holla rather than by the return of the smc call. This should not be used 4961b8ac9bSSudeep Holla except when the platform requires such behavior. 5061b8ac9bSSudeep Holla maxItems: 1 5161b8ac9bSSudeep Holla 5261b8ac9bSSudeep Holla interrupt-names: 5361b8ac9bSSudeep Holla const: a2p 5461b8ac9bSSudeep Holla 5561b8ac9bSSudeep Holla mbox-names: 5661b8ac9bSSudeep Holla description: 5761b8ac9bSSudeep Holla Specifies the mailboxes used to communicate with SCMI compliant 5861b8ac9bSSudeep Holla firmware. 5961b8ac9bSSudeep Holla items: 6061b8ac9bSSudeep Holla - const: tx 6161b8ac9bSSudeep Holla - const: rx 6261b8ac9bSSudeep Holla 6361b8ac9bSSudeep Holla mboxes: 6461b8ac9bSSudeep Holla description: 6561b8ac9bSSudeep Holla List of phandle and mailbox channel specifiers. It should contain 6661b8ac9bSSudeep Holla exactly one or two mailboxes, one for transmitting messages("tx") 6761b8ac9bSSudeep Holla and another optional for receiving the notifications("rx") if supported. 6861b8ac9bSSudeep Holla minItems: 1 6961b8ac9bSSudeep Holla maxItems: 2 7061b8ac9bSSudeep Holla 7161b8ac9bSSudeep Holla shmem: 7261b8ac9bSSudeep Holla description: 7361b8ac9bSSudeep Holla List of phandle pointing to the shared memory(SHM) area, for each 7461b8ac9bSSudeep Holla transport channel specified. 7561b8ac9bSSudeep Holla minItems: 1 7661b8ac9bSSudeep Holla maxItems: 2 7761b8ac9bSSudeep Holla 7861b8ac9bSSudeep Holla '#address-cells': 7961b8ac9bSSudeep Holla const: 1 8061b8ac9bSSudeep Holla 8161b8ac9bSSudeep Holla '#size-cells': 8261b8ac9bSSudeep Holla const: 0 8361b8ac9bSSudeep Holla 8461b8ac9bSSudeep Holla arm,smc-id: 8561b8ac9bSSudeep Holla $ref: /schemas/types.yaml#/definitions/uint32 8661b8ac9bSSudeep Holla description: 8761b8ac9bSSudeep Holla SMC id required when using smc or hvc transports 8861b8ac9bSSudeep Holla 89*b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 90*b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 91*b7d2cf7cSEtienne Carriere description: 92*b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport. 93*b7d2cf7cSEtienne Carriere 9461b8ac9bSSudeep Holla protocol@11: 9561b8ac9bSSudeep Holla type: object 9661b8ac9bSSudeep Holla properties: 9761b8ac9bSSudeep Holla reg: 9861b8ac9bSSudeep Holla const: 0x11 9961b8ac9bSSudeep Holla 10061b8ac9bSSudeep Holla '#power-domain-cells': 10161b8ac9bSSudeep Holla const: 1 10261b8ac9bSSudeep Holla 10361b8ac9bSSudeep Holla required: 10461b8ac9bSSudeep Holla - '#power-domain-cells' 10561b8ac9bSSudeep Holla 10661b8ac9bSSudeep Holla protocol@13: 10761b8ac9bSSudeep Holla type: object 10861b8ac9bSSudeep Holla properties: 10961b8ac9bSSudeep Holla reg: 11061b8ac9bSSudeep Holla const: 0x13 11161b8ac9bSSudeep Holla 11261b8ac9bSSudeep Holla '#clock-cells': 11361b8ac9bSSudeep Holla const: 1 11461b8ac9bSSudeep Holla 11561b8ac9bSSudeep Holla required: 11661b8ac9bSSudeep Holla - '#clock-cells' 11761b8ac9bSSudeep Holla 11861b8ac9bSSudeep Holla protocol@14: 11961b8ac9bSSudeep Holla type: object 12061b8ac9bSSudeep Holla properties: 12161b8ac9bSSudeep Holla reg: 12261b8ac9bSSudeep Holla const: 0x14 12361b8ac9bSSudeep Holla 12461b8ac9bSSudeep Holla '#clock-cells': 12561b8ac9bSSudeep Holla const: 1 12661b8ac9bSSudeep Holla 12761b8ac9bSSudeep Holla required: 12861b8ac9bSSudeep Holla - '#clock-cells' 12961b8ac9bSSudeep Holla 13061b8ac9bSSudeep Holla protocol@15: 13161b8ac9bSSudeep Holla type: object 13261b8ac9bSSudeep Holla properties: 13361b8ac9bSSudeep Holla reg: 13461b8ac9bSSudeep Holla const: 0x15 13561b8ac9bSSudeep Holla 13661b8ac9bSSudeep Holla '#thermal-sensor-cells': 13761b8ac9bSSudeep Holla const: 1 13861b8ac9bSSudeep Holla 13961b8ac9bSSudeep Holla required: 14061b8ac9bSSudeep Holla - '#thermal-sensor-cells' 14161b8ac9bSSudeep Holla 14261b8ac9bSSudeep Holla protocol@16: 14361b8ac9bSSudeep Holla type: object 14461b8ac9bSSudeep Holla properties: 14561b8ac9bSSudeep Holla reg: 14661b8ac9bSSudeep Holla const: 0x16 14761b8ac9bSSudeep Holla 14861b8ac9bSSudeep Holla '#reset-cells': 14961b8ac9bSSudeep Holla const: 1 15061b8ac9bSSudeep Holla 15161b8ac9bSSudeep Holla required: 15261b8ac9bSSudeep Holla - '#reset-cells' 15361b8ac9bSSudeep Holla 15461b8ac9bSSudeep Holla protocol@17: 15561b8ac9bSSudeep Holla type: object 15661b8ac9bSSudeep Holla properties: 15761b8ac9bSSudeep Holla reg: 15861b8ac9bSSudeep Holla const: 0x17 15961b8ac9bSSudeep Holla 16061b8ac9bSSudeep Holla regulators: 16161b8ac9bSSudeep Holla type: object 16261b8ac9bSSudeep Holla description: 16361b8ac9bSSudeep Holla The list of all regulators provided by this SCMI controller. 16461b8ac9bSSudeep Holla 16561b8ac9bSSudeep Holla patternProperties: 16661b8ac9bSSudeep Holla '^regulators@[0-9a-f]+$': 16761b8ac9bSSudeep Holla type: object 16861b8ac9bSSudeep Holla $ref: "../regulator/regulator.yaml#" 16961b8ac9bSSudeep Holla 17061b8ac9bSSudeep Holla properties: 17161b8ac9bSSudeep Holla reg: 17261b8ac9bSSudeep Holla maxItems: 1 17361b8ac9bSSudeep Holla description: Identifier for the voltage regulator. 17461b8ac9bSSudeep Holla 17561b8ac9bSSudeep Holla required: 17661b8ac9bSSudeep Holla - reg 17761b8ac9bSSudeep Holla 17861b8ac9bSSudeep HollaadditionalProperties: false 17961b8ac9bSSudeep Holla 18061b8ac9bSSudeep HollapatternProperties: 18161b8ac9bSSudeep Holla '^protocol@[0-9a-f]+$': 18261b8ac9bSSudeep Holla type: object 18361b8ac9bSSudeep Holla description: 18461b8ac9bSSudeep Holla Each sub-node represents a protocol supported. If the platform 18561b8ac9bSSudeep Holla supports a dedicated communication channel for a particular protocol, 18661b8ac9bSSudeep Holla then the corresponding transport properties must be present. 18760625667SIgor Skalkin The virtio transport does not support a dedicated communication channel. 18861b8ac9bSSudeep Holla 18961b8ac9bSSudeep Holla properties: 19061b8ac9bSSudeep Holla reg: 19161b8ac9bSSudeep Holla maxItems: 1 19261b8ac9bSSudeep Holla 19361b8ac9bSSudeep Holla mbox-names: 19461b8ac9bSSudeep Holla items: 19561b8ac9bSSudeep Holla - const: tx 19661b8ac9bSSudeep Holla - const: rx 19761b8ac9bSSudeep Holla 19861b8ac9bSSudeep Holla mboxes: 19961b8ac9bSSudeep Holla minItems: 1 20061b8ac9bSSudeep Holla maxItems: 2 20161b8ac9bSSudeep Holla 20261b8ac9bSSudeep Holla shmem: 20361b8ac9bSSudeep Holla minItems: 1 20461b8ac9bSSudeep Holla maxItems: 2 20561b8ac9bSSudeep Holla 206*b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 207*b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 208*b7d2cf7cSEtienne Carriere description: 209*b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport and 210*b7d2cf7cSEtienne Carriere protocol has a dedicated communication channel. 211*b7d2cf7cSEtienne Carriere 21261b8ac9bSSudeep Holla required: 21361b8ac9bSSudeep Holla - reg 21461b8ac9bSSudeep Holla 21561b8ac9bSSudeep Hollarequired: 21661b8ac9bSSudeep Holla - compatible 21761b8ac9bSSudeep Holla 21861b8ac9bSSudeep Hollaif: 21961b8ac9bSSudeep Holla properties: 22061b8ac9bSSudeep Holla compatible: 22161b8ac9bSSudeep Holla contains: 22261b8ac9bSSudeep Holla const: arm,scmi 22361b8ac9bSSudeep Hollathen: 22461b8ac9bSSudeep Holla properties: 22561b8ac9bSSudeep Holla interrupts: false 22661b8ac9bSSudeep Holla interrupt-names: false 22761b8ac9bSSudeep Holla 22861b8ac9bSSudeep Holla required: 22961b8ac9bSSudeep Holla - mboxes 23060625667SIgor Skalkin - shmem 23161b8ac9bSSudeep Holla 23261b8ac9bSSudeep Hollaelse: 23361b8ac9bSSudeep Holla if: 23461b8ac9bSSudeep Holla properties: 23561b8ac9bSSudeep Holla compatible: 23661b8ac9bSSudeep Holla contains: 23761b8ac9bSSudeep Holla const: arm,scmi-smc 23861b8ac9bSSudeep Holla then: 23961b8ac9bSSudeep Holla required: 24061b8ac9bSSudeep Holla - arm,smc-id 24160625667SIgor Skalkin - shmem 24261b8ac9bSSudeep Holla 243*b7d2cf7cSEtienne Carriere else: 244*b7d2cf7cSEtienne Carriere if: 245*b7d2cf7cSEtienne Carriere properties: 246*b7d2cf7cSEtienne Carriere compatible: 247*b7d2cf7cSEtienne Carriere contains: 248*b7d2cf7cSEtienne Carriere const: linaro,scmi-optee 249*b7d2cf7cSEtienne Carriere then: 250*b7d2cf7cSEtienne Carriere required: 251*b7d2cf7cSEtienne Carriere - linaro,optee-channel-id 252*b7d2cf7cSEtienne Carriere 25361b8ac9bSSudeep Hollaexamples: 25461b8ac9bSSudeep Holla - | 25561b8ac9bSSudeep Holla firmware { 25661b8ac9bSSudeep Holla scmi { 25761b8ac9bSSudeep Holla compatible = "arm,scmi"; 25861b8ac9bSSudeep Holla mboxes = <&mhuB 0 0>, 25961b8ac9bSSudeep Holla <&mhuB 0 1>; 26061b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 26161b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0>, 26261b8ac9bSSudeep Holla <&cpu_scp_lpri1>; 26361b8ac9bSSudeep Holla 26461b8ac9bSSudeep Holla #address-cells = <1>; 26561b8ac9bSSudeep Holla #size-cells = <0>; 26661b8ac9bSSudeep Holla 26761b8ac9bSSudeep Holla scmi_devpd: protocol@11 { 26861b8ac9bSSudeep Holla reg = <0x11>; 26961b8ac9bSSudeep Holla #power-domain-cells = <1>; 27061b8ac9bSSudeep Holla }; 27161b8ac9bSSudeep Holla 27261b8ac9bSSudeep Holla scmi_dvfs: protocol@13 { 27361b8ac9bSSudeep Holla reg = <0x13>; 27461b8ac9bSSudeep Holla #clock-cells = <1>; 27561b8ac9bSSudeep Holla 27661b8ac9bSSudeep Holla mboxes = <&mhuB 1 0>, 27761b8ac9bSSudeep Holla <&mhuB 1 1>; 27861b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 27961b8ac9bSSudeep Holla shmem = <&cpu_scp_hpri0>, 28061b8ac9bSSudeep Holla <&cpu_scp_hpri1>; 28161b8ac9bSSudeep Holla }; 28261b8ac9bSSudeep Holla 28361b8ac9bSSudeep Holla scmi_clk: protocol@14 { 28461b8ac9bSSudeep Holla reg = <0x14>; 28561b8ac9bSSudeep Holla #clock-cells = <1>; 28661b8ac9bSSudeep Holla }; 28761b8ac9bSSudeep Holla 28861b8ac9bSSudeep Holla scmi_sensors: protocol@15 { 28961b8ac9bSSudeep Holla reg = <0x15>; 29061b8ac9bSSudeep Holla #thermal-sensor-cells = <1>; 29161b8ac9bSSudeep Holla }; 29261b8ac9bSSudeep Holla 29361b8ac9bSSudeep Holla scmi_reset: protocol@16 { 29461b8ac9bSSudeep Holla reg = <0x16>; 29561b8ac9bSSudeep Holla #reset-cells = <1>; 29661b8ac9bSSudeep Holla }; 29761b8ac9bSSudeep Holla 29861b8ac9bSSudeep Holla scmi_voltage: protocol@17 { 29961b8ac9bSSudeep Holla reg = <0x17>; 30061b8ac9bSSudeep Holla regulators { 30161b8ac9bSSudeep Holla #address-cells = <1>; 30261b8ac9bSSudeep Holla #size-cells = <0>; 30361b8ac9bSSudeep Holla 30461b8ac9bSSudeep Holla regulator_devX: regulator@0 { 30561b8ac9bSSudeep Holla reg = <0x0>; 30661b8ac9bSSudeep Holla regulator-max-microvolt = <3300000>; 30761b8ac9bSSudeep Holla }; 30861b8ac9bSSudeep Holla 30961b8ac9bSSudeep Holla regulator_devY: regulator@9 { 31061b8ac9bSSudeep Holla reg = <0x9>; 31161b8ac9bSSudeep Holla regulator-min-microvolt = <500000>; 31261b8ac9bSSudeep Holla regulator-max-microvolt = <4200000>; 31361b8ac9bSSudeep Holla }; 31461b8ac9bSSudeep Holla }; 31561b8ac9bSSudeep Holla }; 31661b8ac9bSSudeep Holla }; 31761b8ac9bSSudeep Holla }; 31861b8ac9bSSudeep Holla 31961b8ac9bSSudeep Holla soc { 32061b8ac9bSSudeep Holla #address-cells = <2>; 32161b8ac9bSSudeep Holla #size-cells = <2>; 32261b8ac9bSSudeep Holla 32361b8ac9bSSudeep Holla sram@50000000 { 32461b8ac9bSSudeep Holla compatible = "mmio-sram"; 32561b8ac9bSSudeep Holla reg = <0x0 0x50000000 0x0 0x10000>; 32661b8ac9bSSudeep Holla 32761b8ac9bSSudeep Holla #address-cells = <1>; 32861b8ac9bSSudeep Holla #size-cells = <1>; 32961b8ac9bSSudeep Holla ranges = <0 0x0 0x50000000 0x10000>; 33061b8ac9bSSudeep Holla 33161b8ac9bSSudeep Holla cpu_scp_lpri0: scp-sram-section@0 { 33261b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 33361b8ac9bSSudeep Holla reg = <0x0 0x80>; 33461b8ac9bSSudeep Holla }; 33561b8ac9bSSudeep Holla 33661b8ac9bSSudeep Holla cpu_scp_lpri1: scp-sram-section@80 { 33761b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 33861b8ac9bSSudeep Holla reg = <0x80 0x80>; 33961b8ac9bSSudeep Holla }; 34061b8ac9bSSudeep Holla 34161b8ac9bSSudeep Holla cpu_scp_hpri0: scp-sram-section@100 { 34261b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 34361b8ac9bSSudeep Holla reg = <0x100 0x80>; 34461b8ac9bSSudeep Holla }; 34561b8ac9bSSudeep Holla 34661b8ac9bSSudeep Holla cpu_scp_hpri2: scp-sram-section@180 { 34761b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 34861b8ac9bSSudeep Holla reg = <0x180 0x80>; 34961b8ac9bSSudeep Holla }; 35061b8ac9bSSudeep Holla }; 35161b8ac9bSSudeep Holla }; 35261b8ac9bSSudeep Holla 35361b8ac9bSSudeep Holla - | 35461b8ac9bSSudeep Holla firmware { 35561b8ac9bSSudeep Holla scmi { 35661b8ac9bSSudeep Holla compatible = "arm,scmi-smc"; 35761b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; 35861b8ac9bSSudeep Holla arm,smc-id = <0xc3000001>; 35961b8ac9bSSudeep Holla 36061b8ac9bSSudeep Holla #address-cells = <1>; 36161b8ac9bSSudeep Holla #size-cells = <0>; 36261b8ac9bSSudeep Holla 36361b8ac9bSSudeep Holla scmi_devpd1: protocol@11 { 36461b8ac9bSSudeep Holla reg = <0x11>; 36561b8ac9bSSudeep Holla #power-domain-cells = <1>; 36661b8ac9bSSudeep Holla }; 367*b7d2cf7cSEtienne Carriere }; 368*b7d2cf7cSEtienne Carriere }; 36961b8ac9bSSudeep Holla 370*b7d2cf7cSEtienne Carriere - | 371*b7d2cf7cSEtienne Carriere firmware { 372*b7d2cf7cSEtienne Carriere scmi { 373*b7d2cf7cSEtienne Carriere compatible = "linaro,scmi-optee"; 374*b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <0>; 375*b7d2cf7cSEtienne Carriere 376*b7d2cf7cSEtienne Carriere #address-cells = <1>; 377*b7d2cf7cSEtienne Carriere #size-cells = <0>; 378*b7d2cf7cSEtienne Carriere 379*b7d2cf7cSEtienne Carriere scmi_dvfs1: protocol@13 { 380*b7d2cf7cSEtienne Carriere reg = <0x13>; 381*b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <1>; 382*b7d2cf7cSEtienne Carriere shmem = <&cpu_optee_lpri0>; 383*b7d2cf7cSEtienne Carriere #clock-cells = <1>; 384*b7d2cf7cSEtienne Carriere }; 385*b7d2cf7cSEtienne Carriere 386*b7d2cf7cSEtienne Carriere scmi_clk0: protocol@14 { 387*b7d2cf7cSEtienne Carriere reg = <0x14>; 388*b7d2cf7cSEtienne Carriere #clock-cells = <1>; 389*b7d2cf7cSEtienne Carriere }; 390*b7d2cf7cSEtienne Carriere }; 391*b7d2cf7cSEtienne Carriere }; 392*b7d2cf7cSEtienne Carriere 393*b7d2cf7cSEtienne Carriere soc { 394*b7d2cf7cSEtienne Carriere #address-cells = <2>; 395*b7d2cf7cSEtienne Carriere #size-cells = <2>; 396*b7d2cf7cSEtienne Carriere 397*b7d2cf7cSEtienne Carriere sram@51000000 { 398*b7d2cf7cSEtienne Carriere compatible = "mmio-sram"; 399*b7d2cf7cSEtienne Carriere reg = <0x0 0x51000000 0x0 0x10000>; 400*b7d2cf7cSEtienne Carriere 401*b7d2cf7cSEtienne Carriere #address-cells = <1>; 402*b7d2cf7cSEtienne Carriere #size-cells = <1>; 403*b7d2cf7cSEtienne Carriere ranges = <0 0x0 0x51000000 0x10000>; 404*b7d2cf7cSEtienne Carriere 405*b7d2cf7cSEtienne Carriere cpu_optee_lpri0: optee-sram-section@0 { 406*b7d2cf7cSEtienne Carriere compatible = "arm,scmi-shmem"; 407*b7d2cf7cSEtienne Carriere reg = <0x0 0x80>; 408*b7d2cf7cSEtienne Carriere }; 40961b8ac9bSSudeep Holla }; 41061b8ac9bSSudeep Holla }; 41161b8ac9bSSudeep Holla 41261b8ac9bSSudeep Holla... 413