161b8ac9bSSudeep Holla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 261b8ac9bSSudeep Holla# Copyright 2021 ARM Ltd. 361b8ac9bSSudeep Holla%YAML 1.2 461b8ac9bSSudeep Holla--- 561b8ac9bSSudeep Holla$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# 661b8ac9bSSudeep Holla$schema: http://devicetree.org/meta-schemas/core.yaml# 761b8ac9bSSudeep Holla 884e85359SKrzysztof Kozlowskititle: System Control and Management Interface (SCMI) Message Protocol 961b8ac9bSSudeep Holla 1061b8ac9bSSudeep Hollamaintainers: 1161b8ac9bSSudeep Holla - Sudeep Holla <sudeep.holla@arm.com> 1261b8ac9bSSudeep Holla 1361b8ac9bSSudeep Holladescription: | 1461b8ac9bSSudeep Holla The SCMI is intended to allow agents such as OSPM to manage various functions 1561b8ac9bSSudeep Holla that are provided by the hardware platform it is running on, including power 1661b8ac9bSSudeep Holla and performance functions. 1761b8ac9bSSudeep Holla 1861b8ac9bSSudeep Holla This binding is intended to define the interface the firmware implementing 1961b8ac9bSSudeep Holla the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control 2061b8ac9bSSudeep Holla and Management Interface Platform Design Document")[0] provide for OSPM in 2161b8ac9bSSudeep Holla the device tree. 2261b8ac9bSSudeep Holla 2361b8ac9bSSudeep Holla [0] https://developer.arm.com/documentation/den0056/latest 2461b8ac9bSSudeep Holla 2561b8ac9bSSudeep Hollaproperties: 2661b8ac9bSSudeep Holla $nodename: 2761b8ac9bSSudeep Holla const: scmi 2861b8ac9bSSudeep Holla 2961b8ac9bSSudeep Holla compatible: 3061b8ac9bSSudeep Holla oneOf: 3161b8ac9bSSudeep Holla - description: SCMI compliant firmware with mailbox transport 3261b8ac9bSSudeep Holla items: 3361b8ac9bSSudeep Holla - const: arm,scmi 3461b8ac9bSSudeep Holla - description: SCMI compliant firmware with ARM SMC/HVC transport 3561b8ac9bSSudeep Holla items: 3661b8ac9bSSudeep Holla - const: arm,scmi-smc 3760625667SIgor Skalkin - description: SCMI compliant firmware with SCMI Virtio transport. 3860625667SIgor Skalkin The virtio transport only supports a single device. 3960625667SIgor Skalkin items: 4060625667SIgor Skalkin - const: arm,scmi-virtio 41b7d2cf7cSEtienne Carriere - description: SCMI compliant firmware with OP-TEE transport 42b7d2cf7cSEtienne Carriere items: 43b7d2cf7cSEtienne Carriere - const: linaro,scmi-optee 4461b8ac9bSSudeep Holla 4561b8ac9bSSudeep Holla interrupts: 4661b8ac9bSSudeep Holla description: 4761b8ac9bSSudeep Holla The interrupt that indicates message completion by the platform 4861b8ac9bSSudeep Holla rather than by the return of the smc call. This should not be used 4961b8ac9bSSudeep Holla except when the platform requires such behavior. 5061b8ac9bSSudeep Holla maxItems: 1 5161b8ac9bSSudeep Holla 5261b8ac9bSSudeep Holla interrupt-names: 5361b8ac9bSSudeep Holla const: a2p 5461b8ac9bSSudeep Holla 5561b8ac9bSSudeep Holla mbox-names: 5661b8ac9bSSudeep Holla description: 5761b8ac9bSSudeep Holla Specifies the mailboxes used to communicate with SCMI compliant 5861b8ac9bSSudeep Holla firmware. 59*92ac94f7SCristian Marussi oneOf: 60*92ac94f7SCristian Marussi - items: 6161b8ac9bSSudeep Holla - const: tx 6261b8ac9bSSudeep Holla - const: rx 63*92ac94f7SCristian Marussi minItems: 1 64*92ac94f7SCristian Marussi - items: 65*92ac94f7SCristian Marussi - const: tx 66*92ac94f7SCristian Marussi - const: tx_reply 67*92ac94f7SCristian Marussi - const: rx 68*92ac94f7SCristian Marussi minItems: 2 6961b8ac9bSSudeep Holla 7061b8ac9bSSudeep Holla mboxes: 7161b8ac9bSSudeep Holla description: 7261b8ac9bSSudeep Holla List of phandle and mailbox channel specifiers. It should contain 73*92ac94f7SCristian Marussi exactly one, two or three mailboxes; the first one or two for transmitting 74*92ac94f7SCristian Marussi messages ("tx") and another optional ("rx") for receiving notifications 75*92ac94f7SCristian Marussi and delayed responses, if supported by the platform. 76*92ac94f7SCristian Marussi The number of mailboxes needed for transmitting messages depends on the 77*92ac94f7SCristian Marussi type of channels exposed by the specific underlying mailbox controller; 78*92ac94f7SCristian Marussi one single channel descriptor is enough if such channel is bidirectional, 79*92ac94f7SCristian Marussi while two channel descriptors are needed to represent the SCMI ("tx") 80*92ac94f7SCristian Marussi channel if the underlying mailbox channels are of unidirectional type. 81*92ac94f7SCristian Marussi The effective combination in numbers of mboxes and shmem descriptors let 82*92ac94f7SCristian Marussi the SCMI subsystem determine unambiguosly which type of SCMI channels are 83*92ac94f7SCristian Marussi made available by the underlying mailbox controller and how to use them. 84*92ac94f7SCristian Marussi 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel 85*92ac94f7SCristian Marussi 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels 86*92ac94f7SCristian Marussi 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels 87*92ac94f7SCristian Marussi 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels 88*92ac94f7SCristian Marussi Any other combination of mboxes and shmem is invalid. 8961b8ac9bSSudeep Holla minItems: 1 90*92ac94f7SCristian Marussi maxItems: 3 9161b8ac9bSSudeep Holla 9261b8ac9bSSudeep Holla shmem: 9361b8ac9bSSudeep Holla description: 9461b8ac9bSSudeep Holla List of phandle pointing to the shared memory(SHM) area, for each 9561b8ac9bSSudeep Holla transport channel specified. 9661b8ac9bSSudeep Holla minItems: 1 9761b8ac9bSSudeep Holla maxItems: 2 9861b8ac9bSSudeep Holla 9961b8ac9bSSudeep Holla '#address-cells': 10061b8ac9bSSudeep Holla const: 1 10161b8ac9bSSudeep Holla 10261b8ac9bSSudeep Holla '#size-cells': 10361b8ac9bSSudeep Holla const: 0 10461b8ac9bSSudeep Holla 1050539884cSCristian Marussi atomic-threshold-us: 1060539884cSCristian Marussi description: 1070539884cSCristian Marussi An optional time value, expressed in microseconds, representing, on this 1080539884cSCristian Marussi platform, the threshold above which any SCMI command, advertised to have 1090539884cSCristian Marussi an higher-than-threshold execution latency, should not be considered for 1100539884cSCristian Marussi atomic mode of operation, even if requested. 1110539884cSCristian Marussi default: 0 1120539884cSCristian Marussi 11361b8ac9bSSudeep Holla arm,smc-id: 11461b8ac9bSSudeep Holla $ref: /schemas/types.yaml#/definitions/uint32 11561b8ac9bSSudeep Holla description: 11661b8ac9bSSudeep Holla SMC id required when using smc or hvc transports 11761b8ac9bSSudeep Holla 118b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 119b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 120b7d2cf7cSEtienne Carriere description: 121b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport. 122b7d2cf7cSEtienne Carriere 12361b8ac9bSSudeep Holla protocol@11: 124df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 125df4fdd0dSRob Herring unevaluatedProperties: false 126df4fdd0dSRob Herring 12761b8ac9bSSudeep Holla properties: 12861b8ac9bSSudeep Holla reg: 12961b8ac9bSSudeep Holla const: 0x11 13061b8ac9bSSudeep Holla 13161b8ac9bSSudeep Holla '#power-domain-cells': 13261b8ac9bSSudeep Holla const: 1 13361b8ac9bSSudeep Holla 13461b8ac9bSSudeep Holla required: 13561b8ac9bSSudeep Holla - '#power-domain-cells' 13661b8ac9bSSudeep Holla 13761b8ac9bSSudeep Holla protocol@13: 138df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 139df4fdd0dSRob Herring unevaluatedProperties: false 140df4fdd0dSRob Herring 14161b8ac9bSSudeep Holla properties: 14261b8ac9bSSudeep Holla reg: 14361b8ac9bSSudeep Holla const: 0x13 14461b8ac9bSSudeep Holla 14561b8ac9bSSudeep Holla '#clock-cells': 14661b8ac9bSSudeep Holla const: 1 14761b8ac9bSSudeep Holla 14861b8ac9bSSudeep Holla required: 14961b8ac9bSSudeep Holla - '#clock-cells' 15061b8ac9bSSudeep Holla 15161b8ac9bSSudeep Holla protocol@14: 152df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 153df4fdd0dSRob Herring unevaluatedProperties: false 154df4fdd0dSRob Herring 15561b8ac9bSSudeep Holla properties: 15661b8ac9bSSudeep Holla reg: 15761b8ac9bSSudeep Holla const: 0x14 15861b8ac9bSSudeep Holla 15961b8ac9bSSudeep Holla '#clock-cells': 16061b8ac9bSSudeep Holla const: 1 16161b8ac9bSSudeep Holla 16261b8ac9bSSudeep Holla required: 16361b8ac9bSSudeep Holla - '#clock-cells' 16461b8ac9bSSudeep Holla 16561b8ac9bSSudeep Holla protocol@15: 166df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 167df4fdd0dSRob Herring unevaluatedProperties: false 168df4fdd0dSRob Herring 16961b8ac9bSSudeep Holla properties: 17061b8ac9bSSudeep Holla reg: 17161b8ac9bSSudeep Holla const: 0x15 17261b8ac9bSSudeep Holla 17361b8ac9bSSudeep Holla '#thermal-sensor-cells': 17461b8ac9bSSudeep Holla const: 1 17561b8ac9bSSudeep Holla 17661b8ac9bSSudeep Holla required: 17761b8ac9bSSudeep Holla - '#thermal-sensor-cells' 17861b8ac9bSSudeep Holla 17961b8ac9bSSudeep Holla protocol@16: 180df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 181df4fdd0dSRob Herring unevaluatedProperties: false 182df4fdd0dSRob Herring 18361b8ac9bSSudeep Holla properties: 18461b8ac9bSSudeep Holla reg: 18561b8ac9bSSudeep Holla const: 0x16 18661b8ac9bSSudeep Holla 18761b8ac9bSSudeep Holla '#reset-cells': 18861b8ac9bSSudeep Holla const: 1 18961b8ac9bSSudeep Holla 19061b8ac9bSSudeep Holla required: 19161b8ac9bSSudeep Holla - '#reset-cells' 19261b8ac9bSSudeep Holla 19361b8ac9bSSudeep Holla protocol@17: 194df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 195df4fdd0dSRob Herring unevaluatedProperties: false 196df4fdd0dSRob Herring 19761b8ac9bSSudeep Holla properties: 19861b8ac9bSSudeep Holla reg: 19961b8ac9bSSudeep Holla const: 0x17 20061b8ac9bSSudeep Holla 20161b8ac9bSSudeep Holla regulators: 20261b8ac9bSSudeep Holla type: object 203df4fdd0dSRob Herring additionalProperties: false 20461b8ac9bSSudeep Holla description: 20561b8ac9bSSudeep Holla The list of all regulators provided by this SCMI controller. 20661b8ac9bSSudeep Holla 207df4fdd0dSRob Herring properties: 208df4fdd0dSRob Herring '#address-cells': 209df4fdd0dSRob Herring const: 1 210df4fdd0dSRob Herring 211df4fdd0dSRob Herring '#size-cells': 212df4fdd0dSRob Herring const: 0 213df4fdd0dSRob Herring 21461b8ac9bSSudeep Holla patternProperties: 215df4fdd0dSRob Herring '^regulator@[0-9a-f]+$': 21661b8ac9bSSudeep Holla type: object 21761b8ac9bSSudeep Holla $ref: "../regulator/regulator.yaml#" 218df4fdd0dSRob Herring unevaluatedProperties: false 21961b8ac9bSSudeep Holla 22061b8ac9bSSudeep Holla properties: 22161b8ac9bSSudeep Holla reg: 22261b8ac9bSSudeep Holla maxItems: 1 22361b8ac9bSSudeep Holla description: Identifier for the voltage regulator. 22461b8ac9bSSudeep Holla 22561b8ac9bSSudeep Holla required: 22661b8ac9bSSudeep Holla - reg 22761b8ac9bSSudeep Holla 228451d8457SCristian Marussi protocol@18: 229df4fdd0dSRob Herring $ref: '#/$defs/protocol-node' 230df4fdd0dSRob Herring unevaluatedProperties: false 231df4fdd0dSRob Herring 232451d8457SCristian Marussi properties: 233451d8457SCristian Marussi reg: 234451d8457SCristian Marussi const: 0x18 235451d8457SCristian Marussi 23661b8ac9bSSudeep HollaadditionalProperties: false 23761b8ac9bSSudeep Holla 238df4fdd0dSRob Herring$defs: 239df4fdd0dSRob Herring protocol-node: 24061b8ac9bSSudeep Holla type: object 24161b8ac9bSSudeep Holla description: 24261b8ac9bSSudeep Holla Each sub-node represents a protocol supported. If the platform 24361b8ac9bSSudeep Holla supports a dedicated communication channel for a particular protocol, 24461b8ac9bSSudeep Holla then the corresponding transport properties must be present. 24560625667SIgor Skalkin The virtio transport does not support a dedicated communication channel. 24661b8ac9bSSudeep Holla 24761b8ac9bSSudeep Holla properties: 24861b8ac9bSSudeep Holla reg: 24961b8ac9bSSudeep Holla maxItems: 1 25061b8ac9bSSudeep Holla 25161b8ac9bSSudeep Holla mbox-names: 252*92ac94f7SCristian Marussi oneOf: 253*92ac94f7SCristian Marussi - items: 25461b8ac9bSSudeep Holla - const: tx 25561b8ac9bSSudeep Holla - const: rx 256*92ac94f7SCristian Marussi minItems: 1 257*92ac94f7SCristian Marussi - items: 258*92ac94f7SCristian Marussi - const: tx 259*92ac94f7SCristian Marussi - const: tx_reply 260*92ac94f7SCristian Marussi - const: rx 261*92ac94f7SCristian Marussi minItems: 2 26261b8ac9bSSudeep Holla 26361b8ac9bSSudeep Holla mboxes: 26461b8ac9bSSudeep Holla minItems: 1 265*92ac94f7SCristian Marussi maxItems: 3 26661b8ac9bSSudeep Holla 26761b8ac9bSSudeep Holla shmem: 26861b8ac9bSSudeep Holla minItems: 1 26961b8ac9bSSudeep Holla maxItems: 2 27061b8ac9bSSudeep Holla 271b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 272b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 273b7d2cf7cSEtienne Carriere description: 274b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport and 275b7d2cf7cSEtienne Carriere protocol has a dedicated communication channel. 276b7d2cf7cSEtienne Carriere 27761b8ac9bSSudeep Holla required: 27861b8ac9bSSudeep Holla - reg 27961b8ac9bSSudeep Holla 28061b8ac9bSSudeep Hollarequired: 28161b8ac9bSSudeep Holla - compatible 28261b8ac9bSSudeep Holla 28361b8ac9bSSudeep Hollaif: 28461b8ac9bSSudeep Holla properties: 28561b8ac9bSSudeep Holla compatible: 28661b8ac9bSSudeep Holla contains: 28761b8ac9bSSudeep Holla const: arm,scmi 28861b8ac9bSSudeep Hollathen: 28961b8ac9bSSudeep Holla properties: 29061b8ac9bSSudeep Holla interrupts: false 29161b8ac9bSSudeep Holla interrupt-names: false 29261b8ac9bSSudeep Holla 29361b8ac9bSSudeep Holla required: 29461b8ac9bSSudeep Holla - mboxes 29560625667SIgor Skalkin - shmem 29661b8ac9bSSudeep Holla 29761b8ac9bSSudeep Hollaelse: 29861b8ac9bSSudeep Holla if: 29961b8ac9bSSudeep Holla properties: 30061b8ac9bSSudeep Holla compatible: 30161b8ac9bSSudeep Holla contains: 30261b8ac9bSSudeep Holla const: arm,scmi-smc 30361b8ac9bSSudeep Holla then: 30461b8ac9bSSudeep Holla required: 30561b8ac9bSSudeep Holla - arm,smc-id 30660625667SIgor Skalkin - shmem 30761b8ac9bSSudeep Holla 308b7d2cf7cSEtienne Carriere else: 309b7d2cf7cSEtienne Carriere if: 310b7d2cf7cSEtienne Carriere properties: 311b7d2cf7cSEtienne Carriere compatible: 312b7d2cf7cSEtienne Carriere contains: 313b7d2cf7cSEtienne Carriere const: linaro,scmi-optee 314b7d2cf7cSEtienne Carriere then: 315b7d2cf7cSEtienne Carriere required: 316b7d2cf7cSEtienne Carriere - linaro,optee-channel-id 317b7d2cf7cSEtienne Carriere 31861b8ac9bSSudeep Hollaexamples: 31961b8ac9bSSudeep Holla - | 32061b8ac9bSSudeep Holla firmware { 32161b8ac9bSSudeep Holla scmi { 32261b8ac9bSSudeep Holla compatible = "arm,scmi"; 32361b8ac9bSSudeep Holla mboxes = <&mhuB 0 0>, 32461b8ac9bSSudeep Holla <&mhuB 0 1>; 32561b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 32661b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0>, 32761b8ac9bSSudeep Holla <&cpu_scp_lpri1>; 32861b8ac9bSSudeep Holla 32961b8ac9bSSudeep Holla #address-cells = <1>; 33061b8ac9bSSudeep Holla #size-cells = <0>; 33161b8ac9bSSudeep Holla 3320539884cSCristian Marussi atomic-threshold-us = <10000>; 3330539884cSCristian Marussi 33461b8ac9bSSudeep Holla scmi_devpd: protocol@11 { 33561b8ac9bSSudeep Holla reg = <0x11>; 33661b8ac9bSSudeep Holla #power-domain-cells = <1>; 33761b8ac9bSSudeep Holla }; 33861b8ac9bSSudeep Holla 33961b8ac9bSSudeep Holla scmi_dvfs: protocol@13 { 34061b8ac9bSSudeep Holla reg = <0x13>; 34161b8ac9bSSudeep Holla #clock-cells = <1>; 34261b8ac9bSSudeep Holla 34361b8ac9bSSudeep Holla mboxes = <&mhuB 1 0>, 34461b8ac9bSSudeep Holla <&mhuB 1 1>; 34561b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 34661b8ac9bSSudeep Holla shmem = <&cpu_scp_hpri0>, 34761b8ac9bSSudeep Holla <&cpu_scp_hpri1>; 34861b8ac9bSSudeep Holla }; 34961b8ac9bSSudeep Holla 35061b8ac9bSSudeep Holla scmi_clk: protocol@14 { 35161b8ac9bSSudeep Holla reg = <0x14>; 35261b8ac9bSSudeep Holla #clock-cells = <1>; 35361b8ac9bSSudeep Holla }; 35461b8ac9bSSudeep Holla 35561b8ac9bSSudeep Holla scmi_sensors: protocol@15 { 35661b8ac9bSSudeep Holla reg = <0x15>; 35761b8ac9bSSudeep Holla #thermal-sensor-cells = <1>; 35861b8ac9bSSudeep Holla }; 35961b8ac9bSSudeep Holla 36061b8ac9bSSudeep Holla scmi_reset: protocol@16 { 36161b8ac9bSSudeep Holla reg = <0x16>; 36261b8ac9bSSudeep Holla #reset-cells = <1>; 36361b8ac9bSSudeep Holla }; 36461b8ac9bSSudeep Holla 36561b8ac9bSSudeep Holla scmi_voltage: protocol@17 { 36661b8ac9bSSudeep Holla reg = <0x17>; 36761b8ac9bSSudeep Holla regulators { 36861b8ac9bSSudeep Holla #address-cells = <1>; 36961b8ac9bSSudeep Holla #size-cells = <0>; 37061b8ac9bSSudeep Holla 37161b8ac9bSSudeep Holla regulator_devX: regulator@0 { 37261b8ac9bSSudeep Holla reg = <0x0>; 37361b8ac9bSSudeep Holla regulator-max-microvolt = <3300000>; 37461b8ac9bSSudeep Holla }; 37561b8ac9bSSudeep Holla 37661b8ac9bSSudeep Holla regulator_devY: regulator@9 { 37761b8ac9bSSudeep Holla reg = <0x9>; 37861b8ac9bSSudeep Holla regulator-min-microvolt = <500000>; 37961b8ac9bSSudeep Holla regulator-max-microvolt = <4200000>; 38061b8ac9bSSudeep Holla }; 38161b8ac9bSSudeep Holla }; 38261b8ac9bSSudeep Holla }; 383451d8457SCristian Marussi 384451d8457SCristian Marussi scmi_powercap: protocol@18 { 385451d8457SCristian Marussi reg = <0x18>; 386451d8457SCristian Marussi }; 38761b8ac9bSSudeep Holla }; 38861b8ac9bSSudeep Holla }; 38961b8ac9bSSudeep Holla 39061b8ac9bSSudeep Holla soc { 39161b8ac9bSSudeep Holla #address-cells = <2>; 39261b8ac9bSSudeep Holla #size-cells = <2>; 39361b8ac9bSSudeep Holla 39461b8ac9bSSudeep Holla sram@50000000 { 39561b8ac9bSSudeep Holla compatible = "mmio-sram"; 39661b8ac9bSSudeep Holla reg = <0x0 0x50000000 0x0 0x10000>; 39761b8ac9bSSudeep Holla 39861b8ac9bSSudeep Holla #address-cells = <1>; 39961b8ac9bSSudeep Holla #size-cells = <1>; 40061b8ac9bSSudeep Holla ranges = <0 0x0 0x50000000 0x10000>; 40161b8ac9bSSudeep Holla 40261b8ac9bSSudeep Holla cpu_scp_lpri0: scp-sram-section@0 { 40361b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 40461b8ac9bSSudeep Holla reg = <0x0 0x80>; 40561b8ac9bSSudeep Holla }; 40661b8ac9bSSudeep Holla 40761b8ac9bSSudeep Holla cpu_scp_lpri1: scp-sram-section@80 { 40861b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 40961b8ac9bSSudeep Holla reg = <0x80 0x80>; 41061b8ac9bSSudeep Holla }; 41161b8ac9bSSudeep Holla 41261b8ac9bSSudeep Holla cpu_scp_hpri0: scp-sram-section@100 { 41361b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 41461b8ac9bSSudeep Holla reg = <0x100 0x80>; 41561b8ac9bSSudeep Holla }; 41661b8ac9bSSudeep Holla 41761b8ac9bSSudeep Holla cpu_scp_hpri2: scp-sram-section@180 { 41861b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 41961b8ac9bSSudeep Holla reg = <0x180 0x80>; 42061b8ac9bSSudeep Holla }; 42161b8ac9bSSudeep Holla }; 42261b8ac9bSSudeep Holla }; 42361b8ac9bSSudeep Holla 42461b8ac9bSSudeep Holla - | 42561b8ac9bSSudeep Holla firmware { 42661b8ac9bSSudeep Holla scmi { 42761b8ac9bSSudeep Holla compatible = "arm,scmi-smc"; 42839bd2b6aSRob Herring shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 42961b8ac9bSSudeep Holla arm,smc-id = <0xc3000001>; 43061b8ac9bSSudeep Holla 43161b8ac9bSSudeep Holla #address-cells = <1>; 43261b8ac9bSSudeep Holla #size-cells = <0>; 43361b8ac9bSSudeep Holla 43461b8ac9bSSudeep Holla scmi_devpd1: protocol@11 { 43561b8ac9bSSudeep Holla reg = <0x11>; 43661b8ac9bSSudeep Holla #power-domain-cells = <1>; 43761b8ac9bSSudeep Holla }; 438b7d2cf7cSEtienne Carriere }; 439b7d2cf7cSEtienne Carriere }; 44061b8ac9bSSudeep Holla 441b7d2cf7cSEtienne Carriere - | 442b7d2cf7cSEtienne Carriere firmware { 443b7d2cf7cSEtienne Carriere scmi { 444b7d2cf7cSEtienne Carriere compatible = "linaro,scmi-optee"; 445b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <0>; 446b7d2cf7cSEtienne Carriere 447b7d2cf7cSEtienne Carriere #address-cells = <1>; 448b7d2cf7cSEtienne Carriere #size-cells = <0>; 449b7d2cf7cSEtienne Carriere 450b7d2cf7cSEtienne Carriere scmi_dvfs1: protocol@13 { 451b7d2cf7cSEtienne Carriere reg = <0x13>; 452b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <1>; 453b7d2cf7cSEtienne Carriere shmem = <&cpu_optee_lpri0>; 454b7d2cf7cSEtienne Carriere #clock-cells = <1>; 455b7d2cf7cSEtienne Carriere }; 456b7d2cf7cSEtienne Carriere 457b7d2cf7cSEtienne Carriere scmi_clk0: protocol@14 { 458b7d2cf7cSEtienne Carriere reg = <0x14>; 459b7d2cf7cSEtienne Carriere #clock-cells = <1>; 460b7d2cf7cSEtienne Carriere }; 461b7d2cf7cSEtienne Carriere }; 462b7d2cf7cSEtienne Carriere }; 463b7d2cf7cSEtienne Carriere 464b7d2cf7cSEtienne Carriere soc { 465b7d2cf7cSEtienne Carriere #address-cells = <2>; 466b7d2cf7cSEtienne Carriere #size-cells = <2>; 467b7d2cf7cSEtienne Carriere 468b7d2cf7cSEtienne Carriere sram@51000000 { 469b7d2cf7cSEtienne Carriere compatible = "mmio-sram"; 470b7d2cf7cSEtienne Carriere reg = <0x0 0x51000000 0x0 0x10000>; 471b7d2cf7cSEtienne Carriere 472b7d2cf7cSEtienne Carriere #address-cells = <1>; 473b7d2cf7cSEtienne Carriere #size-cells = <1>; 474b7d2cf7cSEtienne Carriere ranges = <0 0x0 0x51000000 0x10000>; 475b7d2cf7cSEtienne Carriere 476b7d2cf7cSEtienne Carriere cpu_optee_lpri0: optee-sram-section@0 { 477b7d2cf7cSEtienne Carriere compatible = "arm,scmi-shmem"; 478b7d2cf7cSEtienne Carriere reg = <0x0 0x80>; 479b7d2cf7cSEtienne Carriere }; 48061b8ac9bSSudeep Holla }; 48161b8ac9bSSudeep Holla }; 48261b8ac9bSSudeep Holla 48361b8ac9bSSudeep Holla... 484