161b8ac9bSSudeep Holla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 261b8ac9bSSudeep Holla# Copyright 2021 ARM Ltd. 361b8ac9bSSudeep Holla%YAML 1.2 461b8ac9bSSudeep Holla--- 561b8ac9bSSudeep Holla$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml# 661b8ac9bSSudeep Holla$schema: http://devicetree.org/meta-schemas/core.yaml# 761b8ac9bSSudeep Holla 861b8ac9bSSudeep Hollatitle: System Control and Management Interface (SCMI) Message Protocol bindings 961b8ac9bSSudeep Holla 1061b8ac9bSSudeep Hollamaintainers: 1161b8ac9bSSudeep Holla - Sudeep Holla <sudeep.holla@arm.com> 1261b8ac9bSSudeep Holla 1361b8ac9bSSudeep Holladescription: | 1461b8ac9bSSudeep Holla The SCMI is intended to allow agents such as OSPM to manage various functions 1561b8ac9bSSudeep Holla that are provided by the hardware platform it is running on, including power 1661b8ac9bSSudeep Holla and performance functions. 1761b8ac9bSSudeep Holla 1861b8ac9bSSudeep Holla This binding is intended to define the interface the firmware implementing 1961b8ac9bSSudeep Holla the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control 2061b8ac9bSSudeep Holla and Management Interface Platform Design Document")[0] provide for OSPM in 2161b8ac9bSSudeep Holla the device tree. 2261b8ac9bSSudeep Holla 2361b8ac9bSSudeep Holla [0] https://developer.arm.com/documentation/den0056/latest 2461b8ac9bSSudeep Holla 2561b8ac9bSSudeep Hollaproperties: 2661b8ac9bSSudeep Holla $nodename: 2761b8ac9bSSudeep Holla const: scmi 2861b8ac9bSSudeep Holla 2961b8ac9bSSudeep Holla compatible: 3061b8ac9bSSudeep Holla oneOf: 3161b8ac9bSSudeep Holla - description: SCMI compliant firmware with mailbox transport 3261b8ac9bSSudeep Holla items: 3361b8ac9bSSudeep Holla - const: arm,scmi 3461b8ac9bSSudeep Holla - description: SCMI compliant firmware with ARM SMC/HVC transport 3561b8ac9bSSudeep Holla items: 3661b8ac9bSSudeep Holla - const: arm,scmi-smc 3760625667SIgor Skalkin - description: SCMI compliant firmware with SCMI Virtio transport. 3860625667SIgor Skalkin The virtio transport only supports a single device. 3960625667SIgor Skalkin items: 4060625667SIgor Skalkin - const: arm,scmi-virtio 41b7d2cf7cSEtienne Carriere - description: SCMI compliant firmware with OP-TEE transport 42b7d2cf7cSEtienne Carriere items: 43b7d2cf7cSEtienne Carriere - const: linaro,scmi-optee 4461b8ac9bSSudeep Holla 4561b8ac9bSSudeep Holla interrupts: 4661b8ac9bSSudeep Holla description: 4761b8ac9bSSudeep Holla The interrupt that indicates message completion by the platform 4861b8ac9bSSudeep Holla rather than by the return of the smc call. This should not be used 4961b8ac9bSSudeep Holla except when the platform requires such behavior. 5061b8ac9bSSudeep Holla maxItems: 1 5161b8ac9bSSudeep Holla 5261b8ac9bSSudeep Holla interrupt-names: 5361b8ac9bSSudeep Holla const: a2p 5461b8ac9bSSudeep Holla 5561b8ac9bSSudeep Holla mbox-names: 5661b8ac9bSSudeep Holla description: 5761b8ac9bSSudeep Holla Specifies the mailboxes used to communicate with SCMI compliant 5861b8ac9bSSudeep Holla firmware. 5961b8ac9bSSudeep Holla items: 6061b8ac9bSSudeep Holla - const: tx 6161b8ac9bSSudeep Holla - const: rx 6261b8ac9bSSudeep Holla 6361b8ac9bSSudeep Holla mboxes: 6461b8ac9bSSudeep Holla description: 6561b8ac9bSSudeep Holla List of phandle and mailbox channel specifiers. It should contain 6661b8ac9bSSudeep Holla exactly one or two mailboxes, one for transmitting messages("tx") 6761b8ac9bSSudeep Holla and another optional for receiving the notifications("rx") if supported. 6861b8ac9bSSudeep Holla minItems: 1 6961b8ac9bSSudeep Holla maxItems: 2 7061b8ac9bSSudeep Holla 7161b8ac9bSSudeep Holla shmem: 7261b8ac9bSSudeep Holla description: 7361b8ac9bSSudeep Holla List of phandle pointing to the shared memory(SHM) area, for each 7461b8ac9bSSudeep Holla transport channel specified. 7561b8ac9bSSudeep Holla minItems: 1 7661b8ac9bSSudeep Holla maxItems: 2 7761b8ac9bSSudeep Holla 7861b8ac9bSSudeep Holla '#address-cells': 7961b8ac9bSSudeep Holla const: 1 8061b8ac9bSSudeep Holla 8161b8ac9bSSudeep Holla '#size-cells': 8261b8ac9bSSudeep Holla const: 0 8361b8ac9bSSudeep Holla 84*0539884cSCristian Marussi atomic-threshold-us: 85*0539884cSCristian Marussi description: 86*0539884cSCristian Marussi An optional time value, expressed in microseconds, representing, on this 87*0539884cSCristian Marussi platform, the threshold above which any SCMI command, advertised to have 88*0539884cSCristian Marussi an higher-than-threshold execution latency, should not be considered for 89*0539884cSCristian Marussi atomic mode of operation, even if requested. 90*0539884cSCristian Marussi default: 0 91*0539884cSCristian Marussi 9261b8ac9bSSudeep Holla arm,smc-id: 9361b8ac9bSSudeep Holla $ref: /schemas/types.yaml#/definitions/uint32 9461b8ac9bSSudeep Holla description: 9561b8ac9bSSudeep Holla SMC id required when using smc or hvc transports 9661b8ac9bSSudeep Holla 97b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 98b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 99b7d2cf7cSEtienne Carriere description: 100b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport. 101b7d2cf7cSEtienne Carriere 10261b8ac9bSSudeep Holla protocol@11: 10361b8ac9bSSudeep Holla type: object 10461b8ac9bSSudeep Holla properties: 10561b8ac9bSSudeep Holla reg: 10661b8ac9bSSudeep Holla const: 0x11 10761b8ac9bSSudeep Holla 10861b8ac9bSSudeep Holla '#power-domain-cells': 10961b8ac9bSSudeep Holla const: 1 11061b8ac9bSSudeep Holla 11161b8ac9bSSudeep Holla required: 11261b8ac9bSSudeep Holla - '#power-domain-cells' 11361b8ac9bSSudeep Holla 11461b8ac9bSSudeep Holla protocol@13: 11561b8ac9bSSudeep Holla type: object 11661b8ac9bSSudeep Holla properties: 11761b8ac9bSSudeep Holla reg: 11861b8ac9bSSudeep Holla const: 0x13 11961b8ac9bSSudeep Holla 12061b8ac9bSSudeep Holla '#clock-cells': 12161b8ac9bSSudeep Holla const: 1 12261b8ac9bSSudeep Holla 12361b8ac9bSSudeep Holla required: 12461b8ac9bSSudeep Holla - '#clock-cells' 12561b8ac9bSSudeep Holla 12661b8ac9bSSudeep Holla protocol@14: 12761b8ac9bSSudeep Holla type: object 12861b8ac9bSSudeep Holla properties: 12961b8ac9bSSudeep Holla reg: 13061b8ac9bSSudeep Holla const: 0x14 13161b8ac9bSSudeep Holla 13261b8ac9bSSudeep Holla '#clock-cells': 13361b8ac9bSSudeep Holla const: 1 13461b8ac9bSSudeep Holla 13561b8ac9bSSudeep Holla required: 13661b8ac9bSSudeep Holla - '#clock-cells' 13761b8ac9bSSudeep Holla 13861b8ac9bSSudeep Holla protocol@15: 13961b8ac9bSSudeep Holla type: object 14061b8ac9bSSudeep Holla properties: 14161b8ac9bSSudeep Holla reg: 14261b8ac9bSSudeep Holla const: 0x15 14361b8ac9bSSudeep Holla 14461b8ac9bSSudeep Holla '#thermal-sensor-cells': 14561b8ac9bSSudeep Holla const: 1 14661b8ac9bSSudeep Holla 14761b8ac9bSSudeep Holla required: 14861b8ac9bSSudeep Holla - '#thermal-sensor-cells' 14961b8ac9bSSudeep Holla 15061b8ac9bSSudeep Holla protocol@16: 15161b8ac9bSSudeep Holla type: object 15261b8ac9bSSudeep Holla properties: 15361b8ac9bSSudeep Holla reg: 15461b8ac9bSSudeep Holla const: 0x16 15561b8ac9bSSudeep Holla 15661b8ac9bSSudeep Holla '#reset-cells': 15761b8ac9bSSudeep Holla const: 1 15861b8ac9bSSudeep Holla 15961b8ac9bSSudeep Holla required: 16061b8ac9bSSudeep Holla - '#reset-cells' 16161b8ac9bSSudeep Holla 16261b8ac9bSSudeep Holla protocol@17: 16361b8ac9bSSudeep Holla type: object 16461b8ac9bSSudeep Holla properties: 16561b8ac9bSSudeep Holla reg: 16661b8ac9bSSudeep Holla const: 0x17 16761b8ac9bSSudeep Holla 16861b8ac9bSSudeep Holla regulators: 16961b8ac9bSSudeep Holla type: object 17061b8ac9bSSudeep Holla description: 17161b8ac9bSSudeep Holla The list of all regulators provided by this SCMI controller. 17261b8ac9bSSudeep Holla 17361b8ac9bSSudeep Holla patternProperties: 17461b8ac9bSSudeep Holla '^regulators@[0-9a-f]+$': 17561b8ac9bSSudeep Holla type: object 17661b8ac9bSSudeep Holla $ref: "../regulator/regulator.yaml#" 17761b8ac9bSSudeep Holla 17861b8ac9bSSudeep Holla properties: 17961b8ac9bSSudeep Holla reg: 18061b8ac9bSSudeep Holla maxItems: 1 18161b8ac9bSSudeep Holla description: Identifier for the voltage regulator. 18261b8ac9bSSudeep Holla 18361b8ac9bSSudeep Holla required: 18461b8ac9bSSudeep Holla - reg 18561b8ac9bSSudeep Holla 18661b8ac9bSSudeep HollaadditionalProperties: false 18761b8ac9bSSudeep Holla 18861b8ac9bSSudeep HollapatternProperties: 18961b8ac9bSSudeep Holla '^protocol@[0-9a-f]+$': 19061b8ac9bSSudeep Holla type: object 19161b8ac9bSSudeep Holla description: 19261b8ac9bSSudeep Holla Each sub-node represents a protocol supported. If the platform 19361b8ac9bSSudeep Holla supports a dedicated communication channel for a particular protocol, 19461b8ac9bSSudeep Holla then the corresponding transport properties must be present. 19560625667SIgor Skalkin The virtio transport does not support a dedicated communication channel. 19661b8ac9bSSudeep Holla 19761b8ac9bSSudeep Holla properties: 19861b8ac9bSSudeep Holla reg: 19961b8ac9bSSudeep Holla maxItems: 1 20061b8ac9bSSudeep Holla 20161b8ac9bSSudeep Holla mbox-names: 20261b8ac9bSSudeep Holla items: 20361b8ac9bSSudeep Holla - const: tx 20461b8ac9bSSudeep Holla - const: rx 20561b8ac9bSSudeep Holla 20661b8ac9bSSudeep Holla mboxes: 20761b8ac9bSSudeep Holla minItems: 1 20861b8ac9bSSudeep Holla maxItems: 2 20961b8ac9bSSudeep Holla 21061b8ac9bSSudeep Holla shmem: 21161b8ac9bSSudeep Holla minItems: 1 21261b8ac9bSSudeep Holla maxItems: 2 21361b8ac9bSSudeep Holla 214b7d2cf7cSEtienne Carriere linaro,optee-channel-id: 215b7d2cf7cSEtienne Carriere $ref: /schemas/types.yaml#/definitions/uint32 216b7d2cf7cSEtienne Carriere description: 217b7d2cf7cSEtienne Carriere Channel specifier required when using OP-TEE transport and 218b7d2cf7cSEtienne Carriere protocol has a dedicated communication channel. 219b7d2cf7cSEtienne Carriere 22061b8ac9bSSudeep Holla required: 22161b8ac9bSSudeep Holla - reg 22261b8ac9bSSudeep Holla 22361b8ac9bSSudeep Hollarequired: 22461b8ac9bSSudeep Holla - compatible 22561b8ac9bSSudeep Holla 22661b8ac9bSSudeep Hollaif: 22761b8ac9bSSudeep Holla properties: 22861b8ac9bSSudeep Holla compatible: 22961b8ac9bSSudeep Holla contains: 23061b8ac9bSSudeep Holla const: arm,scmi 23161b8ac9bSSudeep Hollathen: 23261b8ac9bSSudeep Holla properties: 23361b8ac9bSSudeep Holla interrupts: false 23461b8ac9bSSudeep Holla interrupt-names: false 23561b8ac9bSSudeep Holla 23661b8ac9bSSudeep Holla required: 23761b8ac9bSSudeep Holla - mboxes 23860625667SIgor Skalkin - shmem 23961b8ac9bSSudeep Holla 24061b8ac9bSSudeep Hollaelse: 24161b8ac9bSSudeep Holla if: 24261b8ac9bSSudeep Holla properties: 24361b8ac9bSSudeep Holla compatible: 24461b8ac9bSSudeep Holla contains: 24561b8ac9bSSudeep Holla const: arm,scmi-smc 24661b8ac9bSSudeep Holla then: 24761b8ac9bSSudeep Holla required: 24861b8ac9bSSudeep Holla - arm,smc-id 24960625667SIgor Skalkin - shmem 25061b8ac9bSSudeep Holla 251b7d2cf7cSEtienne Carriere else: 252b7d2cf7cSEtienne Carriere if: 253b7d2cf7cSEtienne Carriere properties: 254b7d2cf7cSEtienne Carriere compatible: 255b7d2cf7cSEtienne Carriere contains: 256b7d2cf7cSEtienne Carriere const: linaro,scmi-optee 257b7d2cf7cSEtienne Carriere then: 258b7d2cf7cSEtienne Carriere required: 259b7d2cf7cSEtienne Carriere - linaro,optee-channel-id 260b7d2cf7cSEtienne Carriere 26161b8ac9bSSudeep Hollaexamples: 26261b8ac9bSSudeep Holla - | 26361b8ac9bSSudeep Holla firmware { 26461b8ac9bSSudeep Holla scmi { 26561b8ac9bSSudeep Holla compatible = "arm,scmi"; 26661b8ac9bSSudeep Holla mboxes = <&mhuB 0 0>, 26761b8ac9bSSudeep Holla <&mhuB 0 1>; 26861b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 26961b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0>, 27061b8ac9bSSudeep Holla <&cpu_scp_lpri1>; 27161b8ac9bSSudeep Holla 27261b8ac9bSSudeep Holla #address-cells = <1>; 27361b8ac9bSSudeep Holla #size-cells = <0>; 27461b8ac9bSSudeep Holla 275*0539884cSCristian Marussi atomic-threshold-us = <10000>; 276*0539884cSCristian Marussi 27761b8ac9bSSudeep Holla scmi_devpd: protocol@11 { 27861b8ac9bSSudeep Holla reg = <0x11>; 27961b8ac9bSSudeep Holla #power-domain-cells = <1>; 28061b8ac9bSSudeep Holla }; 28161b8ac9bSSudeep Holla 28261b8ac9bSSudeep Holla scmi_dvfs: protocol@13 { 28361b8ac9bSSudeep Holla reg = <0x13>; 28461b8ac9bSSudeep Holla #clock-cells = <1>; 28561b8ac9bSSudeep Holla 28661b8ac9bSSudeep Holla mboxes = <&mhuB 1 0>, 28761b8ac9bSSudeep Holla <&mhuB 1 1>; 28861b8ac9bSSudeep Holla mbox-names = "tx", "rx"; 28961b8ac9bSSudeep Holla shmem = <&cpu_scp_hpri0>, 29061b8ac9bSSudeep Holla <&cpu_scp_hpri1>; 29161b8ac9bSSudeep Holla }; 29261b8ac9bSSudeep Holla 29361b8ac9bSSudeep Holla scmi_clk: protocol@14 { 29461b8ac9bSSudeep Holla reg = <0x14>; 29561b8ac9bSSudeep Holla #clock-cells = <1>; 29661b8ac9bSSudeep Holla }; 29761b8ac9bSSudeep Holla 29861b8ac9bSSudeep Holla scmi_sensors: protocol@15 { 29961b8ac9bSSudeep Holla reg = <0x15>; 30061b8ac9bSSudeep Holla #thermal-sensor-cells = <1>; 30161b8ac9bSSudeep Holla }; 30261b8ac9bSSudeep Holla 30361b8ac9bSSudeep Holla scmi_reset: protocol@16 { 30461b8ac9bSSudeep Holla reg = <0x16>; 30561b8ac9bSSudeep Holla #reset-cells = <1>; 30661b8ac9bSSudeep Holla }; 30761b8ac9bSSudeep Holla 30861b8ac9bSSudeep Holla scmi_voltage: protocol@17 { 30961b8ac9bSSudeep Holla reg = <0x17>; 31061b8ac9bSSudeep Holla regulators { 31161b8ac9bSSudeep Holla #address-cells = <1>; 31261b8ac9bSSudeep Holla #size-cells = <0>; 31361b8ac9bSSudeep Holla 31461b8ac9bSSudeep Holla regulator_devX: regulator@0 { 31561b8ac9bSSudeep Holla reg = <0x0>; 31661b8ac9bSSudeep Holla regulator-max-microvolt = <3300000>; 31761b8ac9bSSudeep Holla }; 31861b8ac9bSSudeep Holla 31961b8ac9bSSudeep Holla regulator_devY: regulator@9 { 32061b8ac9bSSudeep Holla reg = <0x9>; 32161b8ac9bSSudeep Holla regulator-min-microvolt = <500000>; 32261b8ac9bSSudeep Holla regulator-max-microvolt = <4200000>; 32361b8ac9bSSudeep Holla }; 32461b8ac9bSSudeep Holla }; 32561b8ac9bSSudeep Holla }; 32661b8ac9bSSudeep Holla }; 32761b8ac9bSSudeep Holla }; 32861b8ac9bSSudeep Holla 32961b8ac9bSSudeep Holla soc { 33061b8ac9bSSudeep Holla #address-cells = <2>; 33161b8ac9bSSudeep Holla #size-cells = <2>; 33261b8ac9bSSudeep Holla 33361b8ac9bSSudeep Holla sram@50000000 { 33461b8ac9bSSudeep Holla compatible = "mmio-sram"; 33561b8ac9bSSudeep Holla reg = <0x0 0x50000000 0x0 0x10000>; 33661b8ac9bSSudeep Holla 33761b8ac9bSSudeep Holla #address-cells = <1>; 33861b8ac9bSSudeep Holla #size-cells = <1>; 33961b8ac9bSSudeep Holla ranges = <0 0x0 0x50000000 0x10000>; 34061b8ac9bSSudeep Holla 34161b8ac9bSSudeep Holla cpu_scp_lpri0: scp-sram-section@0 { 34261b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 34361b8ac9bSSudeep Holla reg = <0x0 0x80>; 34461b8ac9bSSudeep Holla }; 34561b8ac9bSSudeep Holla 34661b8ac9bSSudeep Holla cpu_scp_lpri1: scp-sram-section@80 { 34761b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 34861b8ac9bSSudeep Holla reg = <0x80 0x80>; 34961b8ac9bSSudeep Holla }; 35061b8ac9bSSudeep Holla 35161b8ac9bSSudeep Holla cpu_scp_hpri0: scp-sram-section@100 { 35261b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 35361b8ac9bSSudeep Holla reg = <0x100 0x80>; 35461b8ac9bSSudeep Holla }; 35561b8ac9bSSudeep Holla 35661b8ac9bSSudeep Holla cpu_scp_hpri2: scp-sram-section@180 { 35761b8ac9bSSudeep Holla compatible = "arm,scmi-shmem"; 35861b8ac9bSSudeep Holla reg = <0x180 0x80>; 35961b8ac9bSSudeep Holla }; 36061b8ac9bSSudeep Holla }; 36161b8ac9bSSudeep Holla }; 36261b8ac9bSSudeep Holla 36361b8ac9bSSudeep Holla - | 36461b8ac9bSSudeep Holla firmware { 36561b8ac9bSSudeep Holla scmi { 36661b8ac9bSSudeep Holla compatible = "arm,scmi-smc"; 36761b8ac9bSSudeep Holla shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; 36861b8ac9bSSudeep Holla arm,smc-id = <0xc3000001>; 36961b8ac9bSSudeep Holla 37061b8ac9bSSudeep Holla #address-cells = <1>; 37161b8ac9bSSudeep Holla #size-cells = <0>; 37261b8ac9bSSudeep Holla 37361b8ac9bSSudeep Holla scmi_devpd1: protocol@11 { 37461b8ac9bSSudeep Holla reg = <0x11>; 37561b8ac9bSSudeep Holla #power-domain-cells = <1>; 37661b8ac9bSSudeep Holla }; 377b7d2cf7cSEtienne Carriere }; 378b7d2cf7cSEtienne Carriere }; 37961b8ac9bSSudeep Holla 380b7d2cf7cSEtienne Carriere - | 381b7d2cf7cSEtienne Carriere firmware { 382b7d2cf7cSEtienne Carriere scmi { 383b7d2cf7cSEtienne Carriere compatible = "linaro,scmi-optee"; 384b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <0>; 385b7d2cf7cSEtienne Carriere 386b7d2cf7cSEtienne Carriere #address-cells = <1>; 387b7d2cf7cSEtienne Carriere #size-cells = <0>; 388b7d2cf7cSEtienne Carriere 389b7d2cf7cSEtienne Carriere scmi_dvfs1: protocol@13 { 390b7d2cf7cSEtienne Carriere reg = <0x13>; 391b7d2cf7cSEtienne Carriere linaro,optee-channel-id = <1>; 392b7d2cf7cSEtienne Carriere shmem = <&cpu_optee_lpri0>; 393b7d2cf7cSEtienne Carriere #clock-cells = <1>; 394b7d2cf7cSEtienne Carriere }; 395b7d2cf7cSEtienne Carriere 396b7d2cf7cSEtienne Carriere scmi_clk0: protocol@14 { 397b7d2cf7cSEtienne Carriere reg = <0x14>; 398b7d2cf7cSEtienne Carriere #clock-cells = <1>; 399b7d2cf7cSEtienne Carriere }; 400b7d2cf7cSEtienne Carriere }; 401b7d2cf7cSEtienne Carriere }; 402b7d2cf7cSEtienne Carriere 403b7d2cf7cSEtienne Carriere soc { 404b7d2cf7cSEtienne Carriere #address-cells = <2>; 405b7d2cf7cSEtienne Carriere #size-cells = <2>; 406b7d2cf7cSEtienne Carriere 407b7d2cf7cSEtienne Carriere sram@51000000 { 408b7d2cf7cSEtienne Carriere compatible = "mmio-sram"; 409b7d2cf7cSEtienne Carriere reg = <0x0 0x51000000 0x0 0x10000>; 410b7d2cf7cSEtienne Carriere 411b7d2cf7cSEtienne Carriere #address-cells = <1>; 412b7d2cf7cSEtienne Carriere #size-cells = <1>; 413b7d2cf7cSEtienne Carriere ranges = <0 0x0 0x51000000 0x10000>; 414b7d2cf7cSEtienne Carriere 415b7d2cf7cSEtienne Carriere cpu_optee_lpri0: optee-sram-section@0 { 416b7d2cf7cSEtienne Carriere compatible = "arm,scmi-shmem"; 417b7d2cf7cSEtienne Carriere reg = <0x0 0x80>; 418b7d2cf7cSEtienne Carriere }; 41961b8ac9bSSudeep Holla }; 42061b8ac9bSSudeep Holla }; 42161b8ac9bSSudeep Holla 42261b8ac9bSSudeep Holla... 423