1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock Controller on SM6125
8
9maintainers:
10  - Martin Botka <martin.botka@somainline.org>
11
12description: |
13  Qualcomm display clock control module provides the clocks and power domains
14  on SM6125.
15
16  See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,sm6125-dispcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Byte clock from DSI PHY0
27      - description: Pixel clock from DSI PHY0
28      - description: Pixel clock from DSI PHY1
29      - description: Link clock from DP PHY
30      - description: VCO DIV clock from DP PHY
31      - description: AHB config clock from GCC
32      - description: GPLL0 div source from GCC
33
34  clock-names:
35    items:
36      - const: bi_tcxo
37      - const: dsi0_phy_pll_out_byteclk
38      - const: dsi0_phy_pll_out_dsiclk
39      - const: dsi1_phy_pll_out_dsiclk
40      - const: dp_phy_pll_link_clk
41      - const: dp_phy_pll_vco_div_clk
42      - const: cfg_ahb_clk
43      - const: gcc_disp_gpll0_div_clk_src
44
45  '#clock-cells':
46    const: 1
47
48  '#power-domain-cells':
49    const: 1
50
51  reg:
52    maxItems: 1
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - '#clock-cells'
60  - '#power-domain-cells'
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/qcom,rpmcc.h>
67    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
68    clock-controller@5f00000 {
69      compatible = "qcom,sm6125-dispcc";
70      reg = <0x5f00000 0x20000>;
71      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
72               <&dsi0_phy 0>,
73               <&dsi0_phy 1>,
74               <&dsi1_phy 1>,
75               <&dp_phy 0>,
76               <&dp_phy 1>,
77               <&gcc GCC_DISP_AHB_CLK>,
78               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
79      clock-names = "bi_tcxo",
80                    "dsi0_phy_pll_out_byteclk",
81                    "dsi0_phy_pll_out_dsiclk",
82                    "dsi1_phy_pll_out_dsiclk",
83                    "dp_phy_pll_link_clk",
84                    "dp_phy_pll_vco_div_clk",
85                    "cfg_ahb_clk",
86                    "gcc_disp_gpll0_div_clk_src";
87      #clock-cells = <1>;
88      #power-domain-cells = <1>;
89    };
90...
91