1*60f9e37aSTsahee Zidenberg======================================================== 2*60f9e37aSTsahee ZidenbergSecondary CPU enable-method "al,alpine-smp" binding 3*60f9e37aSTsahee Zidenberg======================================================== 4*60f9e37aSTsahee Zidenberg 5*60f9e37aSTsahee ZidenbergThis document describes the "al,alpine-smp" method for 6*60f9e37aSTsahee Zidenbergenabling secondary CPUs. To apply to all CPUs, a single 7*60f9e37aSTsahee Zidenberg"al,alpine-smp" enable method should be defined in the 8*60f9e37aSTsahee Zidenberg"cpus" node. 9*60f9e37aSTsahee Zidenberg 10*60f9e37aSTsahee ZidenbergEnable method name: "al,alpine-smp" 11*60f9e37aSTsahee ZidenbergCompatible machines: "al,alpine" 12*60f9e37aSTsahee ZidenbergCompatible CPUs: "arm,cortex-a15" 13*60f9e37aSTsahee ZidenbergRelated properties: (none) 14*60f9e37aSTsahee Zidenberg 15*60f9e37aSTsahee ZidenbergNote: 16*60f9e37aSTsahee ZidenbergThis enable method requires valid nodes compatible with 17*60f9e37aSTsahee Zidenberg"al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. 18*60f9e37aSTsahee Zidenberg 19*60f9e37aSTsahee ZidenbergExample: 20*60f9e37aSTsahee Zidenberg 21*60f9e37aSTsahee Zidenbergcpus { 22*60f9e37aSTsahee Zidenberg #address-cells = <1>; 23*60f9e37aSTsahee Zidenberg #size-cells = <0>; 24*60f9e37aSTsahee Zidenberg enable-method = "al,alpine-smp"; 25*60f9e37aSTsahee Zidenberg 26*60f9e37aSTsahee Zidenberg cpu@0 { 27*60f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 28*60f9e37aSTsahee Zidenberg device_type = "cpu"; 29*60f9e37aSTsahee Zidenberg reg = <0>; 30*60f9e37aSTsahee Zidenberg }; 31*60f9e37aSTsahee Zidenberg 32*60f9e37aSTsahee Zidenberg cpu@1 { 33*60f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 34*60f9e37aSTsahee Zidenberg device_type = "cpu"; 35*60f9e37aSTsahee Zidenberg reg = <1>; 36*60f9e37aSTsahee Zidenberg }; 37*60f9e37aSTsahee Zidenberg 38*60f9e37aSTsahee Zidenberg cpu@2 { 39*60f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 40*60f9e37aSTsahee Zidenberg device_type = "cpu"; 41*60f9e37aSTsahee Zidenberg reg = <2>; 42*60f9e37aSTsahee Zidenberg }; 43*60f9e37aSTsahee Zidenberg 44*60f9e37aSTsahee Zidenberg cpu@3 { 45*60f9e37aSTsahee Zidenberg compatible = "arm,cortex-a15"; 46*60f9e37aSTsahee Zidenberg device_type = "cpu"; 47*60f9e37aSTsahee Zidenberg reg = <3>; 48*60f9e37aSTsahee Zidenberg }; 49*60f9e37aSTsahee Zidenberg}; 50*60f9e37aSTsahee Zidenberg 51*60f9e37aSTsahee Zidenberg-- 52*60f9e37aSTsahee Zidenberg[1] arm/al,alpine.txt 53