1What: /sys/bus/cxl/devices/memX/firmware_version 2Date: December, 2020 3KernelVersion: v5.12 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (RO) "FW Revision" string as reported by the Identify 7 Memory Device Output Payload in the CXL-2.0 8 specification. 9 10What: /sys/bus/cxl/devices/memX/ram/size 11Date: December, 2020 12KernelVersion: v5.12 13Contact: linux-cxl@vger.kernel.org 14Description: 15 (RO) "Volatile Only Capacity" as bytes. Represents the 16 identically named field in the Identify Memory Device Output 17 Payload in the CXL-2.0 specification. 18 19What: /sys/bus/cxl/devices/memX/pmem/size 20Date: December, 2020 21KernelVersion: v5.12 22Contact: linux-cxl@vger.kernel.org 23Description: 24 (RO) "Persistent Only Capacity" as bytes. Represents the 25 identically named field in the Identify Memory Device Output 26 Payload in the CXL-2.0 specification. 27 28What: /sys/bus/cxl/devices/memX/serial 29Date: January, 2022 30KernelVersion: v5.18 31Contact: linux-cxl@vger.kernel.org 32Description: 33 (RO) 64-bit serial number per the PCIe Device Serial Number 34 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 35 Memory Device PCIe Capabilities and Extended Capabilities. 36 37What: /sys/bus/cxl/devices/memX/numa_node 38Date: January, 2022 39KernelVersion: v5.18 40Contact: linux-cxl@vger.kernel.org 41Description: 42 (RO) If NUMA is enabled and the platform has affinitized the 43 host PCI device for this memory device, emit the CPU node 44 affinity for this device. 45 46What: /sys/bus/cxl/devices/*/devtype 47Date: June, 2021 48KernelVersion: v5.14 49Contact: linux-cxl@vger.kernel.org 50Description: 51 CXL device objects export the devtype attribute which mirrors 52 the same value communicated in the DEVTYPE environment variable 53 for uevents for devices on the "cxl" bus. 54 55What: /sys/bus/cxl/devices/*/modalias 56Date: December, 2021 57KernelVersion: v5.18 58Contact: linux-cxl@vger.kernel.org 59Description: 60 CXL device objects export the modalias attribute which mirrors 61 the same value communicated in the MODALIAS environment variable 62 for uevents for devices on the "cxl" bus. 63 64What: /sys/bus/cxl/devices/portX/uport 65Date: June, 2021 66KernelVersion: v5.14 67Contact: linux-cxl@vger.kernel.org 68Description: 69 CXL port objects are enumerated from either a platform firmware 70 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 71 CXL component registers. The 'uport' symlink connects the CXL 72 portX object to the device that published the CXL port 73 capability. 74 75What: /sys/bus/cxl/devices/portX/dportY 76Date: June, 2021 77KernelVersion: v5.14 78Contact: linux-cxl@vger.kernel.org 79Description: 80 CXL port objects are enumerated from either a platform firmware 81 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 82 CXL component registers. The 'dportY' symlink identifies one or 83 more downstream ports that the upstream port may target in its 84 decode of CXL memory resources. The 'Y' integer reflects the 85 hardware port unique-id used in the hardware decoder target 86 list. 87 88What: /sys/bus/cxl/devices/decoderX.Y 89Date: June, 2021 90KernelVersion: v5.14 91Contact: linux-cxl@vger.kernel.org 92Description: 93 CXL decoder objects are enumerated from either a platform 94 firmware description, or a CXL HDM decoder register set in a 95 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 96 Capability Structure). The 'X' in decoderX.Y represents the 97 cxl_port container of this decoder, and 'Y' represents the 98 instance id of a given decoder resource. 99 100What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 101Date: June, 2021 102KernelVersion: v5.14 103Contact: linux-cxl@vger.kernel.org 104Description: 105 The 'start' and 'size' attributes together convey the physical 106 address base and number of bytes mapped in the decoder's decode 107 window. For decoders of devtype "cxl_decoder_root" the address 108 range is fixed. For decoders of devtype "cxl_decoder_switch" the 109 address is bounded by the decode range of the cxl_port ancestor 110 of the decoder's cxl_port, and dynamically updates based on the 111 active memory regions in that address space. 112 113What: /sys/bus/cxl/devices/decoderX.Y/locked 114Date: June, 2021 115KernelVersion: v5.14 116Contact: linux-cxl@vger.kernel.org 117Description: 118 CXL HDM decoders have the capability to lock the configuration 119 until the next device reset. For decoders of devtype 120 "cxl_decoder_root" there is no standard facility to unlock them. 121 For decoders of devtype "cxl_decoder_switch" a secondary bus 122 reset, of the PCIe bridge that provides the bus for this 123 decoders uport, unlocks / resets the decoder. 124 125What: /sys/bus/cxl/devices/decoderX.Y/target_list 126Date: June, 2021 127KernelVersion: v5.14 128Contact: linux-cxl@vger.kernel.org 129Description: 130 Display a comma separated list of the current decoder target 131 configuration. The list is ordered by the current configured 132 interleave order of the decoder's dport instances. Each entry in 133 the list is a dport id. 134 135What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 136Date: June, 2021 137KernelVersion: v5.14 138Contact: linux-cxl@vger.kernel.org 139Description: 140 When a CXL decoder is of devtype "cxl_decoder_root", it 141 represents a fixed memory window identified by platform 142 firmware. A fixed window may only support a subset of memory 143 types. The 'cap_*' attributes indicate whether persistent 144 memory, volatile memory, accelerator memory, and / or expander 145 memory may be mapped behind this decoder's memory window. 146 147What: /sys/bus/cxl/devices/decoderX.Y/target_type 148Date: June, 2021 149KernelVersion: v5.14 150Contact: linux-cxl@vger.kernel.org 151Description: 152 When a CXL decoder is of devtype "cxl_decoder_switch", it can 153 optionally decode either accelerator memory (type-2) or expander 154 memory (type-3). The 'target_type' attribute indicates the 155 current setting which may dynamically change based on what 156 memory regions are activated in this decode hierarchy. 157