1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/ram/size 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) "Volatile Only Capacity" as bytes. Represents the 27 identically named field in the Identify Memory Device Output 28 Payload in the CXL-2.0 specification. 29 30 31What: /sys/bus/cxl/devices/memX/pmem/size 32Date: December, 2020 33KernelVersion: v5.12 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) "Persistent Only Capacity" as bytes. Represents the 37 identically named field in the Identify Memory Device Output 38 Payload in the CXL-2.0 specification. 39 40 41What: /sys/bus/cxl/devices/memX/serial 42Date: January, 2022 43KernelVersion: v5.18 44Contact: linux-cxl@vger.kernel.org 45Description: 46 (RO) 64-bit serial number per the PCIe Device Serial Number 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 48 Memory Device PCIe Capabilities and Extended Capabilities. 49 50 51What: /sys/bus/cxl/devices/memX/numa_node 52Date: January, 2022 53KernelVersion: v5.18 54Contact: linux-cxl@vger.kernel.org 55Description: 56 (RO) If NUMA is enabled and the platform has affinitized the 57 host PCI device for this memory device, emit the CPU node 58 affinity for this device. 59 60 61What: /sys/bus/cxl/devices/memX/security/state 62Date: June, 2023 63KernelVersion: v6.5 64Contact: linux-cxl@vger.kernel.org 65Description: 66 (RO) Reading this file will display the CXL security state for 67 that device. Such states can be: 'disabled', 'sanitize', when 68 a sanitization is currently underway; or those available only 69 for persistent memory: 'locked', 'unlocked' or 'frozen'. This 70 sysfs entry is select/poll capable from userspace to notify 71 upon completion of a sanitize operation. 72 73 74What: /sys/bus/cxl/devices/memX/security/sanitize 75Date: June, 2023 76KernelVersion: v6.5 77Contact: linux-cxl@vger.kernel.org 78Description: 79 (WO) Write a boolean 'true' string value to this attribute to 80 sanitize the device to securely re-purpose or decommission it. 81 This is done by ensuring that all user data and meta-data, 82 whether it resides in persistent capacity, volatile capacity, 83 or the LSA, is made permanently unavailable by whatever means 84 is appropriate for the media type. This functionality requires 85 the device to be disabled, that is, not actively decoding any 86 HPA ranges. This permits avoiding explicit global CPU cache 87 management, relying instead for it to be done when a region 88 transitions between software programmed and hardware committed 89 states. If this file is not present, then there is no hardware 90 support for the operation. 91 92 93What /sys/bus/cxl/devices/memX/security/erase 94Date: June, 2023 95KernelVersion: v6.5 96Contact: linux-cxl@vger.kernel.org 97Description: 98 (WO) Write a boolean 'true' string value to this attribute to 99 secure erase user data by changing the media encryption keys for 100 all user data areas of the device. This functionality requires 101 the device to be disabled, that is, not actively decoding any 102 HPA ranges. This permits avoiding explicit global CPU cache 103 management, relying instead for it to be done when a region 104 transitions between software programmed and hardware committed 105 states. If this file is not present, then there is no hardware 106 support for the operation. 107 108 109What: /sys/bus/cxl/devices/memX/firmware/ 110Date: April, 2023 111KernelVersion: v6.5 112Contact: linux-cxl@vger.kernel.org 113Description: 114 (RW) Firmware uploader mechanism. The different files under 115 this directory can be used to upload and activate new 116 firmware for CXL devices. The interfaces under this are 117 documented in sysfs-class-firmware. 118 119 120What: /sys/bus/cxl/devices/*/devtype 121Date: June, 2021 122KernelVersion: v5.14 123Contact: linux-cxl@vger.kernel.org 124Description: 125 (RO) CXL device objects export the devtype attribute which 126 mirrors the same value communicated in the DEVTYPE environment 127 variable for uevents for devices on the "cxl" bus. 128 129 130What: /sys/bus/cxl/devices/*/modalias 131Date: December, 2021 132KernelVersion: v5.18 133Contact: linux-cxl@vger.kernel.org 134Description: 135 (RO) CXL device objects export the modalias attribute which 136 mirrors the same value communicated in the MODALIAS environment 137 variable for uevents for devices on the "cxl" bus. 138 139 140What: /sys/bus/cxl/devices/portX/uport 141Date: June, 2021 142KernelVersion: v5.14 143Contact: linux-cxl@vger.kernel.org 144Description: 145 (RO) CXL port objects are enumerated from either a platform 146 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 147 port with CXL component registers. The 'uport' symlink connects 148 the CXL portX object to the device that published the CXL port 149 capability. 150 151 152What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport 153Date: January, 2023 154KernelVersion: v6.3 155Contact: linux-cxl@vger.kernel.org 156Description: 157 (RO) CXL port objects are instantiated for each upstream port in 158 a CXL/PCIe switch, and for each endpoint to map the 159 corresponding memory device into the CXL port hierarchy. When a 160 descendant CXL port (switch or endpoint) is enumerated it is 161 useful to know which 'dport' object in the parent CXL port 162 routes to this descendant. The 'parent_dport' symlink points to 163 the device representing the downstream port of a CXL switch that 164 routes to {port,endpoint}X. 165 166 167What: /sys/bus/cxl/devices/portX/dportY 168Date: June, 2021 169KernelVersion: v5.14 170Contact: linux-cxl@vger.kernel.org 171Description: 172 (RO) CXL port objects are enumerated from either a platform 173 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 174 port with CXL component registers. The 'dportY' symlink 175 identifies one or more downstream ports that the upstream port 176 may target in its decode of CXL memory resources. The 'Y' 177 integer reflects the hardware port unique-id used in the 178 hardware decoder target list. 179 180 181What: /sys/bus/cxl/devices/decoderX.Y 182Date: June, 2021 183KernelVersion: v5.14 184Contact: linux-cxl@vger.kernel.org 185Description: 186 (RO) CXL decoder objects are enumerated from either a platform 187 firmware description, or a CXL HDM decoder register set in a 188 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 189 Capability Structure). The 'X' in decoderX.Y represents the 190 cxl_port container of this decoder, and 'Y' represents the 191 instance id of a given decoder resource. 192 193 194What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 195Date: June, 2021 196KernelVersion: v5.14 197Contact: linux-cxl@vger.kernel.org 198Description: 199 (RO) The 'start' and 'size' attributes together convey the 200 physical address base and number of bytes mapped in the 201 decoder's decode window. For decoders of devtype 202 "cxl_decoder_root" the address range is fixed. For decoders of 203 devtype "cxl_decoder_switch" the address is bounded by the 204 decode range of the cxl_port ancestor of the decoder's cxl_port, 205 and dynamically updates based on the active memory regions in 206 that address space. 207 208 209What: /sys/bus/cxl/devices/decoderX.Y/locked 210Date: June, 2021 211KernelVersion: v5.14 212Contact: linux-cxl@vger.kernel.org 213Description: 214 (RO) CXL HDM decoders have the capability to lock the 215 configuration until the next device reset. For decoders of 216 devtype "cxl_decoder_root" there is no standard facility to 217 unlock them. For decoders of devtype "cxl_decoder_switch" a 218 secondary bus reset, of the PCIe bridge that provides the bus 219 for this decoders uport, unlocks / resets the decoder. 220 221 222What: /sys/bus/cxl/devices/decoderX.Y/target_list 223Date: June, 2021 224KernelVersion: v5.14 225Contact: linux-cxl@vger.kernel.org 226Description: 227 (RO) Display a comma separated list of the current decoder 228 target configuration. The list is ordered by the current 229 configured interleave order of the decoder's dport instances. 230 Each entry in the list is a dport id. 231 232 233What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 234Date: June, 2021 235KernelVersion: v5.14 236Contact: linux-cxl@vger.kernel.org 237Description: 238 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 239 represents a fixed memory window identified by platform 240 firmware. A fixed window may only support a subset of memory 241 types. The 'cap_*' attributes indicate whether persistent 242 memory, volatile memory, accelerator memory, and / or expander 243 memory may be mapped behind this decoder's memory window. 244 245 246What: /sys/bus/cxl/devices/decoderX.Y/target_type 247Date: June, 2021 248KernelVersion: v5.14 249Contact: linux-cxl@vger.kernel.org 250Description: 251 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 252 can optionally decode either accelerator memory (type-2) or 253 expander memory (type-3). The 'target_type' attribute indicates 254 the current setting which may dynamically change based on what 255 memory regions are activated in this decode hierarchy. 256 257 258What: /sys/bus/cxl/devices/endpointX/CDAT 259Date: July, 2022 260KernelVersion: v6.0 261Contact: linux-cxl@vger.kernel.org 262Description: 263 (RO) If this sysfs entry is not present no DOE mailbox was 264 found to support CDAT data. If it is present and the length of 265 the data is 0 reading the CDAT data failed. Otherwise the CDAT 266 data is reported. 267 268 269What: /sys/bus/cxl/devices/decoderX.Y/mode 270Date: May, 2022 271KernelVersion: v6.0 272Contact: linux-cxl@vger.kernel.org 273Description: 274 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 275 translates from a host physical address range, to a device local 276 address range. Device-local address ranges are further split 277 into a 'ram' (volatile memory) range and 'pmem' (persistent 278 memory) range. The 'mode' attribute emits one of 'ram', 'pmem', 279 'mixed', or 'none'. The 'mixed' indication is for error cases 280 when a decoder straddles the volatile/persistent partition 281 boundary, and 'none' indicates the decoder is not actively 282 decoding, or no DPA allocation policy has been set. 283 284 'mode' can be written, when the decoder is in the 'disabled' 285 state, with either 'ram' or 'pmem' to set the boundaries for the 286 next allocation. 287 288 289What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 290Date: May, 2022 291KernelVersion: v6.0 292Contact: linux-cxl@vger.kernel.org 293Description: 294 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 295 and its 'dpa_size' attribute is non-zero, this attribute 296 indicates the device physical address (DPA) base address of the 297 allocation. 298 299 300What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 301Date: May, 2022 302KernelVersion: v6.0 303Contact: linux-cxl@vger.kernel.org 304Description: 305 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 306 translates from a host physical address range, to a device local 307 address range. The range, base address plus length in bytes, of 308 DPA allocated to this decoder is conveyed in these 2 attributes. 309 Allocations can be mutated as long as the decoder is in the 310 disabled state. A write to 'dpa_size' releases the previous DPA 311 allocation and then attempts to allocate from the free capacity 312 in the device partition referred to by 'decoderX.Y/mode'. 313 Allocate and free requests can only be performed on the highest 314 instance number disabled decoder with non-zero size. I.e. 315 allocations are enforced to occur in increasing 'decoderX.Y/id' 316 order and frees are enforced to occur in decreasing 317 'decoderX.Y/id' order. 318 319 320What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 321Date: May, 2022 322KernelVersion: v6.0 323Contact: linux-cxl@vger.kernel.org 324Description: 325 (RO) The number of targets across which this decoder's host 326 physical address (HPA) memory range is interleaved. The device 327 maps every Nth block of HPA (of size == 328 'interleave_granularity') to consecutive DPA addresses. The 329 decoder's position in the interleave is determined by the 330 device's (endpoint or switch) switch ancestry. For root 331 decoders their interleave is specified by platform firmware and 332 they only specify a downstream target order for host bridges. 333 334 335What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 336Date: May, 2022 337KernelVersion: v6.0 338Contact: linux-cxl@vger.kernel.org 339Description: 340 (RO) The number of consecutive bytes of host physical address 341 space this decoder claims at address N before the decode rotates 342 to the next target in the interleave at address N + 343 interleave_granularity (assuming N is aligned to 344 interleave_granularity). 345 346 347What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region 348Date: May, 2022, January, 2023 349KernelVersion: v6.0 (pmem), v6.3 (ram) 350Contact: linux-cxl@vger.kernel.org 351Description: 352 (RW) Write a string in the form 'regionZ' to start the process 353 of defining a new persistent, or volatile memory region 354 (interleave-set) within the decode range bounded by root decoder 355 'decoderX.Y'. The value written must match the current value 356 returned from reading this attribute. An atomic compare exchange 357 operation is done on write to assign the requested id to a 358 region and allocate the region-id for the next creation attempt. 359 EBUSY is returned if the region name written does not match the 360 current cached value. 361 362 363What: /sys/bus/cxl/devices/decoderX.Y/delete_region 364Date: May, 2022 365KernelVersion: v6.0 366Contact: linux-cxl@vger.kernel.org 367Description: 368 (WO) Write a string in the form 'regionZ' to delete that region, 369 provided it is currently idle / not bound to a driver. 370 371 372What: /sys/bus/cxl/devices/regionZ/uuid 373Date: May, 2022 374KernelVersion: v6.0 375Contact: linux-cxl@vger.kernel.org 376Description: 377 (RW) Write a unique identifier for the region. This field must 378 be set for persistent regions and it must not conflict with the 379 UUID of another region. For volatile ram regions this 380 attribute is a read-only empty string. 381 382 383What: /sys/bus/cxl/devices/regionZ/interleave_granularity 384Date: May, 2022 385KernelVersion: v6.0 386Contact: linux-cxl@vger.kernel.org 387Description: 388 (RW) Set the number of consecutive bytes each device in the 389 interleave set will claim. The possible interleave granularity 390 values are determined by the CXL spec and the participating 391 devices. 392 393 394What: /sys/bus/cxl/devices/regionZ/interleave_ways 395Date: May, 2022 396KernelVersion: v6.0 397Contact: linux-cxl@vger.kernel.org 398Description: 399 (RW) Configures the number of devices participating in the 400 region is set by writing this value. Each device will provide 401 1/interleave_ways of storage for the region. 402 403 404What: /sys/bus/cxl/devices/regionZ/size 405Date: May, 2022 406KernelVersion: v6.0 407Contact: linux-cxl@vger.kernel.org 408Description: 409 (RW) System physical address space to be consumed by the region. 410 When written trigger the driver to allocate space out of the 411 parent root decoder's address space. When read the size of the 412 address space is reported and should match the span of the 413 region's resource attribute. Size shall be set after the 414 interleave configuration parameters. Once set it cannot be 415 changed, only freed by writing 0. The kernel makes no guarantees 416 that data is maintained over an address space freeing event, and 417 there is no guarantee that a free followed by an allocate 418 results in the same address being allocated. 419 420 421What: /sys/bus/cxl/devices/regionZ/mode 422Date: January, 2023 423KernelVersion: v6.3 424Contact: linux-cxl@vger.kernel.org 425Description: 426 (RO) The mode of a region is established at region creation time 427 and dictates the mode of the endpoint decoder that comprise the 428 region. For more details on the possible modes see 429 /sys/bus/cxl/devices/decoderX.Y/mode 430 431 432What: /sys/bus/cxl/devices/regionZ/resource 433Date: May, 2022 434KernelVersion: v6.0 435Contact: linux-cxl@vger.kernel.org 436Description: 437 (RO) A region is a contiguous partition of a CXL root decoder 438 address space. Region capacity is allocated by writing to the 439 size attribute, the resulting physical address space determined 440 by the driver is reflected here. It is therefore not useful to 441 read this before writing a value to the size attribute. 442 443 444What: /sys/bus/cxl/devices/regionZ/target[0..N] 445Date: May, 2022 446KernelVersion: v6.0 447Contact: linux-cxl@vger.kernel.org 448Description: 449 (RW) Write an endpoint decoder object name to 'targetX' where X 450 is the intended position of the endpoint device in the region 451 interleave and N is the 'interleave_ways' setting for the 452 region. ENXIO is returned if the write results in an impossible 453 to map decode scenario, like the endpoint is unreachable at that 454 position relative to the root decoder interleave. EBUSY is 455 returned if the position in the region is already occupied, or 456 if the region is not in a state to accept interleave 457 configuration changes. EINVAL is returned if the object name is 458 not an endpoint decoder. Once all positions have been 459 successfully written a final validation for decode conflicts is 460 performed before activating the region. 461 462 463What: /sys/bus/cxl/devices/regionZ/commit 464Date: May, 2022 465KernelVersion: v6.0 466Contact: linux-cxl@vger.kernel.org 467Description: 468 (RW) Write a boolean 'true' string value to this attribute to 469 trigger the region to transition from the software programmed 470 state to the actively decoding in hardware state. The commit 471 operation in addition to validating that the region is in proper 472 configured state, validates that the decoders are being 473 committed in spec mandated order (last committed decoder id + 474 1), and checks that the hardware accepts the commit request. 475 Reading this value indicates whether the region is committed or 476 not. 477 478 479What: /sys/bus/cxl/devices/memX/trigger_poison_list 480Date: April, 2023 481KernelVersion: v6.4 482Contact: linux-cxl@vger.kernel.org 483Description: 484 (WO) When a boolean 'true' is written to this attribute the 485 memdev driver retrieves the poison list from the device. The 486 list consists of addresses that are poisoned, or would result 487 in poison if accessed, and the source of the poison. This 488 attribute is only visible for devices supporting the 489 capability. The retrieved errors are logged as kernel 490 events when cxl_poison event tracing is enabled. 491