1What:		/sys/bus/cxl/flush
2Date:		Januarry, 2022
3KernelVersion:	v5.18
4Contact:	linux-cxl@vger.kernel.org
5Description:
6		(WO) If userspace manually unbinds a port the kernel schedules
7		all descendant memdevs for unbind. Writing '1' to this attribute
8		flushes that work.
9
10What:		/sys/bus/cxl/devices/memX/firmware_version
11Date:		December, 2020
12KernelVersion:	v5.12
13Contact:	linux-cxl@vger.kernel.org
14Description:
15		(RO) "FW Revision" string as reported by the Identify
16		Memory Device Output Payload in the CXL-2.0
17		specification.
18
19What:		/sys/bus/cxl/devices/memX/ram/size
20Date:		December, 2020
21KernelVersion:	v5.12
22Contact:	linux-cxl@vger.kernel.org
23Description:
24		(RO) "Volatile Only Capacity" as bytes. Represents the
25		identically named field in the Identify Memory Device Output
26		Payload in the CXL-2.0 specification.
27
28What:		/sys/bus/cxl/devices/memX/pmem/size
29Date:		December, 2020
30KernelVersion:	v5.12
31Contact:	linux-cxl@vger.kernel.org
32Description:
33		(RO) "Persistent Only Capacity" as bytes. Represents the
34		identically named field in the Identify Memory Device Output
35		Payload in the CXL-2.0 specification.
36
37What:		/sys/bus/cxl/devices/memX/serial
38Date:		January, 2022
39KernelVersion:	v5.18
40Contact:	linux-cxl@vger.kernel.org
41Description:
42		(RO) 64-bit serial number per the PCIe Device Serial Number
43		capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
44		Memory Device PCIe Capabilities and Extended Capabilities.
45
46What:		/sys/bus/cxl/devices/memX/numa_node
47Date:		January, 2022
48KernelVersion:	v5.18
49Contact:	linux-cxl@vger.kernel.org
50Description:
51		(RO) If NUMA is enabled and the platform has affinitized the
52		host PCI device for this memory device, emit the CPU node
53		affinity for this device.
54
55What:		/sys/bus/cxl/devices/*/devtype
56Date:		June, 2021
57KernelVersion:	v5.14
58Contact:	linux-cxl@vger.kernel.org
59Description:
60		(RO) CXL device objects export the devtype attribute which
61		mirrors the same value communicated in the DEVTYPE environment
62		variable for uevents for devices on the "cxl" bus.
63
64What:		/sys/bus/cxl/devices/*/modalias
65Date:		December, 2021
66KernelVersion:	v5.18
67Contact:	linux-cxl@vger.kernel.org
68Description:
69		(RO) CXL device objects export the modalias attribute which
70		mirrors the same value communicated in the MODALIAS environment
71		variable for uevents for devices on the "cxl" bus.
72
73What:		/sys/bus/cxl/devices/portX/uport
74Date:		June, 2021
75KernelVersion:	v5.14
76Contact:	linux-cxl@vger.kernel.org
77Description:
78		(RO) CXL port objects are enumerated from either a platform
79		firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
80		port with CXL component registers. The 'uport' symlink connects
81		the CXL portX object to the device that published the CXL port
82		capability.
83
84What:		/sys/bus/cxl/devices/portX/dportY
85Date:		June, 2021
86KernelVersion:	v5.14
87Contact:	linux-cxl@vger.kernel.org
88Description:
89		(RO) CXL port objects are enumerated from either a platform
90		firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
91		port with CXL component registers. The 'dportY' symlink
92		identifies one or more downstream ports that the upstream port
93		may target in its decode of CXL memory resources.  The 'Y'
94		integer reflects the hardware port unique-id used in the
95		hardware decoder target list.
96
97What:		/sys/bus/cxl/devices/decoderX.Y
98Date:		June, 2021
99KernelVersion:	v5.14
100Contact:	linux-cxl@vger.kernel.org
101Description:
102		(RO) CXL decoder objects are enumerated from either a platform
103		firmware description, or a CXL HDM decoder register set in a
104		PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
105		Capability Structure). The 'X' in decoderX.Y represents the
106		cxl_port container of this decoder, and 'Y' represents the
107		instance id of a given decoder resource.
108
109What:		/sys/bus/cxl/devices/decoderX.Y/{start,size}
110Date:		June, 2021
111KernelVersion:	v5.14
112Contact:	linux-cxl@vger.kernel.org
113Description:
114		(RO) The 'start' and 'size' attributes together convey the
115		physical address base and number of bytes mapped in the
116		decoder's decode window. For decoders of devtype
117		"cxl_decoder_root" the address range is fixed. For decoders of
118		devtype "cxl_decoder_switch" the address is bounded by the
119		decode range of the cxl_port ancestor of the decoder's cxl_port,
120		and dynamically updates based on the active memory regions in
121		that address space.
122
123What:		/sys/bus/cxl/devices/decoderX.Y/locked
124Date:		June, 2021
125KernelVersion:	v5.14
126Contact:	linux-cxl@vger.kernel.org
127Description:
128		(RO) CXL HDM decoders have the capability to lock the
129		configuration until the next device reset. For decoders of
130		devtype "cxl_decoder_root" there is no standard facility to
131		unlock them.  For decoders of devtype "cxl_decoder_switch" a
132		secondary bus reset, of the PCIe bridge that provides the bus
133		for this decoders uport, unlocks / resets the decoder.
134
135What:		/sys/bus/cxl/devices/decoderX.Y/target_list
136Date:		June, 2021
137KernelVersion:	v5.14
138Contact:	linux-cxl@vger.kernel.org
139Description:
140		(RO) Display a comma separated list of the current decoder
141		target configuration. The list is ordered by the current
142		configured interleave order of the decoder's dport instances.
143		Each entry in the list is a dport id.
144
145What:		/sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
146Date:		June, 2021
147KernelVersion:	v5.14
148Contact:	linux-cxl@vger.kernel.org
149Description:
150		(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
151		represents a fixed memory window identified by platform
152		firmware. A fixed window may only support a subset of memory
153		types. The 'cap_*' attributes indicate whether persistent
154		memory, volatile memory, accelerator memory, and / or expander
155		memory may be mapped behind this decoder's memory window.
156
157What:		/sys/bus/cxl/devices/decoderX.Y/target_type
158Date:		June, 2021
159KernelVersion:	v5.14
160Contact:	linux-cxl@vger.kernel.org
161Description:
162		(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
163		can optionally decode either accelerator memory (type-2) or
164		expander memory (type-3). The 'target_type' attribute indicates
165		the current setting which may dynamically change based on what
166		memory regions are activated in this decode hierarchy.
167
168What:		/sys/bus/cxl/devices/endpointX/CDAT
169Date:		July, 2022
170KernelVersion:	v5.20
171Contact:	linux-cxl@vger.kernel.org
172Description:
173		(RO) If this sysfs entry is not present no DOE mailbox was
174		found to support CDAT data.  If it is present and the length of
175		the data is 0 reading the CDAT data failed.  Otherwise the CDAT
176		data is reported.
177