1What: /sys/bus/cxl/devices/memX/firmware_version 2Date: December, 2020 3KernelVersion: v5.12 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (RO) "FW Revision" string as reported by the Identify 7 Memory Device Output Payload in the CXL-2.0 8 specification. 9 10What: /sys/bus/cxl/devices/memX/ram/size 11Date: December, 2020 12KernelVersion: v5.12 13Contact: linux-cxl@vger.kernel.org 14Description: 15 (RO) "Volatile Only Capacity" as bytes. Represents the 16 identically named field in the Identify Memory Device Output 17 Payload in the CXL-2.0 specification. 18 19What: /sys/bus/cxl/devices/memX/pmem/size 20Date: December, 2020 21KernelVersion: v5.12 22Contact: linux-cxl@vger.kernel.org 23Description: 24 (RO) "Persistent Only Capacity" as bytes. Represents the 25 identically named field in the Identify Memory Device Output 26 Payload in the CXL-2.0 specification. 27 28What: /sys/bus/cxl/devices/memX/serial 29Date: January, 2022 30KernelVersion: v5.18 31Contact: linux-cxl@vger.kernel.org 32Description: 33 (RO) 64-bit serial number per the PCIe Device Serial Number 34 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 35 Memory Device PCIe Capabilities and Extended Capabilities. 36 37What: /sys/bus/cxl/devices/*/devtype 38Date: June, 2021 39KernelVersion: v5.14 40Contact: linux-cxl@vger.kernel.org 41Description: 42 CXL device objects export the devtype attribute which mirrors 43 the same value communicated in the DEVTYPE environment variable 44 for uevents for devices on the "cxl" bus. 45 46What: /sys/bus/cxl/devices/*/modalias 47Date: December, 2021 48KernelVersion: v5.18 49Contact: linux-cxl@vger.kernel.org 50Description: 51 CXL device objects export the modalias attribute which mirrors 52 the same value communicated in the MODALIAS environment variable 53 for uevents for devices on the "cxl" bus. 54 55What: /sys/bus/cxl/devices/portX/uport 56Date: June, 2021 57KernelVersion: v5.14 58Contact: linux-cxl@vger.kernel.org 59Description: 60 CXL port objects are enumerated from either a platform firmware 61 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 62 CXL component registers. The 'uport' symlink connects the CXL 63 portX object to the device that published the CXL port 64 capability. 65 66What: /sys/bus/cxl/devices/portX/dportY 67Date: June, 2021 68KernelVersion: v5.14 69Contact: linux-cxl@vger.kernel.org 70Description: 71 CXL port objects are enumerated from either a platform firmware 72 device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 73 CXL component registers. The 'dportY' symlink identifies one or 74 more downstream ports that the upstream port may target in its 75 decode of CXL memory resources. The 'Y' integer reflects the 76 hardware port unique-id used in the hardware decoder target 77 list. 78 79What: /sys/bus/cxl/devices/decoderX.Y 80Date: June, 2021 81KernelVersion: v5.14 82Contact: linux-cxl@vger.kernel.org 83Description: 84 CXL decoder objects are enumerated from either a platform 85 firmware description, or a CXL HDM decoder register set in a 86 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 87 Capability Structure). The 'X' in decoderX.Y represents the 88 cxl_port container of this decoder, and 'Y' represents the 89 instance id of a given decoder resource. 90 91What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 92Date: June, 2021 93KernelVersion: v5.14 94Contact: linux-cxl@vger.kernel.org 95Description: 96 The 'start' and 'size' attributes together convey the physical 97 address base and number of bytes mapped in the decoder's decode 98 window. For decoders of devtype "cxl_decoder_root" the address 99 range is fixed. For decoders of devtype "cxl_decoder_switch" the 100 address is bounded by the decode range of the cxl_port ancestor 101 of the decoder's cxl_port, and dynamically updates based on the 102 active memory regions in that address space. 103 104What: /sys/bus/cxl/devices/decoderX.Y/locked 105Date: June, 2021 106KernelVersion: v5.14 107Contact: linux-cxl@vger.kernel.org 108Description: 109 CXL HDM decoders have the capability to lock the configuration 110 until the next device reset. For decoders of devtype 111 "cxl_decoder_root" there is no standard facility to unlock them. 112 For decoders of devtype "cxl_decoder_switch" a secondary bus 113 reset, of the PCIe bridge that provides the bus for this 114 decoders uport, unlocks / resets the decoder. 115 116What: /sys/bus/cxl/devices/decoderX.Y/target_list 117Date: June, 2021 118KernelVersion: v5.14 119Contact: linux-cxl@vger.kernel.org 120Description: 121 Display a comma separated list of the current decoder target 122 configuration. The list is ordered by the current configured 123 interleave order of the decoder's dport instances. Each entry in 124 the list is a dport id. 125 126What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 127Date: June, 2021 128KernelVersion: v5.14 129Contact: linux-cxl@vger.kernel.org 130Description: 131 When a CXL decoder is of devtype "cxl_decoder_root", it 132 represents a fixed memory window identified by platform 133 firmware. A fixed window may only support a subset of memory 134 types. The 'cap_*' attributes indicate whether persistent 135 memory, volatile memory, accelerator memory, and / or expander 136 memory may be mapped behind this decoder's memory window. 137 138What: /sys/bus/cxl/devices/decoderX.Y/target_type 139Date: June, 2021 140KernelVersion: v5.14 141Contact: linux-cxl@vger.kernel.org 142Description: 143 When a CXL decoder is of devtype "cxl_decoder_switch", it can 144 optionally decode either accelerator memory (type-2) or expander 145 memory (type-3). The 'target_type' attribute indicates the 146 current setting which may dynamically change based on what 147 memory regions are activated in this decode hierarchy. 148