1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/ram/size 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) "Volatile Only Capacity" as bytes. Represents the 27 identically named field in the Identify Memory Device Output 28 Payload in the CXL-2.0 specification. 29 30 31What: /sys/bus/cxl/devices/memX/pmem/size 32Date: December, 2020 33KernelVersion: v5.12 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) "Persistent Only Capacity" as bytes. Represents the 37 identically named field in the Identify Memory Device Output 38 Payload in the CXL-2.0 specification. 39 40 41What: /sys/bus/cxl/devices/memX/serial 42Date: January, 2022 43KernelVersion: v5.18 44Contact: linux-cxl@vger.kernel.org 45Description: 46 (RO) 64-bit serial number per the PCIe Device Serial Number 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 48 Memory Device PCIe Capabilities and Extended Capabilities. 49 50 51What: /sys/bus/cxl/devices/memX/numa_node 52Date: January, 2022 53KernelVersion: v5.18 54Contact: linux-cxl@vger.kernel.org 55Description: 56 (RO) If NUMA is enabled and the platform has affinitized the 57 host PCI device for this memory device, emit the CPU node 58 affinity for this device. 59 60 61What: /sys/bus/cxl/devices/memX/security/state 62Date: June, 2023 63KernelVersion: v6.5 64Contact: linux-cxl@vger.kernel.org 65Description: 66 (RO) Reading this file will display the CXL security state for 67 that device. Such states can be: 'disabled', or those available 68 only for persistent memory: 'locked', 'unlocked' or 'frozen'. 69 70 71What: /sys/bus/cxl/devices/*/devtype 72Date: June, 2021 73KernelVersion: v5.14 74Contact: linux-cxl@vger.kernel.org 75Description: 76 (RO) CXL device objects export the devtype attribute which 77 mirrors the same value communicated in the DEVTYPE environment 78 variable for uevents for devices on the "cxl" bus. 79 80 81What: /sys/bus/cxl/devices/*/modalias 82Date: December, 2021 83KernelVersion: v5.18 84Contact: linux-cxl@vger.kernel.org 85Description: 86 (RO) CXL device objects export the modalias attribute which 87 mirrors the same value communicated in the MODALIAS environment 88 variable for uevents for devices on the "cxl" bus. 89 90 91What: /sys/bus/cxl/devices/portX/uport 92Date: June, 2021 93KernelVersion: v5.14 94Contact: linux-cxl@vger.kernel.org 95Description: 96 (RO) CXL port objects are enumerated from either a platform 97 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 98 port with CXL component registers. The 'uport' symlink connects 99 the CXL portX object to the device that published the CXL port 100 capability. 101 102 103What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport 104Date: January, 2023 105KernelVersion: v6.3 106Contact: linux-cxl@vger.kernel.org 107Description: 108 (RO) CXL port objects are instantiated for each upstream port in 109 a CXL/PCIe switch, and for each endpoint to map the 110 corresponding memory device into the CXL port hierarchy. When a 111 descendant CXL port (switch or endpoint) is enumerated it is 112 useful to know which 'dport' object in the parent CXL port 113 routes to this descendant. The 'parent_dport' symlink points to 114 the device representing the downstream port of a CXL switch that 115 routes to {port,endpoint}X. 116 117 118What: /sys/bus/cxl/devices/portX/dportY 119Date: June, 2021 120KernelVersion: v5.14 121Contact: linux-cxl@vger.kernel.org 122Description: 123 (RO) CXL port objects are enumerated from either a platform 124 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 125 port with CXL component registers. The 'dportY' symlink 126 identifies one or more downstream ports that the upstream port 127 may target in its decode of CXL memory resources. The 'Y' 128 integer reflects the hardware port unique-id used in the 129 hardware decoder target list. 130 131 132What: /sys/bus/cxl/devices/decoderX.Y 133Date: June, 2021 134KernelVersion: v5.14 135Contact: linux-cxl@vger.kernel.org 136Description: 137 (RO) CXL decoder objects are enumerated from either a platform 138 firmware description, or a CXL HDM decoder register set in a 139 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 140 Capability Structure). The 'X' in decoderX.Y represents the 141 cxl_port container of this decoder, and 'Y' represents the 142 instance id of a given decoder resource. 143 144 145What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 146Date: June, 2021 147KernelVersion: v5.14 148Contact: linux-cxl@vger.kernel.org 149Description: 150 (RO) The 'start' and 'size' attributes together convey the 151 physical address base and number of bytes mapped in the 152 decoder's decode window. For decoders of devtype 153 "cxl_decoder_root" the address range is fixed. For decoders of 154 devtype "cxl_decoder_switch" the address is bounded by the 155 decode range of the cxl_port ancestor of the decoder's cxl_port, 156 and dynamically updates based on the active memory regions in 157 that address space. 158 159 160What: /sys/bus/cxl/devices/decoderX.Y/locked 161Date: June, 2021 162KernelVersion: v5.14 163Contact: linux-cxl@vger.kernel.org 164Description: 165 (RO) CXL HDM decoders have the capability to lock the 166 configuration until the next device reset. For decoders of 167 devtype "cxl_decoder_root" there is no standard facility to 168 unlock them. For decoders of devtype "cxl_decoder_switch" a 169 secondary bus reset, of the PCIe bridge that provides the bus 170 for this decoders uport, unlocks / resets the decoder. 171 172 173What: /sys/bus/cxl/devices/decoderX.Y/target_list 174Date: June, 2021 175KernelVersion: v5.14 176Contact: linux-cxl@vger.kernel.org 177Description: 178 (RO) Display a comma separated list of the current decoder 179 target configuration. The list is ordered by the current 180 configured interleave order of the decoder's dport instances. 181 Each entry in the list is a dport id. 182 183 184What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 185Date: June, 2021 186KernelVersion: v5.14 187Contact: linux-cxl@vger.kernel.org 188Description: 189 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 190 represents a fixed memory window identified by platform 191 firmware. A fixed window may only support a subset of memory 192 types. The 'cap_*' attributes indicate whether persistent 193 memory, volatile memory, accelerator memory, and / or expander 194 memory may be mapped behind this decoder's memory window. 195 196 197What: /sys/bus/cxl/devices/decoderX.Y/target_type 198Date: June, 2021 199KernelVersion: v5.14 200Contact: linux-cxl@vger.kernel.org 201Description: 202 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 203 can optionally decode either accelerator memory (type-2) or 204 expander memory (type-3). The 'target_type' attribute indicates 205 the current setting which may dynamically change based on what 206 memory regions are activated in this decode hierarchy. 207 208 209What: /sys/bus/cxl/devices/endpointX/CDAT 210Date: July, 2022 211KernelVersion: v6.0 212Contact: linux-cxl@vger.kernel.org 213Description: 214 (RO) If this sysfs entry is not present no DOE mailbox was 215 found to support CDAT data. If it is present and the length of 216 the data is 0 reading the CDAT data failed. Otherwise the CDAT 217 data is reported. 218 219 220What: /sys/bus/cxl/devices/decoderX.Y/mode 221Date: May, 2022 222KernelVersion: v6.0 223Contact: linux-cxl@vger.kernel.org 224Description: 225 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 226 translates from a host physical address range, to a device local 227 address range. Device-local address ranges are further split 228 into a 'ram' (volatile memory) range and 'pmem' (persistent 229 memory) range. The 'mode' attribute emits one of 'ram', 'pmem', 230 'mixed', or 'none'. The 'mixed' indication is for error cases 231 when a decoder straddles the volatile/persistent partition 232 boundary, and 'none' indicates the decoder is not actively 233 decoding, or no DPA allocation policy has been set. 234 235 'mode' can be written, when the decoder is in the 'disabled' 236 state, with either 'ram' or 'pmem' to set the boundaries for the 237 next allocation. 238 239 240What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 241Date: May, 2022 242KernelVersion: v6.0 243Contact: linux-cxl@vger.kernel.org 244Description: 245 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 246 and its 'dpa_size' attribute is non-zero, this attribute 247 indicates the device physical address (DPA) base address of the 248 allocation. 249 250 251What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 252Date: May, 2022 253KernelVersion: v6.0 254Contact: linux-cxl@vger.kernel.org 255Description: 256 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 257 translates from a host physical address range, to a device local 258 address range. The range, base address plus length in bytes, of 259 DPA allocated to this decoder is conveyed in these 2 attributes. 260 Allocations can be mutated as long as the decoder is in the 261 disabled state. A write to 'dpa_size' releases the previous DPA 262 allocation and then attempts to allocate from the free capacity 263 in the device partition referred to by 'decoderX.Y/mode'. 264 Allocate and free requests can only be performed on the highest 265 instance number disabled decoder with non-zero size. I.e. 266 allocations are enforced to occur in increasing 'decoderX.Y/id' 267 order and frees are enforced to occur in decreasing 268 'decoderX.Y/id' order. 269 270 271What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 272Date: May, 2022 273KernelVersion: v6.0 274Contact: linux-cxl@vger.kernel.org 275Description: 276 (RO) The number of targets across which this decoder's host 277 physical address (HPA) memory range is interleaved. The device 278 maps every Nth block of HPA (of size == 279 'interleave_granularity') to consecutive DPA addresses. The 280 decoder's position in the interleave is determined by the 281 device's (endpoint or switch) switch ancestry. For root 282 decoders their interleave is specified by platform firmware and 283 they only specify a downstream target order for host bridges. 284 285 286What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 287Date: May, 2022 288KernelVersion: v6.0 289Contact: linux-cxl@vger.kernel.org 290Description: 291 (RO) The number of consecutive bytes of host physical address 292 space this decoder claims at address N before the decode rotates 293 to the next target in the interleave at address N + 294 interleave_granularity (assuming N is aligned to 295 interleave_granularity). 296 297 298What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region 299Date: May, 2022, January, 2023 300KernelVersion: v6.0 (pmem), v6.3 (ram) 301Contact: linux-cxl@vger.kernel.org 302Description: 303 (RW) Write a string in the form 'regionZ' to start the process 304 of defining a new persistent, or volatile memory region 305 (interleave-set) within the decode range bounded by root decoder 306 'decoderX.Y'. The value written must match the current value 307 returned from reading this attribute. An atomic compare exchange 308 operation is done on write to assign the requested id to a 309 region and allocate the region-id for the next creation attempt. 310 EBUSY is returned if the region name written does not match the 311 current cached value. 312 313 314What: /sys/bus/cxl/devices/decoderX.Y/delete_region 315Date: May, 2022 316KernelVersion: v6.0 317Contact: linux-cxl@vger.kernel.org 318Description: 319 (WO) Write a string in the form 'regionZ' to delete that region, 320 provided it is currently idle / not bound to a driver. 321 322 323What: /sys/bus/cxl/devices/regionZ/uuid 324Date: May, 2022 325KernelVersion: v6.0 326Contact: linux-cxl@vger.kernel.org 327Description: 328 (RW) Write a unique identifier for the region. This field must 329 be set for persistent regions and it must not conflict with the 330 UUID of another region. For volatile ram regions this 331 attribute is a read-only empty string. 332 333 334What: /sys/bus/cxl/devices/regionZ/interleave_granularity 335Date: May, 2022 336KernelVersion: v6.0 337Contact: linux-cxl@vger.kernel.org 338Description: 339 (RW) Set the number of consecutive bytes each device in the 340 interleave set will claim. The possible interleave granularity 341 values are determined by the CXL spec and the participating 342 devices. 343 344 345What: /sys/bus/cxl/devices/regionZ/interleave_ways 346Date: May, 2022 347KernelVersion: v6.0 348Contact: linux-cxl@vger.kernel.org 349Description: 350 (RW) Configures the number of devices participating in the 351 region is set by writing this value. Each device will provide 352 1/interleave_ways of storage for the region. 353 354 355What: /sys/bus/cxl/devices/regionZ/size 356Date: May, 2022 357KernelVersion: v6.0 358Contact: linux-cxl@vger.kernel.org 359Description: 360 (RW) System physical address space to be consumed by the region. 361 When written trigger the driver to allocate space out of the 362 parent root decoder's address space. When read the size of the 363 address space is reported and should match the span of the 364 region's resource attribute. Size shall be set after the 365 interleave configuration parameters. Once set it cannot be 366 changed, only freed by writing 0. The kernel makes no guarantees 367 that data is maintained over an address space freeing event, and 368 there is no guarantee that a free followed by an allocate 369 results in the same address being allocated. 370 371 372What: /sys/bus/cxl/devices/regionZ/mode 373Date: January, 2023 374KernelVersion: v6.3 375Contact: linux-cxl@vger.kernel.org 376Description: 377 (RO) The mode of a region is established at region creation time 378 and dictates the mode of the endpoint decoder that comprise the 379 region. For more details on the possible modes see 380 /sys/bus/cxl/devices/decoderX.Y/mode 381 382 383What: /sys/bus/cxl/devices/regionZ/resource 384Date: May, 2022 385KernelVersion: v6.0 386Contact: linux-cxl@vger.kernel.org 387Description: 388 (RO) A region is a contiguous partition of a CXL root decoder 389 address space. Region capacity is allocated by writing to the 390 size attribute, the resulting physical address space determined 391 by the driver is reflected here. It is therefore not useful to 392 read this before writing a value to the size attribute. 393 394 395What: /sys/bus/cxl/devices/regionZ/target[0..N] 396Date: May, 2022 397KernelVersion: v6.0 398Contact: linux-cxl@vger.kernel.org 399Description: 400 (RW) Write an endpoint decoder object name to 'targetX' where X 401 is the intended position of the endpoint device in the region 402 interleave and N is the 'interleave_ways' setting for the 403 region. ENXIO is returned if the write results in an impossible 404 to map decode scenario, like the endpoint is unreachable at that 405 position relative to the root decoder interleave. EBUSY is 406 returned if the position in the region is already occupied, or 407 if the region is not in a state to accept interleave 408 configuration changes. EINVAL is returned if the object name is 409 not an endpoint decoder. Once all positions have been 410 successfully written a final validation for decode conflicts is 411 performed before activating the region. 412 413 414What: /sys/bus/cxl/devices/regionZ/commit 415Date: May, 2022 416KernelVersion: v6.0 417Contact: linux-cxl@vger.kernel.org 418Description: 419 (RW) Write a boolean 'true' string value to this attribute to 420 trigger the region to transition from the software programmed 421 state to the actively decoding in hardware state. The commit 422 operation in addition to validating that the region is in proper 423 configured state, validates that the decoders are being 424 committed in spec mandated order (last committed decoder id + 425 1), and checks that the hardware accepts the commit request. 426 Reading this value indicates whether the region is committed or 427 not. 428 429 430What: /sys/bus/cxl/devices/memX/trigger_poison_list 431Date: April, 2023 432KernelVersion: v6.4 433Contact: linux-cxl@vger.kernel.org 434Description: 435 (WO) When a boolean 'true' is written to this attribute the 436 memdev driver retrieves the poison list from the device. The 437 list consists of addresses that are poisoned, or would result 438 in poison if accessed, and the source of the poison. This 439 attribute is only visible for devices supporting the 440 capability. The retrieved errors are logged as kernel 441 events when cxl_poison event tracing is enabled. 442