1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/ram/size 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) "Volatile Only Capacity" as bytes. Represents the 27 identically named field in the Identify Memory Device Output 28 Payload in the CXL-2.0 specification. 29 30 31What: /sys/bus/cxl/devices/memX/pmem/size 32Date: December, 2020 33KernelVersion: v5.12 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) "Persistent Only Capacity" as bytes. Represents the 37 identically named field in the Identify Memory Device Output 38 Payload in the CXL-2.0 specification. 39 40 41What: /sys/bus/cxl/devices/memX/serial 42Date: January, 2022 43KernelVersion: v5.18 44Contact: linux-cxl@vger.kernel.org 45Description: 46 (RO) 64-bit serial number per the PCIe Device Serial Number 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 48 Memory Device PCIe Capabilities and Extended Capabilities. 49 50 51What: /sys/bus/cxl/devices/memX/numa_node 52Date: January, 2022 53KernelVersion: v5.18 54Contact: linux-cxl@vger.kernel.org 55Description: 56 (RO) If NUMA is enabled and the platform has affinitized the 57 host PCI device for this memory device, emit the CPU node 58 affinity for this device. 59 60 61What: /sys/bus/cxl/devices/memX/firmware/ 62Date: April, 2023 63KernelVersion: v6.5 64Contact: linux-cxl@vger.kernel.org 65Description: 66 (RW) Firmware uploader mechanism. The different files under 67 this directory can be used to upload and activate new 68 firmware for CXL devices. The interfaces under this are 69 documented in sysfs-class-firmware. 70 71 72What: /sys/bus/cxl/devices/*/devtype 73Date: June, 2021 74KernelVersion: v5.14 75Contact: linux-cxl@vger.kernel.org 76Description: 77 (RO) CXL device objects export the devtype attribute which 78 mirrors the same value communicated in the DEVTYPE environment 79 variable for uevents for devices on the "cxl" bus. 80 81 82What: /sys/bus/cxl/devices/*/modalias 83Date: December, 2021 84KernelVersion: v5.18 85Contact: linux-cxl@vger.kernel.org 86Description: 87 (RO) CXL device objects export the modalias attribute which 88 mirrors the same value communicated in the MODALIAS environment 89 variable for uevents for devices on the "cxl" bus. 90 91 92What: /sys/bus/cxl/devices/portX/uport 93Date: June, 2021 94KernelVersion: v5.14 95Contact: linux-cxl@vger.kernel.org 96Description: 97 (RO) CXL port objects are enumerated from either a platform 98 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 99 port with CXL component registers. The 'uport' symlink connects 100 the CXL portX object to the device that published the CXL port 101 capability. 102 103 104What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport 105Date: January, 2023 106KernelVersion: v6.3 107Contact: linux-cxl@vger.kernel.org 108Description: 109 (RO) CXL port objects are instantiated for each upstream port in 110 a CXL/PCIe switch, and for each endpoint to map the 111 corresponding memory device into the CXL port hierarchy. When a 112 descendant CXL port (switch or endpoint) is enumerated it is 113 useful to know which 'dport' object in the parent CXL port 114 routes to this descendant. The 'parent_dport' symlink points to 115 the device representing the downstream port of a CXL switch that 116 routes to {port,endpoint}X. 117 118 119What: /sys/bus/cxl/devices/portX/dportY 120Date: June, 2021 121KernelVersion: v5.14 122Contact: linux-cxl@vger.kernel.org 123Description: 124 (RO) CXL port objects are enumerated from either a platform 125 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 126 port with CXL component registers. The 'dportY' symlink 127 identifies one or more downstream ports that the upstream port 128 may target in its decode of CXL memory resources. The 'Y' 129 integer reflects the hardware port unique-id used in the 130 hardware decoder target list. 131 132 133What: /sys/bus/cxl/devices/decoderX.Y 134Date: June, 2021 135KernelVersion: v5.14 136Contact: linux-cxl@vger.kernel.org 137Description: 138 (RO) CXL decoder objects are enumerated from either a platform 139 firmware description, or a CXL HDM decoder register set in a 140 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 141 Capability Structure). The 'X' in decoderX.Y represents the 142 cxl_port container of this decoder, and 'Y' represents the 143 instance id of a given decoder resource. 144 145 146What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 147Date: June, 2021 148KernelVersion: v5.14 149Contact: linux-cxl@vger.kernel.org 150Description: 151 (RO) The 'start' and 'size' attributes together convey the 152 physical address base and number of bytes mapped in the 153 decoder's decode window. For decoders of devtype 154 "cxl_decoder_root" the address range is fixed. For decoders of 155 devtype "cxl_decoder_switch" the address is bounded by the 156 decode range of the cxl_port ancestor of the decoder's cxl_port, 157 and dynamically updates based on the active memory regions in 158 that address space. 159 160 161What: /sys/bus/cxl/devices/decoderX.Y/locked 162Date: June, 2021 163KernelVersion: v5.14 164Contact: linux-cxl@vger.kernel.org 165Description: 166 (RO) CXL HDM decoders have the capability to lock the 167 configuration until the next device reset. For decoders of 168 devtype "cxl_decoder_root" there is no standard facility to 169 unlock them. For decoders of devtype "cxl_decoder_switch" a 170 secondary bus reset, of the PCIe bridge that provides the bus 171 for this decoders uport, unlocks / resets the decoder. 172 173 174What: /sys/bus/cxl/devices/decoderX.Y/target_list 175Date: June, 2021 176KernelVersion: v5.14 177Contact: linux-cxl@vger.kernel.org 178Description: 179 (RO) Display a comma separated list of the current decoder 180 target configuration. The list is ordered by the current 181 configured interleave order of the decoder's dport instances. 182 Each entry in the list is a dport id. 183 184 185What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 186Date: June, 2021 187KernelVersion: v5.14 188Contact: linux-cxl@vger.kernel.org 189Description: 190 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 191 represents a fixed memory window identified by platform 192 firmware. A fixed window may only support a subset of memory 193 types. The 'cap_*' attributes indicate whether persistent 194 memory, volatile memory, accelerator memory, and / or expander 195 memory may be mapped behind this decoder's memory window. 196 197 198What: /sys/bus/cxl/devices/decoderX.Y/target_type 199Date: June, 2021 200KernelVersion: v5.14 201Contact: linux-cxl@vger.kernel.org 202Description: 203 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 204 can optionally decode either accelerator memory (type-2) or 205 expander memory (type-3). The 'target_type' attribute indicates 206 the current setting which may dynamically change based on what 207 memory regions are activated in this decode hierarchy. 208 209 210What: /sys/bus/cxl/devices/endpointX/CDAT 211Date: July, 2022 212KernelVersion: v6.0 213Contact: linux-cxl@vger.kernel.org 214Description: 215 (RO) If this sysfs entry is not present no DOE mailbox was 216 found to support CDAT data. If it is present and the length of 217 the data is 0 reading the CDAT data failed. Otherwise the CDAT 218 data is reported. 219 220 221What: /sys/bus/cxl/devices/decoderX.Y/mode 222Date: May, 2022 223KernelVersion: v6.0 224Contact: linux-cxl@vger.kernel.org 225Description: 226 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 227 translates from a host physical address range, to a device local 228 address range. Device-local address ranges are further split 229 into a 'ram' (volatile memory) range and 'pmem' (persistent 230 memory) range. The 'mode' attribute emits one of 'ram', 'pmem', 231 'mixed', or 'none'. The 'mixed' indication is for error cases 232 when a decoder straddles the volatile/persistent partition 233 boundary, and 'none' indicates the decoder is not actively 234 decoding, or no DPA allocation policy has been set. 235 236 'mode' can be written, when the decoder is in the 'disabled' 237 state, with either 'ram' or 'pmem' to set the boundaries for the 238 next allocation. 239 240 241What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 242Date: May, 2022 243KernelVersion: v6.0 244Contact: linux-cxl@vger.kernel.org 245Description: 246 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 247 and its 'dpa_size' attribute is non-zero, this attribute 248 indicates the device physical address (DPA) base address of the 249 allocation. 250 251 252What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 253Date: May, 2022 254KernelVersion: v6.0 255Contact: linux-cxl@vger.kernel.org 256Description: 257 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 258 translates from a host physical address range, to a device local 259 address range. The range, base address plus length in bytes, of 260 DPA allocated to this decoder is conveyed in these 2 attributes. 261 Allocations can be mutated as long as the decoder is in the 262 disabled state. A write to 'dpa_size' releases the previous DPA 263 allocation and then attempts to allocate from the free capacity 264 in the device partition referred to by 'decoderX.Y/mode'. 265 Allocate and free requests can only be performed on the highest 266 instance number disabled decoder with non-zero size. I.e. 267 allocations are enforced to occur in increasing 'decoderX.Y/id' 268 order and frees are enforced to occur in decreasing 269 'decoderX.Y/id' order. 270 271 272What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 273Date: May, 2022 274KernelVersion: v6.0 275Contact: linux-cxl@vger.kernel.org 276Description: 277 (RO) The number of targets across which this decoder's host 278 physical address (HPA) memory range is interleaved. The device 279 maps every Nth block of HPA (of size == 280 'interleave_granularity') to consecutive DPA addresses. The 281 decoder's position in the interleave is determined by the 282 device's (endpoint or switch) switch ancestry. For root 283 decoders their interleave is specified by platform firmware and 284 they only specify a downstream target order for host bridges. 285 286 287What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 288Date: May, 2022 289KernelVersion: v6.0 290Contact: linux-cxl@vger.kernel.org 291Description: 292 (RO) The number of consecutive bytes of host physical address 293 space this decoder claims at address N before the decode rotates 294 to the next target in the interleave at address N + 295 interleave_granularity (assuming N is aligned to 296 interleave_granularity). 297 298 299What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region 300Date: May, 2022, January, 2023 301KernelVersion: v6.0 (pmem), v6.3 (ram) 302Contact: linux-cxl@vger.kernel.org 303Description: 304 (RW) Write a string in the form 'regionZ' to start the process 305 of defining a new persistent, or volatile memory region 306 (interleave-set) within the decode range bounded by root decoder 307 'decoderX.Y'. The value written must match the current value 308 returned from reading this attribute. An atomic compare exchange 309 operation is done on write to assign the requested id to a 310 region and allocate the region-id for the next creation attempt. 311 EBUSY is returned if the region name written does not match the 312 current cached value. 313 314 315What: /sys/bus/cxl/devices/decoderX.Y/delete_region 316Date: May, 2022 317KernelVersion: v6.0 318Contact: linux-cxl@vger.kernel.org 319Description: 320 (WO) Write a string in the form 'regionZ' to delete that region, 321 provided it is currently idle / not bound to a driver. 322 323 324What: /sys/bus/cxl/devices/regionZ/uuid 325Date: May, 2022 326KernelVersion: v6.0 327Contact: linux-cxl@vger.kernel.org 328Description: 329 (RW) Write a unique identifier for the region. This field must 330 be set for persistent regions and it must not conflict with the 331 UUID of another region. For volatile ram regions this 332 attribute is a read-only empty string. 333 334 335What: /sys/bus/cxl/devices/regionZ/interleave_granularity 336Date: May, 2022 337KernelVersion: v6.0 338Contact: linux-cxl@vger.kernel.org 339Description: 340 (RW) Set the number of consecutive bytes each device in the 341 interleave set will claim. The possible interleave granularity 342 values are determined by the CXL spec and the participating 343 devices. 344 345 346What: /sys/bus/cxl/devices/regionZ/interleave_ways 347Date: May, 2022 348KernelVersion: v6.0 349Contact: linux-cxl@vger.kernel.org 350Description: 351 (RW) Configures the number of devices participating in the 352 region is set by writing this value. Each device will provide 353 1/interleave_ways of storage for the region. 354 355 356What: /sys/bus/cxl/devices/regionZ/size 357Date: May, 2022 358KernelVersion: v6.0 359Contact: linux-cxl@vger.kernel.org 360Description: 361 (RW) System physical address space to be consumed by the region. 362 When written trigger the driver to allocate space out of the 363 parent root decoder's address space. When read the size of the 364 address space is reported and should match the span of the 365 region's resource attribute. Size shall be set after the 366 interleave configuration parameters. Once set it cannot be 367 changed, only freed by writing 0. The kernel makes no guarantees 368 that data is maintained over an address space freeing event, and 369 there is no guarantee that a free followed by an allocate 370 results in the same address being allocated. 371 372 373What: /sys/bus/cxl/devices/regionZ/mode 374Date: January, 2023 375KernelVersion: v6.3 376Contact: linux-cxl@vger.kernel.org 377Description: 378 (RO) The mode of a region is established at region creation time 379 and dictates the mode of the endpoint decoder that comprise the 380 region. For more details on the possible modes see 381 /sys/bus/cxl/devices/decoderX.Y/mode 382 383 384What: /sys/bus/cxl/devices/regionZ/resource 385Date: May, 2022 386KernelVersion: v6.0 387Contact: linux-cxl@vger.kernel.org 388Description: 389 (RO) A region is a contiguous partition of a CXL root decoder 390 address space. Region capacity is allocated by writing to the 391 size attribute, the resulting physical address space determined 392 by the driver is reflected here. It is therefore not useful to 393 read this before writing a value to the size attribute. 394 395 396What: /sys/bus/cxl/devices/regionZ/target[0..N] 397Date: May, 2022 398KernelVersion: v6.0 399Contact: linux-cxl@vger.kernel.org 400Description: 401 (RW) Write an endpoint decoder object name to 'targetX' where X 402 is the intended position of the endpoint device in the region 403 interleave and N is the 'interleave_ways' setting for the 404 region. ENXIO is returned if the write results in an impossible 405 to map decode scenario, like the endpoint is unreachable at that 406 position relative to the root decoder interleave. EBUSY is 407 returned if the position in the region is already occupied, or 408 if the region is not in a state to accept interleave 409 configuration changes. EINVAL is returned if the object name is 410 not an endpoint decoder. Once all positions have been 411 successfully written a final validation for decode conflicts is 412 performed before activating the region. 413 414 415What: /sys/bus/cxl/devices/regionZ/commit 416Date: May, 2022 417KernelVersion: v6.0 418Contact: linux-cxl@vger.kernel.org 419Description: 420 (RW) Write a boolean 'true' string value to this attribute to 421 trigger the region to transition from the software programmed 422 state to the actively decoding in hardware state. The commit 423 operation in addition to validating that the region is in proper 424 configured state, validates that the decoders are being 425 committed in spec mandated order (last committed decoder id + 426 1), and checks that the hardware accepts the commit request. 427 Reading this value indicates whether the region is committed or 428 not. 429 430 431What: /sys/bus/cxl/devices/memX/trigger_poison_list 432Date: April, 2023 433KernelVersion: v6.4 434Contact: linux-cxl@vger.kernel.org 435Description: 436 (WO) When a boolean 'true' is written to this attribute the 437 memdev driver retrieves the poison list from the device. The 438 list consists of addresses that are poisoned, or would result 439 in poison if accessed, and the source of the poison. This 440 attribute is only visible for devices supporting the 441 capability. The retrieved errors are logged as kernel 442 events when cxl_poison event tracing is enabled. 443