1What:		/sys/bus/cxl/devices/memX/firmware_version
2Date:		December, 2020
3KernelVersion:	v5.12
4Contact:	linux-cxl@vger.kernel.org
5Description:
6		(RO) "FW Revision" string as reported by the Identify
7		Memory Device Output Payload in the CXL-2.0
8		specification.
9
10What:		/sys/bus/cxl/devices/memX/ram/size
11Date:		December, 2020
12KernelVersion:	v5.12
13Contact:	linux-cxl@vger.kernel.org
14Description:
15		(RO) "Volatile Only Capacity" as bytes. Represents the
16		identically named field in the Identify Memory Device Output
17		Payload in the CXL-2.0 specification.
18
19What:		/sys/bus/cxl/devices/memX/pmem/size
20Date:		December, 2020
21KernelVersion:	v5.12
22Contact:	linux-cxl@vger.kernel.org
23Description:
24		(RO) "Persistent Only Capacity" as bytes. Represents the
25		identically named field in the Identify Memory Device Output
26		Payload in the CXL-2.0 specification.
27
28What:		/sys/bus/cxl/devices/*/devtype
29Date:		June, 2021
30KernelVersion:	v5.14
31Contact:	linux-cxl@vger.kernel.org
32Description:
33		CXL device objects export the devtype attribute which mirrors
34		the same value communicated in the DEVTYPE environment variable
35		for uevents for devices on the "cxl" bus.
36
37What:		/sys/bus/cxl/devices/*/modalias
38Date:		December, 2021
39KernelVersion:	v5.18
40Contact:	linux-cxl@vger.kernel.org
41Description:
42		CXL device objects export the modalias attribute which mirrors
43		the same value communicated in the MODALIAS environment variable
44		for uevents for devices on the "cxl" bus.
45
46What:		/sys/bus/cxl/devices/portX/uport
47Date:		June, 2021
48KernelVersion:	v5.14
49Contact:	linux-cxl@vger.kernel.org
50Description:
51		CXL port objects are enumerated from either a platform firmware
52		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
53		CXL component registers. The 'uport' symlink connects the CXL
54		portX object to the device that published the CXL port
55		capability.
56
57What:		/sys/bus/cxl/devices/portX/dportY
58Date:		June, 2021
59KernelVersion:	v5.14
60Contact:	linux-cxl@vger.kernel.org
61Description:
62		CXL port objects are enumerated from either a platform firmware
63		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
64		CXL component registers. The 'dportY' symlink identifies one or
65		more downstream ports that the upstream port may target in its
66		decode of CXL memory resources.  The 'Y' integer reflects the
67		hardware port unique-id used in the hardware decoder target
68		list.
69
70What:		/sys/bus/cxl/devices/decoderX.Y
71Date:		June, 2021
72KernelVersion:	v5.14
73Contact:	linux-cxl@vger.kernel.org
74Description:
75		CXL decoder objects are enumerated from either a platform
76		firmware description, or a CXL HDM decoder register set in a
77		PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
78		Capability Structure). The 'X' in decoderX.Y represents the
79		cxl_port container of this decoder, and 'Y' represents the
80		instance id of a given decoder resource.
81
82What:		/sys/bus/cxl/devices/decoderX.Y/{start,size}
83Date:		June, 2021
84KernelVersion:	v5.14
85Contact:	linux-cxl@vger.kernel.org
86Description:
87		The 'start' and 'size' attributes together convey the physical
88		address base and number of bytes mapped in the decoder's decode
89		window. For decoders of devtype "cxl_decoder_root" the address
90		range is fixed. For decoders of devtype "cxl_decoder_switch" the
91		address is bounded by the decode range of the cxl_port ancestor
92		of the decoder's cxl_port, and dynamically updates based on the
93		active memory regions in that address space.
94
95What:		/sys/bus/cxl/devices/decoderX.Y/locked
96Date:		June, 2021
97KernelVersion:	v5.14
98Contact:	linux-cxl@vger.kernel.org
99Description:
100		CXL HDM decoders have the capability to lock the configuration
101		until the next device reset. For decoders of devtype
102		"cxl_decoder_root" there is no standard facility to unlock them.
103		For decoders of devtype "cxl_decoder_switch" a secondary bus
104		reset, of the PCIe bridge that provides the bus for this
105		decoders uport, unlocks / resets the decoder.
106
107What:		/sys/bus/cxl/devices/decoderX.Y/target_list
108Date:		June, 2021
109KernelVersion:	v5.14
110Contact:	linux-cxl@vger.kernel.org
111Description:
112		Display a comma separated list of the current decoder target
113		configuration. The list is ordered by the current configured
114		interleave order of the decoder's dport instances. Each entry in
115		the list is a dport id.
116
117What:		/sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
118Date:		June, 2021
119KernelVersion:	v5.14
120Contact:	linux-cxl@vger.kernel.org
121Description:
122		When a CXL decoder is of devtype "cxl_decoder_root", it
123		represents a fixed memory window identified by platform
124		firmware. A fixed window may only support a subset of memory
125		types. The 'cap_*' attributes indicate whether persistent
126		memory, volatile memory, accelerator memory, and / or expander
127		memory may be mapped behind this decoder's memory window.
128
129What:		/sys/bus/cxl/devices/decoderX.Y/target_type
130Date:		June, 2021
131KernelVersion:	v5.14
132Contact:	linux-cxl@vger.kernel.org
133Description:
134		When a CXL decoder is of devtype "cxl_decoder_switch", it can
135		optionally decode either accelerator memory (type-2) or expander
136		memory (type-3). The 'target_type' attribute indicates the
137		current setting which may dynamically change based on what
138		memory regions are activated in this decode hierarchy.
139