1What:		/sys/bus/cxl/devices/memX/firmware_version
2Date:		December, 2020
3KernelVersion:	v5.12
4Contact:	linux-cxl@vger.kernel.org
5Description:
6		(RO) "FW Revision" string as reported by the Identify
7		Memory Device Output Payload in the CXL-2.0
8		specification.
9
10What:		/sys/bus/cxl/devices/memX/ram/size
11Date:		December, 2020
12KernelVersion:	v5.12
13Contact:	linux-cxl@vger.kernel.org
14Description:
15		(RO) "Volatile Only Capacity" as bytes. Represents the
16		identically named field in the Identify Memory Device Output
17		Payload in the CXL-2.0 specification.
18
19What:		/sys/bus/cxl/devices/memX/pmem/size
20Date:		December, 2020
21KernelVersion:	v5.12
22Contact:	linux-cxl@vger.kernel.org
23Description:
24		(RO) "Persistent Only Capacity" as bytes. Represents the
25		identically named field in the Identify Memory Device Output
26		Payload in the CXL-2.0 specification.
27
28What:		/sys/bus/cxl/devices/*/devtype
29Date:		June, 2021
30KernelVersion:	v5.14
31Contact:	linux-cxl@vger.kernel.org
32Description:
33		CXL device objects export the devtype attribute which mirrors
34		the same value communicated in the DEVTYPE environment variable
35		for uevents for devices on the "cxl" bus.
36
37What:		/sys/bus/cxl/devices/portX/uport
38Date:		June, 2021
39KernelVersion:	v5.14
40Contact:	linux-cxl@vger.kernel.org
41Description:
42		CXL port objects are enumerated from either a platform firmware
43		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
44		CXL component registers. The 'uport' symlink connects the CXL
45		portX object to the device that published the CXL port
46		capability.
47
48What:		/sys/bus/cxl/devices/portX/dportY
49Date:		June, 2021
50KernelVersion:	v5.14
51Contact:	linux-cxl@vger.kernel.org
52Description:
53		CXL port objects are enumerated from either a platform firmware
54		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
55		CXL component registers. The 'dportY' symlink identifies one or
56		more downstream ports that the upstream port may target in its
57		decode of CXL memory resources.  The 'Y' integer reflects the
58		hardware port unique-id used in the hardware decoder target
59		list.
60