1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/ram/size 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) "Volatile Only Capacity" as bytes. Represents the 27 identically named field in the Identify Memory Device Output 28 Payload in the CXL-2.0 specification. 29 30 31What: /sys/bus/cxl/devices/memX/pmem/size 32Date: December, 2020 33KernelVersion: v5.12 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) "Persistent Only Capacity" as bytes. Represents the 37 identically named field in the Identify Memory Device Output 38 Payload in the CXL-2.0 specification. 39 40 41What: /sys/bus/cxl/devices/memX/serial 42Date: January, 2022 43KernelVersion: v5.18 44Contact: linux-cxl@vger.kernel.org 45Description: 46 (RO) 64-bit serial number per the PCIe Device Serial Number 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 48 Memory Device PCIe Capabilities and Extended Capabilities. 49 50 51What: /sys/bus/cxl/devices/memX/numa_node 52Date: January, 2022 53KernelVersion: v5.18 54Contact: linux-cxl@vger.kernel.org 55Description: 56 (RO) If NUMA is enabled and the platform has affinitized the 57 host PCI device for this memory device, emit the CPU node 58 affinity for this device. 59 60 61What: /sys/bus/cxl/devices/memX/security/state 62Date: June, 2023 63KernelVersion: v6.5 64Contact: linux-cxl@vger.kernel.org 65Description: 66 (RO) Reading this file will display the CXL security state for 67 that device. Such states can be: 'disabled', 'sanitize', when 68 a sanitization is currently underway; or those available only 69 for persistent memory: 'locked', 'unlocked' or 'frozen'. This 70 sysfs entry is select/poll capable from userspace to notify 71 upon completion of a sanitize operation. 72 73 74What: /sys/bus/cxl/devices/memX/security/sanitize 75Date: June, 2023 76KernelVersion: v6.5 77Contact: linux-cxl@vger.kernel.org 78Description: 79 (WO) Write a boolean 'true' string value to this attribute to 80 sanitize the device to securely re-purpose or decommission it. 81 This is done by ensuring that all user data and meta-data, 82 whether it resides in persistent capacity, volatile capacity, 83 or the LSA, is made permanently unavailable by whatever means 84 is appropriate for the media type. This functionality requires 85 the device to be not be actively decoding any HPA ranges. 86 87 88What /sys/bus/cxl/devices/memX/security/erase 89Date: June, 2023 90KernelVersion: v6.5 91Contact: linux-cxl@vger.kernel.org 92Description: 93 (WO) Write a boolean 'true' string value to this attribute to 94 secure erase user data by changing the media encryption keys for 95 all user data areas of the device. 96 97 98What: /sys/bus/cxl/devices/memX/firmware/ 99Date: April, 2023 100KernelVersion: v6.5 101Contact: linux-cxl@vger.kernel.org 102Description: 103 (RW) Firmware uploader mechanism. The different files under 104 this directory can be used to upload and activate new 105 firmware for CXL devices. The interfaces under this are 106 documented in sysfs-class-firmware. 107 108 109What: /sys/bus/cxl/devices/*/devtype 110Date: June, 2021 111KernelVersion: v5.14 112Contact: linux-cxl@vger.kernel.org 113Description: 114 (RO) CXL device objects export the devtype attribute which 115 mirrors the same value communicated in the DEVTYPE environment 116 variable for uevents for devices on the "cxl" bus. 117 118 119What: /sys/bus/cxl/devices/*/modalias 120Date: December, 2021 121KernelVersion: v5.18 122Contact: linux-cxl@vger.kernel.org 123Description: 124 (RO) CXL device objects export the modalias attribute which 125 mirrors the same value communicated in the MODALIAS environment 126 variable for uevents for devices on the "cxl" bus. 127 128 129What: /sys/bus/cxl/devices/portX/uport 130Date: June, 2021 131KernelVersion: v5.14 132Contact: linux-cxl@vger.kernel.org 133Description: 134 (RO) CXL port objects are enumerated from either a platform 135 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 136 port with CXL component registers. The 'uport' symlink connects 137 the CXL portX object to the device that published the CXL port 138 capability. 139 140 141What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport 142Date: January, 2023 143KernelVersion: v6.3 144Contact: linux-cxl@vger.kernel.org 145Description: 146 (RO) CXL port objects are instantiated for each upstream port in 147 a CXL/PCIe switch, and for each endpoint to map the 148 corresponding memory device into the CXL port hierarchy. When a 149 descendant CXL port (switch or endpoint) is enumerated it is 150 useful to know which 'dport' object in the parent CXL port 151 routes to this descendant. The 'parent_dport' symlink points to 152 the device representing the downstream port of a CXL switch that 153 routes to {port,endpoint}X. 154 155 156What: /sys/bus/cxl/devices/portX/dportY 157Date: June, 2021 158KernelVersion: v5.14 159Contact: linux-cxl@vger.kernel.org 160Description: 161 (RO) CXL port objects are enumerated from either a platform 162 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 163 port with CXL component registers. The 'dportY' symlink 164 identifies one or more downstream ports that the upstream port 165 may target in its decode of CXL memory resources. The 'Y' 166 integer reflects the hardware port unique-id used in the 167 hardware decoder target list. 168 169 170What: /sys/bus/cxl/devices/decoderX.Y 171Date: June, 2021 172KernelVersion: v5.14 173Contact: linux-cxl@vger.kernel.org 174Description: 175 (RO) CXL decoder objects are enumerated from either a platform 176 firmware description, or a CXL HDM decoder register set in a 177 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 178 Capability Structure). The 'X' in decoderX.Y represents the 179 cxl_port container of this decoder, and 'Y' represents the 180 instance id of a given decoder resource. 181 182 183What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 184Date: June, 2021 185KernelVersion: v5.14 186Contact: linux-cxl@vger.kernel.org 187Description: 188 (RO) The 'start' and 'size' attributes together convey the 189 physical address base and number of bytes mapped in the 190 decoder's decode window. For decoders of devtype 191 "cxl_decoder_root" the address range is fixed. For decoders of 192 devtype "cxl_decoder_switch" the address is bounded by the 193 decode range of the cxl_port ancestor of the decoder's cxl_port, 194 and dynamically updates based on the active memory regions in 195 that address space. 196 197 198What: /sys/bus/cxl/devices/decoderX.Y/locked 199Date: June, 2021 200KernelVersion: v5.14 201Contact: linux-cxl@vger.kernel.org 202Description: 203 (RO) CXL HDM decoders have the capability to lock the 204 configuration until the next device reset. For decoders of 205 devtype "cxl_decoder_root" there is no standard facility to 206 unlock them. For decoders of devtype "cxl_decoder_switch" a 207 secondary bus reset, of the PCIe bridge that provides the bus 208 for this decoders uport, unlocks / resets the decoder. 209 210 211What: /sys/bus/cxl/devices/decoderX.Y/target_list 212Date: June, 2021 213KernelVersion: v5.14 214Contact: linux-cxl@vger.kernel.org 215Description: 216 (RO) Display a comma separated list of the current decoder 217 target configuration. The list is ordered by the current 218 configured interleave order of the decoder's dport instances. 219 Each entry in the list is a dport id. 220 221 222What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 223Date: June, 2021 224KernelVersion: v5.14 225Contact: linux-cxl@vger.kernel.org 226Description: 227 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 228 represents a fixed memory window identified by platform 229 firmware. A fixed window may only support a subset of memory 230 types. The 'cap_*' attributes indicate whether persistent 231 memory, volatile memory, accelerator memory, and / or expander 232 memory may be mapped behind this decoder's memory window. 233 234 235What: /sys/bus/cxl/devices/decoderX.Y/target_type 236Date: June, 2021 237KernelVersion: v5.14 238Contact: linux-cxl@vger.kernel.org 239Description: 240 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 241 can optionally decode either accelerator memory (type-2) or 242 expander memory (type-3). The 'target_type' attribute indicates 243 the current setting which may dynamically change based on what 244 memory regions are activated in this decode hierarchy. 245 246 247What: /sys/bus/cxl/devices/endpointX/CDAT 248Date: July, 2022 249KernelVersion: v6.0 250Contact: linux-cxl@vger.kernel.org 251Description: 252 (RO) If this sysfs entry is not present no DOE mailbox was 253 found to support CDAT data. If it is present and the length of 254 the data is 0 reading the CDAT data failed. Otherwise the CDAT 255 data is reported. 256 257 258What: /sys/bus/cxl/devices/decoderX.Y/mode 259Date: May, 2022 260KernelVersion: v6.0 261Contact: linux-cxl@vger.kernel.org 262Description: 263 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 264 translates from a host physical address range, to a device local 265 address range. Device-local address ranges are further split 266 into a 'ram' (volatile memory) range and 'pmem' (persistent 267 memory) range. The 'mode' attribute emits one of 'ram', 'pmem', 268 'mixed', or 'none'. The 'mixed' indication is for error cases 269 when a decoder straddles the volatile/persistent partition 270 boundary, and 'none' indicates the decoder is not actively 271 decoding, or no DPA allocation policy has been set. 272 273 'mode' can be written, when the decoder is in the 'disabled' 274 state, with either 'ram' or 'pmem' to set the boundaries for the 275 next allocation. 276 277 278What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 279Date: May, 2022 280KernelVersion: v6.0 281Contact: linux-cxl@vger.kernel.org 282Description: 283 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 284 and its 'dpa_size' attribute is non-zero, this attribute 285 indicates the device physical address (DPA) base address of the 286 allocation. 287 288 289What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 290Date: May, 2022 291KernelVersion: v6.0 292Contact: linux-cxl@vger.kernel.org 293Description: 294 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 295 translates from a host physical address range, to a device local 296 address range. The range, base address plus length in bytes, of 297 DPA allocated to this decoder is conveyed in these 2 attributes. 298 Allocations can be mutated as long as the decoder is in the 299 disabled state. A write to 'dpa_size' releases the previous DPA 300 allocation and then attempts to allocate from the free capacity 301 in the device partition referred to by 'decoderX.Y/mode'. 302 Allocate and free requests can only be performed on the highest 303 instance number disabled decoder with non-zero size. I.e. 304 allocations are enforced to occur in increasing 'decoderX.Y/id' 305 order and frees are enforced to occur in decreasing 306 'decoderX.Y/id' order. 307 308 309What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 310Date: May, 2022 311KernelVersion: v6.0 312Contact: linux-cxl@vger.kernel.org 313Description: 314 (RO) The number of targets across which this decoder's host 315 physical address (HPA) memory range is interleaved. The device 316 maps every Nth block of HPA (of size == 317 'interleave_granularity') to consecutive DPA addresses. The 318 decoder's position in the interleave is determined by the 319 device's (endpoint or switch) switch ancestry. For root 320 decoders their interleave is specified by platform firmware and 321 they only specify a downstream target order for host bridges. 322 323 324What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 325Date: May, 2022 326KernelVersion: v6.0 327Contact: linux-cxl@vger.kernel.org 328Description: 329 (RO) The number of consecutive bytes of host physical address 330 space this decoder claims at address N before the decode rotates 331 to the next target in the interleave at address N + 332 interleave_granularity (assuming N is aligned to 333 interleave_granularity). 334 335 336What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region 337Date: May, 2022, January, 2023 338KernelVersion: v6.0 (pmem), v6.3 (ram) 339Contact: linux-cxl@vger.kernel.org 340Description: 341 (RW) Write a string in the form 'regionZ' to start the process 342 of defining a new persistent, or volatile memory region 343 (interleave-set) within the decode range bounded by root decoder 344 'decoderX.Y'. The value written must match the current value 345 returned from reading this attribute. An atomic compare exchange 346 operation is done on write to assign the requested id to a 347 region and allocate the region-id for the next creation attempt. 348 EBUSY is returned if the region name written does not match the 349 current cached value. 350 351 352What: /sys/bus/cxl/devices/decoderX.Y/delete_region 353Date: May, 2022 354KernelVersion: v6.0 355Contact: linux-cxl@vger.kernel.org 356Description: 357 (WO) Write a string in the form 'regionZ' to delete that region, 358 provided it is currently idle / not bound to a driver. 359 360 361What: /sys/bus/cxl/devices/regionZ/uuid 362Date: May, 2022 363KernelVersion: v6.0 364Contact: linux-cxl@vger.kernel.org 365Description: 366 (RW) Write a unique identifier for the region. This field must 367 be set for persistent regions and it must not conflict with the 368 UUID of another region. For volatile ram regions this 369 attribute is a read-only empty string. 370 371 372What: /sys/bus/cxl/devices/regionZ/interleave_granularity 373Date: May, 2022 374KernelVersion: v6.0 375Contact: linux-cxl@vger.kernel.org 376Description: 377 (RW) Set the number of consecutive bytes each device in the 378 interleave set will claim. The possible interleave granularity 379 values are determined by the CXL spec and the participating 380 devices. 381 382 383What: /sys/bus/cxl/devices/regionZ/interleave_ways 384Date: May, 2022 385KernelVersion: v6.0 386Contact: linux-cxl@vger.kernel.org 387Description: 388 (RW) Configures the number of devices participating in the 389 region is set by writing this value. Each device will provide 390 1/interleave_ways of storage for the region. 391 392 393What: /sys/bus/cxl/devices/regionZ/size 394Date: May, 2022 395KernelVersion: v6.0 396Contact: linux-cxl@vger.kernel.org 397Description: 398 (RW) System physical address space to be consumed by the region. 399 When written trigger the driver to allocate space out of the 400 parent root decoder's address space. When read the size of the 401 address space is reported and should match the span of the 402 region's resource attribute. Size shall be set after the 403 interleave configuration parameters. Once set it cannot be 404 changed, only freed by writing 0. The kernel makes no guarantees 405 that data is maintained over an address space freeing event, and 406 there is no guarantee that a free followed by an allocate 407 results in the same address being allocated. 408 409 410What: /sys/bus/cxl/devices/regionZ/mode 411Date: January, 2023 412KernelVersion: v6.3 413Contact: linux-cxl@vger.kernel.org 414Description: 415 (RO) The mode of a region is established at region creation time 416 and dictates the mode of the endpoint decoder that comprise the 417 region. For more details on the possible modes see 418 /sys/bus/cxl/devices/decoderX.Y/mode 419 420 421What: /sys/bus/cxl/devices/regionZ/resource 422Date: May, 2022 423KernelVersion: v6.0 424Contact: linux-cxl@vger.kernel.org 425Description: 426 (RO) A region is a contiguous partition of a CXL root decoder 427 address space. Region capacity is allocated by writing to the 428 size attribute, the resulting physical address space determined 429 by the driver is reflected here. It is therefore not useful to 430 read this before writing a value to the size attribute. 431 432 433What: /sys/bus/cxl/devices/regionZ/target[0..N] 434Date: May, 2022 435KernelVersion: v6.0 436Contact: linux-cxl@vger.kernel.org 437Description: 438 (RW) Write an endpoint decoder object name to 'targetX' where X 439 is the intended position of the endpoint device in the region 440 interleave and N is the 'interleave_ways' setting for the 441 region. ENXIO is returned if the write results in an impossible 442 to map decode scenario, like the endpoint is unreachable at that 443 position relative to the root decoder interleave. EBUSY is 444 returned if the position in the region is already occupied, or 445 if the region is not in a state to accept interleave 446 configuration changes. EINVAL is returned if the object name is 447 not an endpoint decoder. Once all positions have been 448 successfully written a final validation for decode conflicts is 449 performed before activating the region. 450 451 452What: /sys/bus/cxl/devices/regionZ/commit 453Date: May, 2022 454KernelVersion: v6.0 455Contact: linux-cxl@vger.kernel.org 456Description: 457 (RW) Write a boolean 'true' string value to this attribute to 458 trigger the region to transition from the software programmed 459 state to the actively decoding in hardware state. The commit 460 operation in addition to validating that the region is in proper 461 configured state, validates that the decoders are being 462 committed in spec mandated order (last committed decoder id + 463 1), and checks that the hardware accepts the commit request. 464 Reading this value indicates whether the region is committed or 465 not. 466 467 468What: /sys/bus/cxl/devices/memX/trigger_poison_list 469Date: April, 2023 470KernelVersion: v6.4 471Contact: linux-cxl@vger.kernel.org 472Description: 473 (WO) When a boolean 'true' is written to this attribute the 474 memdev driver retrieves the poison list from the device. The 475 list consists of addresses that are poisoned, or would result 476 in poison if accessed, and the source of the poison. This 477 attribute is only visible for devices supporting the 478 capability. The retrieved errors are logged as kernel 479 events when cxl_poison event tracing is enabled. 480