1What:		/sys/bus/cxl/devices/memX/firmware_version
2Date:		December, 2020
3KernelVersion:	v5.12
4Contact:	linux-cxl@vger.kernel.org
5Description:
6		(RO) "FW Revision" string as reported by the Identify
7		Memory Device Output Payload in the CXL-2.0
8		specification.
9
10What:		/sys/bus/cxl/devices/memX/ram/size
11Date:		December, 2020
12KernelVersion:	v5.12
13Contact:	linux-cxl@vger.kernel.org
14Description:
15		(RO) "Volatile Only Capacity" as bytes. Represents the
16		identically named field in the Identify Memory Device Output
17		Payload in the CXL-2.0 specification.
18
19What:		/sys/bus/cxl/devices/memX/pmem/size
20Date:		December, 2020
21KernelVersion:	v5.12
22Contact:	linux-cxl@vger.kernel.org
23Description:
24		(RO) "Persistent Only Capacity" as bytes. Represents the
25		identically named field in the Identify Memory Device Output
26		Payload in the CXL-2.0 specification.
27
28What:		/sys/bus/cxl/devices/*/devtype
29Date:		June, 2021
30KernelVersion:	v5.14
31Contact:	linux-cxl@vger.kernel.org
32Description:
33		CXL device objects export the devtype attribute which mirrors
34		the same value communicated in the DEVTYPE environment variable
35		for uevents for devices on the "cxl" bus.
36
37What:		/sys/bus/cxl/devices/portX/uport
38Date:		June, 2021
39KernelVersion:	v5.14
40Contact:	linux-cxl@vger.kernel.org
41Description:
42		CXL port objects are enumerated from either a platform firmware
43		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
44		CXL component registers. The 'uport' symlink connects the CXL
45		portX object to the device that published the CXL port
46		capability.
47
48What:		/sys/bus/cxl/devices/portX/dportY
49Date:		June, 2021
50KernelVersion:	v5.14
51Contact:	linux-cxl@vger.kernel.org
52Description:
53		CXL port objects are enumerated from either a platform firmware
54		device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
55		CXL component registers. The 'dportY' symlink identifies one or
56		more downstream ports that the upstream port may target in its
57		decode of CXL memory resources.  The 'Y' integer reflects the
58		hardware port unique-id used in the hardware decoder target
59		list.
60
61What:		/sys/bus/cxl/devices/decoderX.Y
62Date:		June, 2021
63KernelVersion:	v5.14
64Contact:	linux-cxl@vger.kernel.org
65Description:
66		CXL decoder objects are enumerated from either a platform
67		firmware description, or a CXL HDM decoder register set in a
68		PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
69		Capability Structure). The 'X' in decoderX.Y represents the
70		cxl_port container of this decoder, and 'Y' represents the
71		instance id of a given decoder resource.
72
73What:		/sys/bus/cxl/devices/decoderX.Y/{start,size}
74Date:		June, 2021
75KernelVersion:	v5.14
76Contact:	linux-cxl@vger.kernel.org
77Description:
78		The 'start' and 'size' attributes together convey the physical
79		address base and number of bytes mapped in the decoder's decode
80		window. For decoders of devtype "cxl_decoder_root" the address
81		range is fixed. For decoders of devtype "cxl_decoder_switch" the
82		address is bounded by the decode range of the cxl_port ancestor
83		of the decoder's cxl_port, and dynamically updates based on the
84		active memory regions in that address space.
85
86What:		/sys/bus/cxl/devices/decoderX.Y/locked
87Date:		June, 2021
88KernelVersion:	v5.14
89Contact:	linux-cxl@vger.kernel.org
90Description:
91		CXL HDM decoders have the capability to lock the configuration
92		until the next device reset. For decoders of devtype
93		"cxl_decoder_root" there is no standard facility to unlock them.
94		For decoders of devtype "cxl_decoder_switch" a secondary bus
95		reset, of the PCIe bridge that provides the bus for this
96		decoders uport, unlocks / resets the decoder.
97
98What:		/sys/bus/cxl/devices/decoderX.Y/target_list
99Date:		June, 2021
100KernelVersion:	v5.14
101Contact:	linux-cxl@vger.kernel.org
102Description:
103		Display a comma separated list of the current decoder target
104		configuration. The list is ordered by the current configured
105		interleave order of the decoder's dport instances. Each entry in
106		the list is a dport id.
107
108What:		/sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
109Date:		June, 2021
110KernelVersion:	v5.14
111Contact:	linux-cxl@vger.kernel.org
112Description:
113		When a CXL decoder is of devtype "cxl_decoder_root", it
114		represents a fixed memory window identified by platform
115		firmware. A fixed window may only support a subset of memory
116		types. The 'cap_*' attributes indicate whether persistent
117		memory, volatile memory, accelerator memory, and / or expander
118		memory may be mapped behind this decoder's memory window.
119
120What:		/sys/bus/cxl/devices/decoderX.Y/target_type
121Date:		June, 2021
122KernelVersion:	v5.14
123Contact:	linux-cxl@vger.kernel.org
124Description:
125		When a CXL decoder is of devtype "cxl_decoder_switch", it can
126		optionally decode either accelerator memory (type-2) or expander
127		memory (type-3). The 'target_type' attribute indicates the
128		current setting which may dynamically change based on what
129		memory regions are activated in this decode hierarchy.
130