1What: /sys/bus/cxl/flush 2Date: Januarry, 2022 3KernelVersion: v5.18 4Contact: linux-cxl@vger.kernel.org 5Description: 6 (WO) If userspace manually unbinds a port the kernel schedules 7 all descendant memdevs for unbind. Writing '1' to this attribute 8 flushes that work. 9 10 11What: /sys/bus/cxl/devices/memX/firmware_version 12Date: December, 2020 13KernelVersion: v5.12 14Contact: linux-cxl@vger.kernel.org 15Description: 16 (RO) "FW Revision" string as reported by the Identify 17 Memory Device Output Payload in the CXL-2.0 18 specification. 19 20 21What: /sys/bus/cxl/devices/memX/ram/size 22Date: December, 2020 23KernelVersion: v5.12 24Contact: linux-cxl@vger.kernel.org 25Description: 26 (RO) "Volatile Only Capacity" as bytes. Represents the 27 identically named field in the Identify Memory Device Output 28 Payload in the CXL-2.0 specification. 29 30 31What: /sys/bus/cxl/devices/memX/pmem/size 32Date: December, 2020 33KernelVersion: v5.12 34Contact: linux-cxl@vger.kernel.org 35Description: 36 (RO) "Persistent Only Capacity" as bytes. Represents the 37 identically named field in the Identify Memory Device Output 38 Payload in the CXL-2.0 specification. 39 40 41What: /sys/bus/cxl/devices/memX/serial 42Date: January, 2022 43KernelVersion: v5.18 44Contact: linux-cxl@vger.kernel.org 45Description: 46 (RO) 64-bit serial number per the PCIe Device Serial Number 47 capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2 48 Memory Device PCIe Capabilities and Extended Capabilities. 49 50 51What: /sys/bus/cxl/devices/memX/numa_node 52Date: January, 2022 53KernelVersion: v5.18 54Contact: linux-cxl@vger.kernel.org 55Description: 56 (RO) If NUMA is enabled and the platform has affinitized the 57 host PCI device for this memory device, emit the CPU node 58 affinity for this device. 59 60 61What: /sys/bus/cxl/devices/memX/security/state 62Date: June, 2023 63KernelVersion: v6.5 64Contact: linux-cxl@vger.kernel.org 65Description: 66 (RO) Reading this file will display the CXL security state for 67 that device. Such states can be: 'disabled', 'sanitize', when 68 a sanitization is currently underway; or those available only 69 for persistent memory: 'locked', 'unlocked' or 'frozen'. This 70 sysfs entry is select/poll capable from userspace to notify 71 upon completion of a sanitize operation. 72 73 74What: /sys/bus/cxl/devices/memX/security/sanitize 75Date: June, 2023 76KernelVersion: v6.5 77Contact: linux-cxl@vger.kernel.org 78Description: 79 (WO) Write a boolean 'true' string value to this attribute to 80 sanitize the device to securely re-purpose or decommission it. 81 This is done by ensuring that all user data and meta-data, 82 whether it resides in persistent capacity, volatile capacity, 83 or the LSA, is made permanently unavailable by whatever means 84 is appropriate for the media type. This functionality requires 85 the device to be not be actively decoding any HPA ranges. 86 87 88What: /sys/bus/cxl/devices/*/devtype 89Date: June, 2021 90KernelVersion: v5.14 91Contact: linux-cxl@vger.kernel.org 92Description: 93 (RO) CXL device objects export the devtype attribute which 94 mirrors the same value communicated in the DEVTYPE environment 95 variable for uevents for devices on the "cxl" bus. 96 97 98What: /sys/bus/cxl/devices/*/modalias 99Date: December, 2021 100KernelVersion: v5.18 101Contact: linux-cxl@vger.kernel.org 102Description: 103 (RO) CXL device objects export the modalias attribute which 104 mirrors the same value communicated in the MODALIAS environment 105 variable for uevents for devices on the "cxl" bus. 106 107 108What: /sys/bus/cxl/devices/portX/uport 109Date: June, 2021 110KernelVersion: v5.14 111Contact: linux-cxl@vger.kernel.org 112Description: 113 (RO) CXL port objects are enumerated from either a platform 114 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 115 port with CXL component registers. The 'uport' symlink connects 116 the CXL portX object to the device that published the CXL port 117 capability. 118 119 120What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport 121Date: January, 2023 122KernelVersion: v6.3 123Contact: linux-cxl@vger.kernel.org 124Description: 125 (RO) CXL port objects are instantiated for each upstream port in 126 a CXL/PCIe switch, and for each endpoint to map the 127 corresponding memory device into the CXL port hierarchy. When a 128 descendant CXL port (switch or endpoint) is enumerated it is 129 useful to know which 'dport' object in the parent CXL port 130 routes to this descendant. The 'parent_dport' symlink points to 131 the device representing the downstream port of a CXL switch that 132 routes to {port,endpoint}X. 133 134 135What: /sys/bus/cxl/devices/portX/dportY 136Date: June, 2021 137KernelVersion: v5.14 138Contact: linux-cxl@vger.kernel.org 139Description: 140 (RO) CXL port objects are enumerated from either a platform 141 firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream 142 port with CXL component registers. The 'dportY' symlink 143 identifies one or more downstream ports that the upstream port 144 may target in its decode of CXL memory resources. The 'Y' 145 integer reflects the hardware port unique-id used in the 146 hardware decoder target list. 147 148 149What: /sys/bus/cxl/devices/decoderX.Y 150Date: June, 2021 151KernelVersion: v5.14 152Contact: linux-cxl@vger.kernel.org 153Description: 154 (RO) CXL decoder objects are enumerated from either a platform 155 firmware description, or a CXL HDM decoder register set in a 156 PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 157 Capability Structure). The 'X' in decoderX.Y represents the 158 cxl_port container of this decoder, and 'Y' represents the 159 instance id of a given decoder resource. 160 161 162What: /sys/bus/cxl/devices/decoderX.Y/{start,size} 163Date: June, 2021 164KernelVersion: v5.14 165Contact: linux-cxl@vger.kernel.org 166Description: 167 (RO) The 'start' and 'size' attributes together convey the 168 physical address base and number of bytes mapped in the 169 decoder's decode window. For decoders of devtype 170 "cxl_decoder_root" the address range is fixed. For decoders of 171 devtype "cxl_decoder_switch" the address is bounded by the 172 decode range of the cxl_port ancestor of the decoder's cxl_port, 173 and dynamically updates based on the active memory regions in 174 that address space. 175 176 177What: /sys/bus/cxl/devices/decoderX.Y/locked 178Date: June, 2021 179KernelVersion: v5.14 180Contact: linux-cxl@vger.kernel.org 181Description: 182 (RO) CXL HDM decoders have the capability to lock the 183 configuration until the next device reset. For decoders of 184 devtype "cxl_decoder_root" there is no standard facility to 185 unlock them. For decoders of devtype "cxl_decoder_switch" a 186 secondary bus reset, of the PCIe bridge that provides the bus 187 for this decoders uport, unlocks / resets the decoder. 188 189 190What: /sys/bus/cxl/devices/decoderX.Y/target_list 191Date: June, 2021 192KernelVersion: v5.14 193Contact: linux-cxl@vger.kernel.org 194Description: 195 (RO) Display a comma separated list of the current decoder 196 target configuration. The list is ordered by the current 197 configured interleave order of the decoder's dport instances. 198 Each entry in the list is a dport id. 199 200 201What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 202Date: June, 2021 203KernelVersion: v5.14 204Contact: linux-cxl@vger.kernel.org 205Description: 206 (RO) When a CXL decoder is of devtype "cxl_decoder_root", it 207 represents a fixed memory window identified by platform 208 firmware. A fixed window may only support a subset of memory 209 types. The 'cap_*' attributes indicate whether persistent 210 memory, volatile memory, accelerator memory, and / or expander 211 memory may be mapped behind this decoder's memory window. 212 213 214What: /sys/bus/cxl/devices/decoderX.Y/target_type 215Date: June, 2021 216KernelVersion: v5.14 217Contact: linux-cxl@vger.kernel.org 218Description: 219 (RO) When a CXL decoder is of devtype "cxl_decoder_switch", it 220 can optionally decode either accelerator memory (type-2) or 221 expander memory (type-3). The 'target_type' attribute indicates 222 the current setting which may dynamically change based on what 223 memory regions are activated in this decode hierarchy. 224 225 226What: /sys/bus/cxl/devices/endpointX/CDAT 227Date: July, 2022 228KernelVersion: v6.0 229Contact: linux-cxl@vger.kernel.org 230Description: 231 (RO) If this sysfs entry is not present no DOE mailbox was 232 found to support CDAT data. If it is present and the length of 233 the data is 0 reading the CDAT data failed. Otherwise the CDAT 234 data is reported. 235 236 237What: /sys/bus/cxl/devices/decoderX.Y/mode 238Date: May, 2022 239KernelVersion: v6.0 240Contact: linux-cxl@vger.kernel.org 241Description: 242 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 243 translates from a host physical address range, to a device local 244 address range. Device-local address ranges are further split 245 into a 'ram' (volatile memory) range and 'pmem' (persistent 246 memory) range. The 'mode' attribute emits one of 'ram', 'pmem', 247 'mixed', or 'none'. The 'mixed' indication is for error cases 248 when a decoder straddles the volatile/persistent partition 249 boundary, and 'none' indicates the decoder is not actively 250 decoding, or no DPA allocation policy has been set. 251 252 'mode' can be written, when the decoder is in the 'disabled' 253 state, with either 'ram' or 'pmem' to set the boundaries for the 254 next allocation. 255 256 257What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource 258Date: May, 2022 259KernelVersion: v6.0 260Contact: linux-cxl@vger.kernel.org 261Description: 262 (RO) When a CXL decoder is of devtype "cxl_decoder_endpoint", 263 and its 'dpa_size' attribute is non-zero, this attribute 264 indicates the device physical address (DPA) base address of the 265 allocation. 266 267 268What: /sys/bus/cxl/devices/decoderX.Y/dpa_size 269Date: May, 2022 270KernelVersion: v6.0 271Contact: linux-cxl@vger.kernel.org 272Description: 273 (RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it 274 translates from a host physical address range, to a device local 275 address range. The range, base address plus length in bytes, of 276 DPA allocated to this decoder is conveyed in these 2 attributes. 277 Allocations can be mutated as long as the decoder is in the 278 disabled state. A write to 'dpa_size' releases the previous DPA 279 allocation and then attempts to allocate from the free capacity 280 in the device partition referred to by 'decoderX.Y/mode'. 281 Allocate and free requests can only be performed on the highest 282 instance number disabled decoder with non-zero size. I.e. 283 allocations are enforced to occur in increasing 'decoderX.Y/id' 284 order and frees are enforced to occur in decreasing 285 'decoderX.Y/id' order. 286 287 288What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways 289Date: May, 2022 290KernelVersion: v6.0 291Contact: linux-cxl@vger.kernel.org 292Description: 293 (RO) The number of targets across which this decoder's host 294 physical address (HPA) memory range is interleaved. The device 295 maps every Nth block of HPA (of size == 296 'interleave_granularity') to consecutive DPA addresses. The 297 decoder's position in the interleave is determined by the 298 device's (endpoint or switch) switch ancestry. For root 299 decoders their interleave is specified by platform firmware and 300 they only specify a downstream target order for host bridges. 301 302 303What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity 304Date: May, 2022 305KernelVersion: v6.0 306Contact: linux-cxl@vger.kernel.org 307Description: 308 (RO) The number of consecutive bytes of host physical address 309 space this decoder claims at address N before the decode rotates 310 to the next target in the interleave at address N + 311 interleave_granularity (assuming N is aligned to 312 interleave_granularity). 313 314 315What: /sys/bus/cxl/devices/decoderX.Y/create_{pmem,ram}_region 316Date: May, 2022, January, 2023 317KernelVersion: v6.0 (pmem), v6.3 (ram) 318Contact: linux-cxl@vger.kernel.org 319Description: 320 (RW) Write a string in the form 'regionZ' to start the process 321 of defining a new persistent, or volatile memory region 322 (interleave-set) within the decode range bounded by root decoder 323 'decoderX.Y'. The value written must match the current value 324 returned from reading this attribute. An atomic compare exchange 325 operation is done on write to assign the requested id to a 326 region and allocate the region-id for the next creation attempt. 327 EBUSY is returned if the region name written does not match the 328 current cached value. 329 330 331What: /sys/bus/cxl/devices/decoderX.Y/delete_region 332Date: May, 2022 333KernelVersion: v6.0 334Contact: linux-cxl@vger.kernel.org 335Description: 336 (WO) Write a string in the form 'regionZ' to delete that region, 337 provided it is currently idle / not bound to a driver. 338 339 340What: /sys/bus/cxl/devices/regionZ/uuid 341Date: May, 2022 342KernelVersion: v6.0 343Contact: linux-cxl@vger.kernel.org 344Description: 345 (RW) Write a unique identifier for the region. This field must 346 be set for persistent regions and it must not conflict with the 347 UUID of another region. For volatile ram regions this 348 attribute is a read-only empty string. 349 350 351What: /sys/bus/cxl/devices/regionZ/interleave_granularity 352Date: May, 2022 353KernelVersion: v6.0 354Contact: linux-cxl@vger.kernel.org 355Description: 356 (RW) Set the number of consecutive bytes each device in the 357 interleave set will claim. The possible interleave granularity 358 values are determined by the CXL spec and the participating 359 devices. 360 361 362What: /sys/bus/cxl/devices/regionZ/interleave_ways 363Date: May, 2022 364KernelVersion: v6.0 365Contact: linux-cxl@vger.kernel.org 366Description: 367 (RW) Configures the number of devices participating in the 368 region is set by writing this value. Each device will provide 369 1/interleave_ways of storage for the region. 370 371 372What: /sys/bus/cxl/devices/regionZ/size 373Date: May, 2022 374KernelVersion: v6.0 375Contact: linux-cxl@vger.kernel.org 376Description: 377 (RW) System physical address space to be consumed by the region. 378 When written trigger the driver to allocate space out of the 379 parent root decoder's address space. When read the size of the 380 address space is reported and should match the span of the 381 region's resource attribute. Size shall be set after the 382 interleave configuration parameters. Once set it cannot be 383 changed, only freed by writing 0. The kernel makes no guarantees 384 that data is maintained over an address space freeing event, and 385 there is no guarantee that a free followed by an allocate 386 results in the same address being allocated. 387 388 389What: /sys/bus/cxl/devices/regionZ/mode 390Date: January, 2023 391KernelVersion: v6.3 392Contact: linux-cxl@vger.kernel.org 393Description: 394 (RO) The mode of a region is established at region creation time 395 and dictates the mode of the endpoint decoder that comprise the 396 region. For more details on the possible modes see 397 /sys/bus/cxl/devices/decoderX.Y/mode 398 399 400What: /sys/bus/cxl/devices/regionZ/resource 401Date: May, 2022 402KernelVersion: v6.0 403Contact: linux-cxl@vger.kernel.org 404Description: 405 (RO) A region is a contiguous partition of a CXL root decoder 406 address space. Region capacity is allocated by writing to the 407 size attribute, the resulting physical address space determined 408 by the driver is reflected here. It is therefore not useful to 409 read this before writing a value to the size attribute. 410 411 412What: /sys/bus/cxl/devices/regionZ/target[0..N] 413Date: May, 2022 414KernelVersion: v6.0 415Contact: linux-cxl@vger.kernel.org 416Description: 417 (RW) Write an endpoint decoder object name to 'targetX' where X 418 is the intended position of the endpoint device in the region 419 interleave and N is the 'interleave_ways' setting for the 420 region. ENXIO is returned if the write results in an impossible 421 to map decode scenario, like the endpoint is unreachable at that 422 position relative to the root decoder interleave. EBUSY is 423 returned if the position in the region is already occupied, or 424 if the region is not in a state to accept interleave 425 configuration changes. EINVAL is returned if the object name is 426 not an endpoint decoder. Once all positions have been 427 successfully written a final validation for decode conflicts is 428 performed before activating the region. 429 430 431What: /sys/bus/cxl/devices/regionZ/commit 432Date: May, 2022 433KernelVersion: v6.0 434Contact: linux-cxl@vger.kernel.org 435Description: 436 (RW) Write a boolean 'true' string value to this attribute to 437 trigger the region to transition from the software programmed 438 state to the actively decoding in hardware state. The commit 439 operation in addition to validating that the region is in proper 440 configured state, validates that the decoders are being 441 committed in spec mandated order (last committed decoder id + 442 1), and checks that the hardware accepts the commit request. 443 Reading this value indicates whether the region is committed or 444 not. 445 446 447What: /sys/bus/cxl/devices/memX/trigger_poison_list 448Date: April, 2023 449KernelVersion: v6.4 450Contact: linux-cxl@vger.kernel.org 451Description: 452 (WO) When a boolean 'true' is written to this attribute the 453 memdev driver retrieves the poison list from the device. The 454 list consists of addresses that are poisoned, or would result 455 in poison if accessed, and the source of the poison. This 456 attribute is only visible for devices supporting the 457 capability. The retrieved errors are logged as kernel 458 events when cxl_poison event tracing is enabled. 459