1b39cb105SDan WilliamsWhat: /sys/bus/cxl/devices/memX/firmware_version 2b39cb105SDan WilliamsDate: December, 2020 3b39cb105SDan WilliamsKernelVersion: v5.12 4b39cb105SDan WilliamsContact: linux-cxl@vger.kernel.org 5b39cb105SDan WilliamsDescription: 6b39cb105SDan Williams (RO) "FW Revision" string as reported by the Identify 7b39cb105SDan Williams Memory Device Output Payload in the CXL-2.0 8b39cb105SDan Williams specification. 9b39cb105SDan Williams 10b39cb105SDan WilliamsWhat: /sys/bus/cxl/devices/memX/ram/size 11b39cb105SDan WilliamsDate: December, 2020 12b39cb105SDan WilliamsKernelVersion: v5.12 13b39cb105SDan WilliamsContact: linux-cxl@vger.kernel.org 14b39cb105SDan WilliamsDescription: 15b39cb105SDan Williams (RO) "Volatile Only Capacity" as bytes. Represents the 16b39cb105SDan Williams identically named field in the Identify Memory Device Output 17b39cb105SDan Williams Payload in the CXL-2.0 specification. 18b39cb105SDan Williams 19b39cb105SDan WilliamsWhat: /sys/bus/cxl/devices/memX/pmem/size 20b39cb105SDan WilliamsDate: December, 2020 21b39cb105SDan WilliamsKernelVersion: v5.12 22b39cb105SDan WilliamsContact: linux-cxl@vger.kernel.org 23b39cb105SDan WilliamsDescription: 24b39cb105SDan Williams (RO) "Persistent Only Capacity" as bytes. Represents the 25b39cb105SDan Williams identically named field in the Identify Memory Device Output 26b39cb105SDan Williams Payload in the CXL-2.0 specification. 274812be97SDan Williams 284812be97SDan WilliamsWhat: /sys/bus/cxl/devices/*/devtype 294812be97SDan WilliamsDate: June, 2021 304812be97SDan WilliamsKernelVersion: v5.14 314812be97SDan WilliamsContact: linux-cxl@vger.kernel.org 324812be97SDan WilliamsDescription: 334812be97SDan Williams CXL device objects export the devtype attribute which mirrors 344812be97SDan Williams the same value communicated in the DEVTYPE environment variable 354812be97SDan Williams for uevents for devices on the "cxl" bus. 364812be97SDan Williams 374812be97SDan WilliamsWhat: /sys/bus/cxl/devices/portX/uport 384812be97SDan WilliamsDate: June, 2021 394812be97SDan WilliamsKernelVersion: v5.14 404812be97SDan WilliamsContact: linux-cxl@vger.kernel.org 414812be97SDan WilliamsDescription: 424812be97SDan Williams CXL port objects are enumerated from either a platform firmware 434812be97SDan Williams device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 444812be97SDan Williams CXL component registers. The 'uport' symlink connects the CXL 454812be97SDan Williams portX object to the device that published the CXL port 464812be97SDan Williams capability. 477d4b5ca2SDan Williams 487d4b5ca2SDan WilliamsWhat: /sys/bus/cxl/devices/portX/dportY 497d4b5ca2SDan WilliamsDate: June, 2021 507d4b5ca2SDan WilliamsKernelVersion: v5.14 517d4b5ca2SDan WilliamsContact: linux-cxl@vger.kernel.org 527d4b5ca2SDan WilliamsDescription: 537d4b5ca2SDan Williams CXL port objects are enumerated from either a platform firmware 547d4b5ca2SDan Williams device (ACPI0017 and ACPI0016) or PCIe switch upstream port with 557d4b5ca2SDan Williams CXL component registers. The 'dportY' symlink identifies one or 567d4b5ca2SDan Williams more downstream ports that the upstream port may target in its 577d4b5ca2SDan Williams decode of CXL memory resources. The 'Y' integer reflects the 587d4b5ca2SDan Williams hardware port unique-id used in the hardware decoder target 597d4b5ca2SDan Williams list. 60*40ba17afSDan Williams 61*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y 62*40ba17afSDan WilliamsDate: June, 2021 63*40ba17afSDan WilliamsKernelVersion: v5.14 64*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 65*40ba17afSDan WilliamsDescription: 66*40ba17afSDan Williams CXL decoder objects are enumerated from either a platform 67*40ba17afSDan Williams firmware description, or a CXL HDM decoder register set in a 68*40ba17afSDan Williams PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder 69*40ba17afSDan Williams Capability Structure). The 'X' in decoderX.Y represents the 70*40ba17afSDan Williams cxl_port container of this decoder, and 'Y' represents the 71*40ba17afSDan Williams instance id of a given decoder resource. 72*40ba17afSDan Williams 73*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y/{start,size} 74*40ba17afSDan WilliamsDate: June, 2021 75*40ba17afSDan WilliamsKernelVersion: v5.14 76*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 77*40ba17afSDan WilliamsDescription: 78*40ba17afSDan Williams The 'start' and 'size' attributes together convey the physical 79*40ba17afSDan Williams address base and number of bytes mapped in the decoder's decode 80*40ba17afSDan Williams window. For decoders of devtype "cxl_decoder_root" the address 81*40ba17afSDan Williams range is fixed. For decoders of devtype "cxl_decoder_switch" the 82*40ba17afSDan Williams address is bounded by the decode range of the cxl_port ancestor 83*40ba17afSDan Williams of the decoder's cxl_port, and dynamically updates based on the 84*40ba17afSDan Williams active memory regions in that address space. 85*40ba17afSDan Williams 86*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y/locked 87*40ba17afSDan WilliamsDate: June, 2021 88*40ba17afSDan WilliamsKernelVersion: v5.14 89*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 90*40ba17afSDan WilliamsDescription: 91*40ba17afSDan Williams CXL HDM decoders have the capability to lock the configuration 92*40ba17afSDan Williams until the next device reset. For decoders of devtype 93*40ba17afSDan Williams "cxl_decoder_root" there is no standard facility to unlock them. 94*40ba17afSDan Williams For decoders of devtype "cxl_decoder_switch" a secondary bus 95*40ba17afSDan Williams reset, of the PCIe bridge that provides the bus for this 96*40ba17afSDan Williams decoders uport, unlocks / resets the decoder. 97*40ba17afSDan Williams 98*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y/target_list 99*40ba17afSDan WilliamsDate: June, 2021 100*40ba17afSDan WilliamsKernelVersion: v5.14 101*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 102*40ba17afSDan WilliamsDescription: 103*40ba17afSDan Williams Display a comma separated list of the current decoder target 104*40ba17afSDan Williams configuration. The list is ordered by the current configured 105*40ba17afSDan Williams interleave order of the decoder's dport instances. Each entry in 106*40ba17afSDan Williams the list is a dport id. 107*40ba17afSDan Williams 108*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3} 109*40ba17afSDan WilliamsDate: June, 2021 110*40ba17afSDan WilliamsKernelVersion: v5.14 111*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 112*40ba17afSDan WilliamsDescription: 113*40ba17afSDan Williams When a CXL decoder is of devtype "cxl_decoder_root", it 114*40ba17afSDan Williams represents a fixed memory window identified by platform 115*40ba17afSDan Williams firmware. A fixed window may only support a subset of memory 116*40ba17afSDan Williams types. The 'cap_*' attributes indicate whether persistent 117*40ba17afSDan Williams memory, volatile memory, accelerator memory, and / or expander 118*40ba17afSDan Williams memory may be mapped behind this decoder's memory window. 119*40ba17afSDan Williams 120*40ba17afSDan WilliamsWhat: /sys/bus/cxl/devices/decoderX.Y/target_type 121*40ba17afSDan WilliamsDate: June, 2021 122*40ba17afSDan WilliamsKernelVersion: v5.14 123*40ba17afSDan WilliamsContact: linux-cxl@vger.kernel.org 124*40ba17afSDan WilliamsDescription: 125*40ba17afSDan Williams When a CXL decoder is of devtype "cxl_decoder_switch", it can 126*40ba17afSDan Williams optionally decode either accelerator memory (type-2) or expander 127*40ba17afSDan Williams memory (type-3). The 'target_type' attribute indicates the 128*40ba17afSDan Williams current setting which may dynamically change based on what 129*40ba17afSDan Williams memory regions are activated in this decode hierarchy. 130