1 /** 2 * Describes available sections to the CPER parser. 3 * 4 * Author: Lawrence.Tang@arm.com 5 **/ 6 #include "../edk/Cper.h" 7 #include "cper-section.h" 8 #include "cper-section-arm.h" 9 #include "cper-section-generic.h" 10 #include "cper-section-ia32x64.h" 11 #include "cper-section-ipf.h" 12 #include "cper-section-memory.h" 13 #include "cper-section-pcie.h" 14 #include "cper-section-firmware.h" 15 #include "cper-section-pci-bus.h" 16 #include "cper-section-pci-dev.h" 17 #include "cper-section-dmar-generic.h" 18 #include "cper-section-dmar-vtd.h" 19 #include "cper-section-dmar-iommu.h" 20 #include "cper-section-ccix-per.h" 21 #include "cper-section-cxl-protocol.h" 22 #include "cper-section-cxl-component.h" 23 #include "cper-section-nvidia.h" 24 #include "cper-section-ampere.h" 25 26 //Definitions of all sections available to the CPER parser. 27 CPER_SECTION_DEFINITION section_definitions[] = { 28 { &gEfiProcessorGenericErrorSectionGuid, "Processor Generic", 29 cper_section_generic_to_ir, ir_section_generic_to_cper }, 30 { &gEfiIa32X64ProcessorErrorSectionGuid, "IA32/X64", 31 cper_section_ia32x64_to_ir, ir_section_ia32x64_to_cper }, 32 { &gEfiIpfProcessorErrorSectionGuid, "IPF", NULL, NULL }, 33 { &gEfiArmProcessorErrorSectionGuid, "ARM", cper_section_arm_to_ir, 34 ir_section_arm_to_cper }, 35 { &gEfiPlatformMemoryErrorSectionGuid, "Platform Memory", 36 cper_section_platform_memory_to_ir, ir_section_memory_to_cper }, 37 { &gEfiPlatformMemoryError2SectionGuid, "Platform Memory 2", 38 cper_section_platform_memory2_to_ir, ir_section_memory2_to_cper }, 39 { &gEfiPcieErrorSectionGuid, "PCIe", cper_section_pcie_to_ir, 40 ir_section_pcie_to_cper }, 41 { &gEfiFirmwareErrorSectionGuid, "Firmware Error Record Reference", 42 cper_section_firmware_to_ir, ir_section_firmware_to_cper }, 43 { &gEfiPciBusErrorSectionGuid, "PCI/PCI-X Bus", 44 cper_section_pci_bus_to_ir, ir_section_pci_bus_to_cper }, 45 { &gEfiPciDevErrorSectionGuid, "PCI Component/Device", 46 cper_section_pci_dev_to_ir, ir_section_pci_dev_to_cper }, 47 { &gEfiDMArGenericErrorSectionGuid, "DMAr Generic", 48 cper_section_dmar_generic_to_ir, ir_section_dmar_generic_to_cper }, 49 { &gEfiDirectedIoDMArErrorSectionGuid, 50 "Intel VT for Directed I/O Specific DMAr", 51 cper_section_dmar_vtd_to_ir, ir_section_dmar_vtd_to_cper }, 52 { &gEfiIommuDMArErrorSectionGuid, "IOMMU Specific DMAr", 53 cper_section_dmar_iommu_to_ir, ir_section_dmar_iommu_to_cper }, 54 { &gEfiCcixPerLogErrorSectionGuid, "CCIX PER Log Error", 55 cper_section_ccix_per_to_ir, ir_section_ccix_per_to_cper }, 56 { &gEfiCxlProtocolErrorSectionGuid, "CXL Protocol Error", 57 cper_section_cxl_protocol_to_ir, ir_section_cxl_protocol_to_cper }, 58 { &gEfiCxlGeneralMediaErrorSectionGuid, 59 "CXL General Media Component Error", cper_section_cxl_component_to_ir, 60 ir_section_cxl_component_to_cper }, 61 { &gEfiCxlDramEventErrorSectionGuid, "CXL DRAM Component Error", 62 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 63 { &gEfiCxlMemoryModuleErrorSectionGuid, 64 "CXL Memory Module Component Error", cper_section_cxl_component_to_ir, 65 ir_section_cxl_component_to_cper }, 66 { &gEfiCxlPhysicalSwitchErrorSectionGuid, 67 "CXL Physical Switch Component Error", 68 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 69 { &gEfiCxlVirtualSwitchErrorSectionGuid, 70 "CXL Virtual Switch Component Error", 71 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 72 { &gEfiCxlMldPortErrorSectionGuid, "CXL MLD Port Component Error", 73 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 74 { &gEfiNvidiaErrorSectionGuid, "NVIDIA", cper_section_nvidia_to_ir, 75 ir_section_nvidia_to_cper }, 76 { &gEfiAmpereErrorSectionGuid, "Ampere", cper_section_ampere_to_ir, 77 ir_section_ampere_to_cper }, 78 }; 79 const size_t section_definitions_len = 80 sizeof(section_definitions) / sizeof(CPER_SECTION_DEFINITION); 81