1 /** 2 * Describes available sections to the CPER parser. 3 * 4 * Author: Lawrence.Tang@arm.com 5 **/ 6 #include "../edk/Cper.h" 7 #include "cper-section.h" 8 #include "cper-section-arm.h" 9 #include "cper-section-generic.h" 10 #include "cper-section-ia32x64.h" 11 #include "cper-section-ipf.h" 12 #include "cper-section-memory.h" 13 #include "cper-section-pcie.h" 14 #include "cper-section-firmware.h" 15 #include "cper-section-pci-bus.h" 16 #include "cper-section-pci-dev.h" 17 #include "cper-section-dmar-generic.h" 18 #include "cper-section-dmar-vtd.h" 19 #include "cper-section-dmar-iommu.h" 20 #include "cper-section-ccix-per.h" 21 #include "cper-section-cxl-protocol.h" 22 #include "cper-section-cxl-component.h" 23 #include "cper-section-nvidia.h" 24 25 //Definitions of all sections available to the CPER parser. 26 CPER_SECTION_DEFINITION section_definitions[] = { 27 { &gEfiProcessorGenericErrorSectionGuid, "Processor Generic", 28 cper_section_generic_to_ir, ir_section_generic_to_cper }, 29 { &gEfiIa32X64ProcessorErrorSectionGuid, "IA32/X64", 30 cper_section_ia32x64_to_ir, ir_section_ia32x64_to_cper }, 31 { &gEfiIpfProcessorErrorSectionGuid, "IPF", NULL, NULL }, 32 { &gEfiArmProcessorErrorSectionGuid, "ARM", cper_section_arm_to_ir, 33 ir_section_arm_to_cper }, 34 { &gEfiPlatformMemoryErrorSectionGuid, "Platform Memory", 35 cper_section_platform_memory_to_ir, ir_section_memory_to_cper }, 36 { &gEfiPlatformMemoryError2SectionGuid, "Platform Memory 2", 37 cper_section_platform_memory2_to_ir, ir_section_memory2_to_cper }, 38 { &gEfiPcieErrorSectionGuid, "PCIe", cper_section_pcie_to_ir, 39 ir_section_pcie_to_cper }, 40 { &gEfiFirmwareErrorSectionGuid, "Firmware Error Record Reference", 41 cper_section_firmware_to_ir, ir_section_firmware_to_cper }, 42 { &gEfiPciBusErrorSectionGuid, "PCI/PCI-X Bus", 43 cper_section_pci_bus_to_ir, ir_section_pci_bus_to_cper }, 44 { &gEfiPciDevErrorSectionGuid, "PCI Component/Device", 45 cper_section_pci_dev_to_ir, ir_section_pci_dev_to_cper }, 46 { &gEfiDMArGenericErrorSectionGuid, "DMAr Generic", 47 cper_section_dmar_generic_to_ir, ir_section_dmar_generic_to_cper }, 48 { &gEfiDirectedIoDMArErrorSectionGuid, 49 "Intel VT for Directed I/O Specific DMAr", 50 cper_section_dmar_vtd_to_ir, ir_section_dmar_vtd_to_cper }, 51 { &gEfiIommuDMArErrorSectionGuid, "IOMMU Specific DMAr", 52 cper_section_dmar_iommu_to_ir, ir_section_dmar_iommu_to_cper }, 53 { &gEfiCcixPerLogErrorSectionGuid, "CCIX PER Log Error", 54 cper_section_ccix_per_to_ir, ir_section_ccix_per_to_cper }, 55 { &gEfiCxlProtocolErrorSectionGuid, "CXL Protocol Error", 56 cper_section_cxl_protocol_to_ir, ir_section_cxl_protocol_to_cper }, 57 { &gEfiCxlGeneralMediaErrorSectionGuid, 58 "CXL General Media Component Error", cper_section_cxl_component_to_ir, 59 ir_section_cxl_component_to_cper }, 60 { &gEfiCxlDramEventErrorSectionGuid, "CXL DRAM Component Error", 61 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 62 { &gEfiCxlMemoryModuleErrorSectionGuid, 63 "CXL Memory Module Component Error", cper_section_cxl_component_to_ir, 64 ir_section_cxl_component_to_cper }, 65 { &gEfiCxlPhysicalSwitchErrorSectionGuid, 66 "CXL Physical Switch Component Error", 67 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 68 { &gEfiCxlVirtualSwitchErrorSectionGuid, 69 "CXL Virtual Switch Component Error", 70 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 71 { &gEfiCxlMldPortErrorSectionGuid, "CXL MLD Port Component Error", 72 cper_section_cxl_component_to_ir, ir_section_cxl_component_to_cper }, 73 { &gEfiNvidiaErrorSectionGuid, "NVIDIA", cper_section_nvidia_to_ir, 74 ir_section_nvidia_to_cper }, 75 }; 76 const size_t section_definitions_len = 77 sizeof(section_definitions) / sizeof(CPER_SECTION_DEFINITION); 78