1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <sdhci.h> 15 16 void *aligned_buffer; 17 18 static void sdhci_reset(struct sdhci_host *host, u8 mask) 19 { 20 unsigned long timeout; 21 22 /* Wait max 100 ms */ 23 timeout = 100; 24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 26 if (timeout == 0) { 27 printf("Reset 0x%x never completed.\n", (int)mask); 28 return; 29 } 30 timeout--; 31 udelay(1000); 32 } 33 } 34 35 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 36 { 37 int i; 38 if (cmd->resp_type & MMC_RSP_136) { 39 /* CRC is stripped so we need to do some shifting. */ 40 for (i = 0; i < 4; i++) { 41 cmd->response[i] = sdhci_readl(host, 42 SDHCI_RESPONSE + (3-i)*4) << 8; 43 if (i != 3) 44 cmd->response[i] |= sdhci_readb(host, 45 SDHCI_RESPONSE + (3-i)*4-1); 46 } 47 } else { 48 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 49 } 50 } 51 52 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 53 { 54 int i; 55 char *offs; 56 for (i = 0; i < data->blocksize; i += 4) { 57 offs = data->dest + i; 58 if (data->flags == MMC_DATA_READ) 59 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 60 else 61 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 62 } 63 } 64 65 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 66 unsigned int start_addr) 67 { 68 unsigned int stat, rdy, mask, timeout, block = 0; 69 #ifdef CONFIG_MMC_SDMA 70 unsigned char ctrl; 71 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 72 ctrl &= ~SDHCI_CTRL_DMA_MASK; 73 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 74 #endif 75 76 timeout = 1000000; 77 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 78 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 79 do { 80 stat = sdhci_readl(host, SDHCI_INT_STATUS); 81 if (stat & SDHCI_INT_ERROR) { 82 printf("Error detected in status(0x%X)!\n", stat); 83 return -1; 84 } 85 if (stat & rdy) { 86 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 87 continue; 88 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 89 sdhci_transfer_pio(host, data); 90 data->dest += data->blocksize; 91 if (++block >= data->blocks) 92 break; 93 } 94 #ifdef CONFIG_MMC_SDMA 95 if (stat & SDHCI_INT_DMA_END) { 96 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 97 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 98 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 99 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 100 } 101 #endif 102 if (timeout-- > 0) 103 udelay(10); 104 else { 105 printf("Transfer data timeout\n"); 106 return -1; 107 } 108 } while (!(stat & SDHCI_INT_DATA_END)); 109 return 0; 110 } 111 112 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 113 struct mmc_data *data) 114 { 115 struct sdhci_host *host = (struct sdhci_host *)mmc->priv; 116 unsigned int stat = 0; 117 int ret = 0; 118 int trans_bytes = 0, is_aligned = 1; 119 u32 mask, flags, mode; 120 unsigned int timeout, start_addr = 0; 121 unsigned int retry = 10000; 122 123 /* Wait max 10 ms */ 124 timeout = 10; 125 126 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 127 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 128 129 /* We shouldn't wait for data inihibit for stop commands, even 130 though they might use busy signaling */ 131 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 132 mask &= ~SDHCI_DATA_INHIBIT; 133 134 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 135 if (timeout == 0) { 136 printf("Controller never released inhibit bit(s).\n"); 137 return COMM_ERR; 138 } 139 timeout--; 140 udelay(1000); 141 } 142 143 mask = SDHCI_INT_RESPONSE; 144 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 145 flags = SDHCI_CMD_RESP_NONE; 146 else if (cmd->resp_type & MMC_RSP_136) 147 flags = SDHCI_CMD_RESP_LONG; 148 else if (cmd->resp_type & MMC_RSP_BUSY) { 149 flags = SDHCI_CMD_RESP_SHORT_BUSY; 150 mask |= SDHCI_INT_DATA_END; 151 } else 152 flags = SDHCI_CMD_RESP_SHORT; 153 154 if (cmd->resp_type & MMC_RSP_CRC) 155 flags |= SDHCI_CMD_CRC; 156 if (cmd->resp_type & MMC_RSP_OPCODE) 157 flags |= SDHCI_CMD_INDEX; 158 if (data) 159 flags |= SDHCI_CMD_DATA; 160 161 /*Set Transfer mode regarding to data flag*/ 162 if (data != 0) { 163 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 164 mode = SDHCI_TRNS_BLK_CNT_EN; 165 trans_bytes = data->blocks * data->blocksize; 166 if (data->blocks > 1) 167 mode |= SDHCI_TRNS_MULTI; 168 169 if (data->flags == MMC_DATA_READ) 170 mode |= SDHCI_TRNS_READ; 171 172 #ifdef CONFIG_MMC_SDMA 173 if (data->flags == MMC_DATA_READ) 174 start_addr = (unsigned int)data->dest; 175 else 176 start_addr = (unsigned int)data->src; 177 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 178 (start_addr & 0x7) != 0x0) { 179 is_aligned = 0; 180 start_addr = (unsigned int)aligned_buffer; 181 if (data->flags != MMC_DATA_READ) 182 memcpy(aligned_buffer, data->src, trans_bytes); 183 } 184 185 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 186 mode |= SDHCI_TRNS_DMA; 187 #endif 188 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 189 data->blocksize), 190 SDHCI_BLOCK_SIZE); 191 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 192 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 193 } 194 195 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 196 #ifdef CONFIG_MMC_SDMA 197 flush_cache(start_addr, trans_bytes); 198 #endif 199 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 200 do { 201 stat = sdhci_readl(host, SDHCI_INT_STATUS); 202 if (stat & SDHCI_INT_ERROR) 203 break; 204 if (--retry == 0) 205 break; 206 } while ((stat & mask) != mask); 207 208 if (retry == 0) { 209 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) 210 return 0; 211 else { 212 printf("Timeout for status update!\n"); 213 return TIMEOUT; 214 } 215 } 216 217 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 218 sdhci_cmd_done(host, cmd); 219 sdhci_writel(host, mask, SDHCI_INT_STATUS); 220 } else 221 ret = -1; 222 223 if (!ret && data) 224 ret = sdhci_transfer_data(host, data, start_addr); 225 226 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 227 udelay(1000); 228 229 stat = sdhci_readl(host, SDHCI_INT_STATUS); 230 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 231 if (!ret) { 232 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 233 !is_aligned && (data->flags == MMC_DATA_READ)) 234 memcpy(data->dest, aligned_buffer, trans_bytes); 235 return 0; 236 } 237 238 sdhci_reset(host, SDHCI_RESET_CMD); 239 sdhci_reset(host, SDHCI_RESET_DATA); 240 if (stat & SDHCI_INT_TIMEOUT) 241 return TIMEOUT; 242 else 243 return COMM_ERR; 244 } 245 246 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 247 { 248 struct sdhci_host *host = (struct sdhci_host *)mmc->priv; 249 unsigned int div, clk, timeout; 250 251 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 252 253 if (clock == 0) 254 return 0; 255 256 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 257 /* Version 3.00 divisors must be a multiple of 2. */ 258 if (mmc->f_max <= clock) 259 div = 1; 260 else { 261 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { 262 if ((mmc->f_max / div) <= clock) 263 break; 264 } 265 } 266 } else { 267 /* Version 2.00 divisors must be a power of 2. */ 268 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 269 if ((mmc->f_max / div) <= clock) 270 break; 271 } 272 } 273 div >>= 1; 274 275 if (host->set_clock) 276 host->set_clock(host->index, div); 277 278 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 279 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 280 << SDHCI_DIVIDER_HI_SHIFT; 281 clk |= SDHCI_CLOCK_INT_EN; 282 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 283 284 /* Wait max 20 ms */ 285 timeout = 20; 286 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 287 & SDHCI_CLOCK_INT_STABLE)) { 288 if (timeout == 0) { 289 printf("Internal clock never stabilised.\n"); 290 return -1; 291 } 292 timeout--; 293 udelay(1000); 294 } 295 296 clk |= SDHCI_CLOCK_CARD_EN; 297 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 298 return 0; 299 } 300 301 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 302 { 303 u8 pwr = 0; 304 305 if (power != (unsigned short)-1) { 306 switch (1 << power) { 307 case MMC_VDD_165_195: 308 pwr = SDHCI_POWER_180; 309 break; 310 case MMC_VDD_29_30: 311 case MMC_VDD_30_31: 312 pwr = SDHCI_POWER_300; 313 break; 314 case MMC_VDD_32_33: 315 case MMC_VDD_33_34: 316 pwr = SDHCI_POWER_330; 317 break; 318 } 319 } 320 321 if (pwr == 0) { 322 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 323 return; 324 } 325 326 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 327 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 328 329 pwr |= SDHCI_POWER_ON; 330 331 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 332 } 333 334 void sdhci_set_ios(struct mmc *mmc) 335 { 336 u32 ctrl; 337 struct sdhci_host *host = (struct sdhci_host *)mmc->priv; 338 339 if (host->set_control_reg) 340 host->set_control_reg(host); 341 342 if (mmc->clock != host->clock) 343 sdhci_set_clock(mmc, mmc->clock); 344 345 /* Set bus width */ 346 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 347 if (mmc->bus_width == 8) { 348 ctrl &= ~SDHCI_CTRL_4BITBUS; 349 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 350 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 351 ctrl |= SDHCI_CTRL_8BITBUS; 352 } else { 353 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 354 ctrl &= ~SDHCI_CTRL_8BITBUS; 355 if (mmc->bus_width == 4) 356 ctrl |= SDHCI_CTRL_4BITBUS; 357 else 358 ctrl &= ~SDHCI_CTRL_4BITBUS; 359 } 360 361 if (mmc->clock > 26000000) 362 ctrl |= SDHCI_CTRL_HISPD; 363 else 364 ctrl &= ~SDHCI_CTRL_HISPD; 365 366 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) 367 ctrl &= ~SDHCI_CTRL_HISPD; 368 369 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 370 } 371 372 int sdhci_init(struct mmc *mmc) 373 { 374 struct sdhci_host *host = (struct sdhci_host *)mmc->priv; 375 376 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 377 aligned_buffer = memalign(8, 512*1024); 378 if (!aligned_buffer) { 379 printf("Aligned buffer alloc failed!!!"); 380 return -1; 381 } 382 } 383 384 sdhci_set_power(host, fls(mmc->voltages) - 1); 385 386 if (host->quirks & SDHCI_QUIRK_NO_CD) { 387 unsigned int status; 388 389 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, 390 SDHCI_HOST_CONTROL); 391 392 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 393 while ((!(status & SDHCI_CARD_PRESENT)) || 394 (!(status & SDHCI_CARD_STATE_STABLE)) || 395 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) 396 status = sdhci_readl(host, SDHCI_PRESENT_STATE); 397 } 398 399 /* Enable only interrupts served by the SD controller */ 400 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK 401 , SDHCI_INT_ENABLE); 402 /* Mask all sdhci interrupt sources */ 403 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 404 405 return 0; 406 } 407 408 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) 409 { 410 struct mmc *mmc; 411 unsigned int caps; 412 413 mmc = malloc(sizeof(struct mmc)); 414 if (!mmc) { 415 printf("mmc malloc fail!\n"); 416 return -1; 417 } 418 419 mmc->priv = host; 420 host->mmc = mmc; 421 422 sprintf(mmc->name, "%s", host->name); 423 mmc->send_cmd = sdhci_send_command; 424 mmc->set_ios = sdhci_set_ios; 425 mmc->init = sdhci_init; 426 mmc->getcd = NULL; 427 mmc->getwp = NULL; 428 429 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 430 #ifdef CONFIG_MMC_SDMA 431 if (!(caps & SDHCI_CAN_DO_SDMA)) { 432 printf("Your controller don't support sdma!!\n"); 433 return -1; 434 } 435 #endif 436 437 if (max_clk) 438 mmc->f_max = max_clk; 439 else { 440 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 441 mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) 442 >> SDHCI_CLOCK_BASE_SHIFT; 443 else 444 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) 445 >> SDHCI_CLOCK_BASE_SHIFT; 446 mmc->f_max *= 1000000; 447 } 448 if (mmc->f_max == 0) { 449 printf("Hardware doesn't specify base clock frequency\n"); 450 return -1; 451 } 452 if (min_clk) 453 mmc->f_min = min_clk; 454 else { 455 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 456 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; 457 else 458 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; 459 } 460 461 mmc->voltages = 0; 462 if (caps & SDHCI_CAN_VDD_330) 463 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 464 if (caps & SDHCI_CAN_VDD_300) 465 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 466 if (caps & SDHCI_CAN_VDD_180) 467 mmc->voltages |= MMC_VDD_165_195; 468 469 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 470 mmc->voltages |= host->voltages; 471 472 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 473 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 474 if (caps & SDHCI_CAN_DO_8BIT) 475 mmc->host_caps |= MMC_MODE_8BIT; 476 } 477 if (host->host_caps) 478 mmc->host_caps |= host->host_caps; 479 480 sdhci_reset(host, SDHCI_RESET_ALL); 481 mmc_register(mmc); 482 483 return 0; 484 } 485