1 /* 2 * Copyright 2008, Freescale Semiconductor, Inc 3 * Andy Fleming 4 * 5 * Based vaguely on the Linux code 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <config.h> 11 #include <common.h> 12 #include <command.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <errno.h> 16 #include <mmc.h> 17 #include <part.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <linux/list.h> 21 #include <div64.h> 22 #include "mmc_private.h" 23 24 static struct list_head mmc_devices; 25 static int cur_dev_num = -1; 26 27 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) 28 { 29 return &mmc->block_dev; 30 } 31 32 __weak int board_mmc_getwp(struct mmc *mmc) 33 { 34 return -1; 35 } 36 37 int mmc_getwp(struct mmc *mmc) 38 { 39 int wp; 40 41 wp = board_mmc_getwp(mmc); 42 43 if (wp < 0) { 44 if (mmc->cfg->ops->getwp) 45 wp = mmc->cfg->ops->getwp(mmc); 46 else 47 wp = 0; 48 } 49 50 return wp; 51 } 52 53 __weak int board_mmc_getcd(struct mmc *mmc) 54 { 55 return -1; 56 } 57 58 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 59 { 60 int ret; 61 62 #ifdef CONFIG_MMC_TRACE 63 int i; 64 u8 *ptr; 65 66 printf("CMD_SEND:%d\n", cmd->cmdidx); 67 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 68 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 69 if (ret) { 70 printf("\t\tRET\t\t\t %d\n", ret); 71 } else { 72 switch (cmd->resp_type) { 73 case MMC_RSP_NONE: 74 printf("\t\tMMC_RSP_NONE\n"); 75 break; 76 case MMC_RSP_R1: 77 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 78 cmd->response[0]); 79 break; 80 case MMC_RSP_R1b: 81 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 82 cmd->response[0]); 83 break; 84 case MMC_RSP_R2: 85 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 86 cmd->response[0]); 87 printf("\t\t \t\t 0x%08X \n", 88 cmd->response[1]); 89 printf("\t\t \t\t 0x%08X \n", 90 cmd->response[2]); 91 printf("\t\t \t\t 0x%08X \n", 92 cmd->response[3]); 93 printf("\n"); 94 printf("\t\t\t\t\tDUMPING DATA\n"); 95 for (i = 0; i < 4; i++) { 96 int j; 97 printf("\t\t\t\t\t%03d - ", i*4); 98 ptr = (u8 *)&cmd->response[i]; 99 ptr += 3; 100 for (j = 0; j < 4; j++) 101 printf("%02X ", *ptr--); 102 printf("\n"); 103 } 104 break; 105 case MMC_RSP_R3: 106 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 107 cmd->response[0]); 108 break; 109 default: 110 printf("\t\tERROR MMC rsp not supported\n"); 111 break; 112 } 113 } 114 #else 115 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 116 #endif 117 return ret; 118 } 119 120 int mmc_send_status(struct mmc *mmc, int timeout) 121 { 122 struct mmc_cmd cmd; 123 int err, retries = 5; 124 #ifdef CONFIG_MMC_TRACE 125 int status; 126 #endif 127 128 cmd.cmdidx = MMC_CMD_SEND_STATUS; 129 cmd.resp_type = MMC_RSP_R1; 130 if (!mmc_host_is_spi(mmc)) 131 cmd.cmdarg = mmc->rca << 16; 132 133 while (1) { 134 err = mmc_send_cmd(mmc, &cmd, NULL); 135 if (!err) { 136 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 137 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 138 MMC_STATE_PRG) 139 break; 140 else if (cmd.response[0] & MMC_STATUS_MASK) { 141 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 142 printf("Status Error: 0x%08X\n", 143 cmd.response[0]); 144 #endif 145 return COMM_ERR; 146 } 147 } else if (--retries < 0) 148 return err; 149 150 if (timeout-- <= 0) 151 break; 152 153 udelay(1000); 154 } 155 156 #ifdef CONFIG_MMC_TRACE 157 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; 158 printf("CURR STATE:%d\n", status); 159 #endif 160 if (timeout <= 0) { 161 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 162 printf("Timeout waiting card ready\n"); 163 #endif 164 return TIMEOUT; 165 } 166 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) 167 return SWITCH_ERR; 168 169 return 0; 170 } 171 172 int mmc_set_blocklen(struct mmc *mmc, int len) 173 { 174 struct mmc_cmd cmd; 175 176 if (mmc->ddr_mode) 177 return 0; 178 179 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 180 cmd.resp_type = MMC_RSP_R1; 181 cmd.cmdarg = len; 182 183 return mmc_send_cmd(mmc, &cmd, NULL); 184 } 185 186 struct mmc *find_mmc_device(int dev_num) 187 { 188 struct mmc *m; 189 struct list_head *entry; 190 191 list_for_each(entry, &mmc_devices) { 192 m = list_entry(entry, struct mmc, link); 193 194 if (m->block_dev.devnum == dev_num) 195 return m; 196 } 197 198 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 199 printf("MMC Device %d not found\n", dev_num); 200 #endif 201 202 return NULL; 203 } 204 205 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 206 lbaint_t blkcnt) 207 { 208 struct mmc_cmd cmd; 209 struct mmc_data data; 210 211 if (blkcnt > 1) 212 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 213 else 214 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 215 216 if (mmc->high_capacity) 217 cmd.cmdarg = start; 218 else 219 cmd.cmdarg = start * mmc->read_bl_len; 220 221 cmd.resp_type = MMC_RSP_R1; 222 223 data.dest = dst; 224 data.blocks = blkcnt; 225 data.blocksize = mmc->read_bl_len; 226 data.flags = MMC_DATA_READ; 227 228 if (mmc_send_cmd(mmc, &cmd, &data)) 229 return 0; 230 231 if (blkcnt > 1) { 232 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 233 cmd.cmdarg = 0; 234 cmd.resp_type = MMC_RSP_R1b; 235 if (mmc_send_cmd(mmc, &cmd, NULL)) { 236 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 237 printf("mmc fail to send stop cmd\n"); 238 #endif 239 return 0; 240 } 241 } 242 243 return blkcnt; 244 } 245 246 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, 247 lbaint_t blkcnt, void *dst) 248 { 249 int dev_num = block_dev->devnum; 250 int err; 251 lbaint_t cur, blocks_todo = blkcnt; 252 253 if (blkcnt == 0) 254 return 0; 255 256 struct mmc *mmc = find_mmc_device(dev_num); 257 if (!mmc) 258 return 0; 259 260 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 261 if (err < 0) 262 return 0; 263 264 if ((start + blkcnt) > mmc->block_dev.lba) { 265 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 266 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 267 start + blkcnt, mmc->block_dev.lba); 268 #endif 269 return 0; 270 } 271 272 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 273 debug("%s: Failed to set blocklen\n", __func__); 274 return 0; 275 } 276 277 do { 278 cur = (blocks_todo > mmc->cfg->b_max) ? 279 mmc->cfg->b_max : blocks_todo; 280 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 281 debug("%s: Failed to read blocks\n", __func__); 282 return 0; 283 } 284 blocks_todo -= cur; 285 start += cur; 286 dst += cur * mmc->read_bl_len; 287 } while (blocks_todo > 0); 288 289 return blkcnt; 290 } 291 292 static int mmc_go_idle(struct mmc *mmc) 293 { 294 struct mmc_cmd cmd; 295 int err; 296 297 udelay(1000); 298 299 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 300 cmd.cmdarg = 0; 301 cmd.resp_type = MMC_RSP_NONE; 302 303 err = mmc_send_cmd(mmc, &cmd, NULL); 304 305 if (err) 306 return err; 307 308 udelay(2000); 309 310 return 0; 311 } 312 313 static int sd_send_op_cond(struct mmc *mmc) 314 { 315 int timeout = 1000; 316 int err; 317 struct mmc_cmd cmd; 318 319 while (1) { 320 cmd.cmdidx = MMC_CMD_APP_CMD; 321 cmd.resp_type = MMC_RSP_R1; 322 cmd.cmdarg = 0; 323 324 err = mmc_send_cmd(mmc, &cmd, NULL); 325 326 if (err) 327 return err; 328 329 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 330 cmd.resp_type = MMC_RSP_R3; 331 332 /* 333 * Most cards do not answer if some reserved bits 334 * in the ocr are set. However, Some controller 335 * can set bit 7 (reserved for low voltages), but 336 * how to manage low voltages SD card is not yet 337 * specified. 338 */ 339 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 340 (mmc->cfg->voltages & 0xff8000); 341 342 if (mmc->version == SD_VERSION_2) 343 cmd.cmdarg |= OCR_HCS; 344 345 err = mmc_send_cmd(mmc, &cmd, NULL); 346 347 if (err) 348 return err; 349 350 if (cmd.response[0] & OCR_BUSY) 351 break; 352 353 if (timeout-- <= 0) 354 return UNUSABLE_ERR; 355 356 udelay(1000); 357 } 358 359 if (mmc->version != SD_VERSION_2) 360 mmc->version = SD_VERSION_1_0; 361 362 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 363 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 364 cmd.resp_type = MMC_RSP_R3; 365 cmd.cmdarg = 0; 366 367 err = mmc_send_cmd(mmc, &cmd, NULL); 368 369 if (err) 370 return err; 371 } 372 373 mmc->ocr = cmd.response[0]; 374 375 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 376 mmc->rca = 0; 377 378 return 0; 379 } 380 381 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 382 { 383 struct mmc_cmd cmd; 384 int err; 385 386 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 387 cmd.resp_type = MMC_RSP_R3; 388 cmd.cmdarg = 0; 389 if (use_arg && !mmc_host_is_spi(mmc)) 390 cmd.cmdarg = OCR_HCS | 391 (mmc->cfg->voltages & 392 (mmc->ocr & OCR_VOLTAGE_MASK)) | 393 (mmc->ocr & OCR_ACCESS_MODE); 394 395 err = mmc_send_cmd(mmc, &cmd, NULL); 396 if (err) 397 return err; 398 mmc->ocr = cmd.response[0]; 399 return 0; 400 } 401 402 static int mmc_send_op_cond(struct mmc *mmc) 403 { 404 int err, i; 405 406 /* Some cards seem to need this */ 407 mmc_go_idle(mmc); 408 409 /* Asking to the card its capabilities */ 410 for (i = 0; i < 2; i++) { 411 err = mmc_send_op_cond_iter(mmc, i != 0); 412 if (err) 413 return err; 414 415 /* exit if not busy (flag seems to be inverted) */ 416 if (mmc->ocr & OCR_BUSY) 417 break; 418 } 419 mmc->op_cond_pending = 1; 420 return 0; 421 } 422 423 static int mmc_complete_op_cond(struct mmc *mmc) 424 { 425 struct mmc_cmd cmd; 426 int timeout = 1000; 427 uint start; 428 int err; 429 430 mmc->op_cond_pending = 0; 431 if (!(mmc->ocr & OCR_BUSY)) { 432 start = get_timer(0); 433 while (1) { 434 err = mmc_send_op_cond_iter(mmc, 1); 435 if (err) 436 return err; 437 if (mmc->ocr & OCR_BUSY) 438 break; 439 if (get_timer(start) > timeout) 440 return UNUSABLE_ERR; 441 udelay(100); 442 } 443 } 444 445 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 446 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 447 cmd.resp_type = MMC_RSP_R3; 448 cmd.cmdarg = 0; 449 450 err = mmc_send_cmd(mmc, &cmd, NULL); 451 452 if (err) 453 return err; 454 455 mmc->ocr = cmd.response[0]; 456 } 457 458 mmc->version = MMC_VERSION_UNKNOWN; 459 460 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 461 mmc->rca = 1; 462 463 return 0; 464 } 465 466 467 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 468 { 469 struct mmc_cmd cmd; 470 struct mmc_data data; 471 int err; 472 473 /* Get the Card Status Register */ 474 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 475 cmd.resp_type = MMC_RSP_R1; 476 cmd.cmdarg = 0; 477 478 data.dest = (char *)ext_csd; 479 data.blocks = 1; 480 data.blocksize = MMC_MAX_BLOCK_LEN; 481 data.flags = MMC_DATA_READ; 482 483 err = mmc_send_cmd(mmc, &cmd, &data); 484 485 return err; 486 } 487 488 489 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 490 { 491 struct mmc_cmd cmd; 492 int timeout = 1000; 493 int ret; 494 495 cmd.cmdidx = MMC_CMD_SWITCH; 496 cmd.resp_type = MMC_RSP_R1b; 497 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 498 (index << 16) | 499 (value << 8); 500 501 ret = mmc_send_cmd(mmc, &cmd, NULL); 502 503 /* Waiting for the ready status */ 504 if (!ret) 505 ret = mmc_send_status(mmc, timeout); 506 507 return ret; 508 509 } 510 511 static int mmc_change_freq(struct mmc *mmc) 512 { 513 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 514 char cardtype; 515 int err; 516 517 mmc->card_caps = 0; 518 519 if (mmc_host_is_spi(mmc)) 520 return 0; 521 522 /* Only version 4 supports high-speed */ 523 if (mmc->version < MMC_VERSION_4) 524 return 0; 525 526 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 527 528 err = mmc_send_ext_csd(mmc, ext_csd); 529 530 if (err) 531 return err; 532 533 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; 534 535 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); 536 537 if (err) 538 return err == SWITCH_ERR ? 0 : err; 539 540 /* Now check to see that it worked */ 541 err = mmc_send_ext_csd(mmc, ext_csd); 542 543 if (err) 544 return err; 545 546 /* No high-speed support */ 547 if (!ext_csd[EXT_CSD_HS_TIMING]) 548 return 0; 549 550 /* High Speed is set, there are two types: 52MHz and 26MHz */ 551 if (cardtype & EXT_CSD_CARD_TYPE_52) { 552 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 553 mmc->card_caps |= MMC_MODE_DDR_52MHz; 554 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 555 } else { 556 mmc->card_caps |= MMC_MODE_HS; 557 } 558 559 return 0; 560 } 561 562 static int mmc_set_capacity(struct mmc *mmc, int part_num) 563 { 564 switch (part_num) { 565 case 0: 566 mmc->capacity = mmc->capacity_user; 567 break; 568 case 1: 569 case 2: 570 mmc->capacity = mmc->capacity_boot; 571 break; 572 case 3: 573 mmc->capacity = mmc->capacity_rpmb; 574 break; 575 case 4: 576 case 5: 577 case 6: 578 case 7: 579 mmc->capacity = mmc->capacity_gp[part_num - 4]; 580 break; 581 default: 582 return -1; 583 } 584 585 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 586 587 return 0; 588 } 589 590 int mmc_switch_part(int dev_num, unsigned int part_num) 591 { 592 struct mmc *mmc = find_mmc_device(dev_num); 593 int ret; 594 595 if (!mmc) 596 return -1; 597 598 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 599 (mmc->part_config & ~PART_ACCESS_MASK) 600 | (part_num & PART_ACCESS_MASK)); 601 602 /* 603 * Set the capacity if the switch succeeded or was intended 604 * to return to representing the raw device. 605 */ 606 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 607 ret = mmc_set_capacity(mmc, part_num); 608 mmc->block_dev.hwpart = part_num; 609 } 610 611 return ret; 612 } 613 614 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) 615 { 616 struct mmc *mmc = find_mmc_device(desc->devnum); 617 int ret; 618 619 if (!mmc) 620 return -ENODEV; 621 622 if (mmc->block_dev.hwpart == hwpart) 623 return 0; 624 625 if (mmc->part_config == MMCPART_NOAVAILABLE) 626 return -EMEDIUMTYPE; 627 628 ret = mmc_switch_part(desc->devnum, hwpart); 629 if (ret) 630 return ret; 631 632 return 0; 633 } 634 635 int mmc_select_hwpart(int dev_num, int hwpart) 636 { 637 struct mmc *mmc = find_mmc_device(dev_num); 638 int ret; 639 640 if (!mmc) 641 return -ENODEV; 642 643 if (mmc->block_dev.hwpart == hwpart) 644 return 0; 645 646 if (mmc->part_config == MMCPART_NOAVAILABLE) 647 return -EMEDIUMTYPE; 648 649 ret = mmc_switch_part(dev_num, hwpart); 650 if (ret) 651 return ret; 652 653 return 0; 654 } 655 656 int mmc_hwpart_config(struct mmc *mmc, 657 const struct mmc_hwpart_conf *conf, 658 enum mmc_hwpart_conf_mode mode) 659 { 660 u8 part_attrs = 0; 661 u32 enh_size_mult; 662 u32 enh_start_addr; 663 u32 gp_size_mult[4]; 664 u32 max_enh_size_mult; 665 u32 tot_enh_size_mult = 0; 666 u8 wr_rel_set; 667 int i, pidx, err; 668 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 669 670 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 671 return -EINVAL; 672 673 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 674 printf("eMMC >= 4.4 required for enhanced user data area\n"); 675 return -EMEDIUMTYPE; 676 } 677 678 if (!(mmc->part_support & PART_SUPPORT)) { 679 printf("Card does not support partitioning\n"); 680 return -EMEDIUMTYPE; 681 } 682 683 if (!mmc->hc_wp_grp_size) { 684 printf("Card does not define HC WP group size\n"); 685 return -EMEDIUMTYPE; 686 } 687 688 /* check partition alignment and total enhanced size */ 689 if (conf->user.enh_size) { 690 if (conf->user.enh_size % mmc->hc_wp_grp_size || 691 conf->user.enh_start % mmc->hc_wp_grp_size) { 692 printf("User data enhanced area not HC WP group " 693 "size aligned\n"); 694 return -EINVAL; 695 } 696 part_attrs |= EXT_CSD_ENH_USR; 697 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 698 if (mmc->high_capacity) { 699 enh_start_addr = conf->user.enh_start; 700 } else { 701 enh_start_addr = (conf->user.enh_start << 9); 702 } 703 } else { 704 enh_size_mult = 0; 705 enh_start_addr = 0; 706 } 707 tot_enh_size_mult += enh_size_mult; 708 709 for (pidx = 0; pidx < 4; pidx++) { 710 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 711 printf("GP%i partition not HC WP group size " 712 "aligned\n", pidx+1); 713 return -EINVAL; 714 } 715 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 716 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 717 part_attrs |= EXT_CSD_ENH_GP(pidx); 718 tot_enh_size_mult += gp_size_mult[pidx]; 719 } 720 } 721 722 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 723 printf("Card does not support enhanced attribute\n"); 724 return -EMEDIUMTYPE; 725 } 726 727 err = mmc_send_ext_csd(mmc, ext_csd); 728 if (err) 729 return err; 730 731 max_enh_size_mult = 732 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 733 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 734 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 735 if (tot_enh_size_mult > max_enh_size_mult) { 736 printf("Total enhanced size exceeds maximum (%u > %u)\n", 737 tot_enh_size_mult, max_enh_size_mult); 738 return -EMEDIUMTYPE; 739 } 740 741 /* The default value of EXT_CSD_WR_REL_SET is device 742 * dependent, the values can only be changed if the 743 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 744 * changed only once and before partitioning is completed. */ 745 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 746 if (conf->user.wr_rel_change) { 747 if (conf->user.wr_rel_set) 748 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 749 else 750 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 751 } 752 for (pidx = 0; pidx < 4; pidx++) { 753 if (conf->gp_part[pidx].wr_rel_change) { 754 if (conf->gp_part[pidx].wr_rel_set) 755 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 756 else 757 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 758 } 759 } 760 761 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 762 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 763 puts("Card does not support host controlled partition write " 764 "reliability settings\n"); 765 return -EMEDIUMTYPE; 766 } 767 768 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 769 EXT_CSD_PARTITION_SETTING_COMPLETED) { 770 printf("Card already partitioned\n"); 771 return -EPERM; 772 } 773 774 if (mode == MMC_HWPART_CONF_CHECK) 775 return 0; 776 777 /* Partitioning requires high-capacity size definitions */ 778 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 779 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 780 EXT_CSD_ERASE_GROUP_DEF, 1); 781 782 if (err) 783 return err; 784 785 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 786 787 /* update erase group size to be high-capacity */ 788 mmc->erase_grp_size = 789 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 790 791 } 792 793 /* all OK, write the configuration */ 794 for (i = 0; i < 4; i++) { 795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 796 EXT_CSD_ENH_START_ADDR+i, 797 (enh_start_addr >> (i*8)) & 0xFF); 798 if (err) 799 return err; 800 } 801 for (i = 0; i < 3; i++) { 802 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 803 EXT_CSD_ENH_SIZE_MULT+i, 804 (enh_size_mult >> (i*8)) & 0xFF); 805 if (err) 806 return err; 807 } 808 for (pidx = 0; pidx < 4; pidx++) { 809 for (i = 0; i < 3; i++) { 810 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 811 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 812 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 813 if (err) 814 return err; 815 } 816 } 817 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 818 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 819 if (err) 820 return err; 821 822 if (mode == MMC_HWPART_CONF_SET) 823 return 0; 824 825 /* The WR_REL_SET is a write-once register but shall be 826 * written before setting PART_SETTING_COMPLETED. As it is 827 * write-once we can only write it when completing the 828 * partitioning. */ 829 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 830 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 831 EXT_CSD_WR_REL_SET, wr_rel_set); 832 if (err) 833 return err; 834 } 835 836 /* Setting PART_SETTING_COMPLETED confirms the partition 837 * configuration but it only becomes effective after power 838 * cycle, so we do not adjust the partition related settings 839 * in the mmc struct. */ 840 841 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 842 EXT_CSD_PARTITION_SETTING, 843 EXT_CSD_PARTITION_SETTING_COMPLETED); 844 if (err) 845 return err; 846 847 return 0; 848 } 849 850 int mmc_getcd(struct mmc *mmc) 851 { 852 int cd; 853 854 cd = board_mmc_getcd(mmc); 855 856 if (cd < 0) { 857 if (mmc->cfg->ops->getcd) 858 cd = mmc->cfg->ops->getcd(mmc); 859 else 860 cd = 1; 861 } 862 863 return cd; 864 } 865 866 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 867 { 868 struct mmc_cmd cmd; 869 struct mmc_data data; 870 871 /* Switch the frequency */ 872 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 873 cmd.resp_type = MMC_RSP_R1; 874 cmd.cmdarg = (mode << 31) | 0xffffff; 875 cmd.cmdarg &= ~(0xf << (group * 4)); 876 cmd.cmdarg |= value << (group * 4); 877 878 data.dest = (char *)resp; 879 data.blocksize = 64; 880 data.blocks = 1; 881 data.flags = MMC_DATA_READ; 882 883 return mmc_send_cmd(mmc, &cmd, &data); 884 } 885 886 887 static int sd_change_freq(struct mmc *mmc) 888 { 889 int err; 890 struct mmc_cmd cmd; 891 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); 892 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 893 struct mmc_data data; 894 int timeout; 895 896 mmc->card_caps = 0; 897 898 if (mmc_host_is_spi(mmc)) 899 return 0; 900 901 /* Read the SCR to find out if this card supports higher speeds */ 902 cmd.cmdidx = MMC_CMD_APP_CMD; 903 cmd.resp_type = MMC_RSP_R1; 904 cmd.cmdarg = mmc->rca << 16; 905 906 err = mmc_send_cmd(mmc, &cmd, NULL); 907 908 if (err) 909 return err; 910 911 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 912 cmd.resp_type = MMC_RSP_R1; 913 cmd.cmdarg = 0; 914 915 timeout = 3; 916 917 retry_scr: 918 data.dest = (char *)scr; 919 data.blocksize = 8; 920 data.blocks = 1; 921 data.flags = MMC_DATA_READ; 922 923 err = mmc_send_cmd(mmc, &cmd, &data); 924 925 if (err) { 926 if (timeout--) 927 goto retry_scr; 928 929 return err; 930 } 931 932 mmc->scr[0] = __be32_to_cpu(scr[0]); 933 mmc->scr[1] = __be32_to_cpu(scr[1]); 934 935 switch ((mmc->scr[0] >> 24) & 0xf) { 936 case 0: 937 mmc->version = SD_VERSION_1_0; 938 break; 939 case 1: 940 mmc->version = SD_VERSION_1_10; 941 break; 942 case 2: 943 mmc->version = SD_VERSION_2; 944 if ((mmc->scr[0] >> 15) & 0x1) 945 mmc->version = SD_VERSION_3; 946 break; 947 default: 948 mmc->version = SD_VERSION_1_0; 949 break; 950 } 951 952 if (mmc->scr[0] & SD_DATA_4BIT) 953 mmc->card_caps |= MMC_MODE_4BIT; 954 955 /* Version 1.0 doesn't support switching */ 956 if (mmc->version == SD_VERSION_1_0) 957 return 0; 958 959 timeout = 4; 960 while (timeout--) { 961 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 962 (u8 *)switch_status); 963 964 if (err) 965 return err; 966 967 /* The high-speed function is busy. Try again */ 968 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 969 break; 970 } 971 972 /* If high-speed isn't supported, we return */ 973 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) 974 return 0; 975 976 /* 977 * If the host doesn't support SD_HIGHSPEED, do not switch card to 978 * HIGHSPEED mode even if the card support SD_HIGHSPPED. 979 * This can avoid furthur problem when the card runs in different 980 * mode between the host. 981 */ 982 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && 983 (mmc->cfg->host_caps & MMC_MODE_HS))) 984 return 0; 985 986 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); 987 988 if (err) 989 return err; 990 991 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) 992 mmc->card_caps |= MMC_MODE_HS; 993 994 return 0; 995 } 996 997 /* frequency bases */ 998 /* divided by 10 to be nice to platforms without floating point */ 999 static const int fbase[] = { 1000 10000, 1001 100000, 1002 1000000, 1003 10000000, 1004 }; 1005 1006 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1007 * to platforms without floating point. 1008 */ 1009 static const int multipliers[] = { 1010 0, /* reserved */ 1011 10, 1012 12, 1013 13, 1014 15, 1015 20, 1016 25, 1017 30, 1018 35, 1019 40, 1020 45, 1021 50, 1022 55, 1023 60, 1024 70, 1025 80, 1026 }; 1027 1028 static void mmc_set_ios(struct mmc *mmc) 1029 { 1030 if (mmc->cfg->ops->set_ios) 1031 mmc->cfg->ops->set_ios(mmc); 1032 } 1033 1034 void mmc_set_clock(struct mmc *mmc, uint clock) 1035 { 1036 if (clock > mmc->cfg->f_max) 1037 clock = mmc->cfg->f_max; 1038 1039 if (clock < mmc->cfg->f_min) 1040 clock = mmc->cfg->f_min; 1041 1042 mmc->clock = clock; 1043 1044 mmc_set_ios(mmc); 1045 } 1046 1047 static void mmc_set_bus_width(struct mmc *mmc, uint width) 1048 { 1049 mmc->bus_width = width; 1050 1051 mmc_set_ios(mmc); 1052 } 1053 1054 static int mmc_startup(struct mmc *mmc) 1055 { 1056 int err, i; 1057 uint mult, freq; 1058 u64 cmult, csize, capacity; 1059 struct mmc_cmd cmd; 1060 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1061 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1062 int timeout = 1000; 1063 bool has_parts = false; 1064 bool part_completed; 1065 1066 #ifdef CONFIG_MMC_SPI_CRC_ON 1067 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 1068 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 1069 cmd.resp_type = MMC_RSP_R1; 1070 cmd.cmdarg = 1; 1071 err = mmc_send_cmd(mmc, &cmd, NULL); 1072 1073 if (err) 1074 return err; 1075 } 1076 #endif 1077 1078 /* Put the Card in Identify Mode */ 1079 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 1080 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 1081 cmd.resp_type = MMC_RSP_R2; 1082 cmd.cmdarg = 0; 1083 1084 err = mmc_send_cmd(mmc, &cmd, NULL); 1085 1086 if (err) 1087 return err; 1088 1089 memcpy(mmc->cid, cmd.response, 16); 1090 1091 /* 1092 * For MMC cards, set the Relative Address. 1093 * For SD cards, get the Relatvie Address. 1094 * This also puts the cards into Standby State 1095 */ 1096 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1097 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 1098 cmd.cmdarg = mmc->rca << 16; 1099 cmd.resp_type = MMC_RSP_R6; 1100 1101 err = mmc_send_cmd(mmc, &cmd, NULL); 1102 1103 if (err) 1104 return err; 1105 1106 if (IS_SD(mmc)) 1107 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 1108 } 1109 1110 /* Get the Card-Specific Data */ 1111 cmd.cmdidx = MMC_CMD_SEND_CSD; 1112 cmd.resp_type = MMC_RSP_R2; 1113 cmd.cmdarg = mmc->rca << 16; 1114 1115 err = mmc_send_cmd(mmc, &cmd, NULL); 1116 1117 /* Waiting for the ready status */ 1118 mmc_send_status(mmc, timeout); 1119 1120 if (err) 1121 return err; 1122 1123 mmc->csd[0] = cmd.response[0]; 1124 mmc->csd[1] = cmd.response[1]; 1125 mmc->csd[2] = cmd.response[2]; 1126 mmc->csd[3] = cmd.response[3]; 1127 1128 if (mmc->version == MMC_VERSION_UNKNOWN) { 1129 int version = (cmd.response[0] >> 26) & 0xf; 1130 1131 switch (version) { 1132 case 0: 1133 mmc->version = MMC_VERSION_1_2; 1134 break; 1135 case 1: 1136 mmc->version = MMC_VERSION_1_4; 1137 break; 1138 case 2: 1139 mmc->version = MMC_VERSION_2_2; 1140 break; 1141 case 3: 1142 mmc->version = MMC_VERSION_3; 1143 break; 1144 case 4: 1145 mmc->version = MMC_VERSION_4; 1146 break; 1147 default: 1148 mmc->version = MMC_VERSION_1_2; 1149 break; 1150 } 1151 } 1152 1153 /* divide frequency by 10, since the mults are 10x bigger */ 1154 freq = fbase[(cmd.response[0] & 0x7)]; 1155 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 1156 1157 mmc->tran_speed = freq * mult; 1158 1159 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 1160 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 1161 1162 if (IS_SD(mmc)) 1163 mmc->write_bl_len = mmc->read_bl_len; 1164 else 1165 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 1166 1167 if (mmc->high_capacity) { 1168 csize = (mmc->csd[1] & 0x3f) << 16 1169 | (mmc->csd[2] & 0xffff0000) >> 16; 1170 cmult = 8; 1171 } else { 1172 csize = (mmc->csd[1] & 0x3ff) << 2 1173 | (mmc->csd[2] & 0xc0000000) >> 30; 1174 cmult = (mmc->csd[2] & 0x00038000) >> 15; 1175 } 1176 1177 mmc->capacity_user = (csize + 1) << (cmult + 2); 1178 mmc->capacity_user *= mmc->read_bl_len; 1179 mmc->capacity_boot = 0; 1180 mmc->capacity_rpmb = 0; 1181 for (i = 0; i < 4; i++) 1182 mmc->capacity_gp[i] = 0; 1183 1184 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 1185 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1186 1187 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 1188 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1189 1190 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 1191 cmd.cmdidx = MMC_CMD_SET_DSR; 1192 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 1193 cmd.resp_type = MMC_RSP_NONE; 1194 if (mmc_send_cmd(mmc, &cmd, NULL)) 1195 printf("MMC: SET_DSR failed\n"); 1196 } 1197 1198 /* Select the card, and put it into Transfer Mode */ 1199 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 1200 cmd.cmdidx = MMC_CMD_SELECT_CARD; 1201 cmd.resp_type = MMC_RSP_R1; 1202 cmd.cmdarg = mmc->rca << 16; 1203 err = mmc_send_cmd(mmc, &cmd, NULL); 1204 1205 if (err) 1206 return err; 1207 } 1208 1209 /* 1210 * For SD, its erase group is always one sector 1211 */ 1212 mmc->erase_grp_size = 1; 1213 mmc->part_config = MMCPART_NOAVAILABLE; 1214 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { 1215 /* check ext_csd version and capacity */ 1216 err = mmc_send_ext_csd(mmc, ext_csd); 1217 if (err) 1218 return err; 1219 if (ext_csd[EXT_CSD_REV] >= 2) { 1220 /* 1221 * According to the JEDEC Standard, the value of 1222 * ext_csd's capacity is valid if the value is more 1223 * than 2GB 1224 */ 1225 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 1226 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 1227 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 1228 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 1229 capacity *= MMC_MAX_BLOCK_LEN; 1230 if ((capacity >> 20) > 2 * 1024) 1231 mmc->capacity_user = capacity; 1232 } 1233 1234 switch (ext_csd[EXT_CSD_REV]) { 1235 case 1: 1236 mmc->version = MMC_VERSION_4_1; 1237 break; 1238 case 2: 1239 mmc->version = MMC_VERSION_4_2; 1240 break; 1241 case 3: 1242 mmc->version = MMC_VERSION_4_3; 1243 break; 1244 case 5: 1245 mmc->version = MMC_VERSION_4_41; 1246 break; 1247 case 6: 1248 mmc->version = MMC_VERSION_4_5; 1249 break; 1250 case 7: 1251 mmc->version = MMC_VERSION_5_0; 1252 break; 1253 } 1254 1255 /* The partition data may be non-zero but it is only 1256 * effective if PARTITION_SETTING_COMPLETED is set in 1257 * EXT_CSD, so ignore any data if this bit is not set, 1258 * except for enabling the high-capacity group size 1259 * definition (see below). */ 1260 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 1261 EXT_CSD_PARTITION_SETTING_COMPLETED); 1262 1263 /* store the partition info of emmc */ 1264 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 1265 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 1266 ext_csd[EXT_CSD_BOOT_MULT]) 1267 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 1268 if (part_completed && 1269 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 1270 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 1271 1272 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 1273 1274 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 1275 1276 for (i = 0; i < 4; i++) { 1277 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 1278 uint mult = (ext_csd[idx + 2] << 16) + 1279 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 1280 if (mult) 1281 has_parts = true; 1282 if (!part_completed) 1283 continue; 1284 mmc->capacity_gp[i] = mult; 1285 mmc->capacity_gp[i] *= 1286 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1287 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1288 mmc->capacity_gp[i] <<= 19; 1289 } 1290 1291 if (part_completed) { 1292 mmc->enh_user_size = 1293 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + 1294 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + 1295 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 1296 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 1297 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1298 mmc->enh_user_size <<= 19; 1299 mmc->enh_user_start = 1300 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + 1301 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + 1302 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + 1303 ext_csd[EXT_CSD_ENH_START_ADDR]; 1304 if (mmc->high_capacity) 1305 mmc->enh_user_start <<= 9; 1306 } 1307 1308 /* 1309 * Host needs to enable ERASE_GRP_DEF bit if device is 1310 * partitioned. This bit will be lost every time after a reset 1311 * or power off. This will affect erase size. 1312 */ 1313 if (part_completed) 1314 has_parts = true; 1315 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 1316 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 1317 has_parts = true; 1318 if (has_parts) { 1319 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1320 EXT_CSD_ERASE_GROUP_DEF, 1); 1321 1322 if (err) 1323 return err; 1324 else 1325 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1326 } 1327 1328 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 1329 /* Read out group size from ext_csd */ 1330 mmc->erase_grp_size = 1331 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1332 /* 1333 * if high capacity and partition setting completed 1334 * SEC_COUNT is valid even if it is smaller than 2 GiB 1335 * JEDEC Standard JESD84-B45, 6.2.4 1336 */ 1337 if (mmc->high_capacity && part_completed) { 1338 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 1339 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 1340 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 1341 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 1342 capacity *= MMC_MAX_BLOCK_LEN; 1343 mmc->capacity_user = capacity; 1344 } 1345 } else { 1346 /* Calculate the group size from the csd value. */ 1347 int erase_gsz, erase_gmul; 1348 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 1349 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 1350 mmc->erase_grp_size = (erase_gsz + 1) 1351 * (erase_gmul + 1); 1352 } 1353 1354 mmc->hc_wp_grp_size = 1024 1355 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1356 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 1357 1358 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1359 } 1360 1361 err = mmc_set_capacity(mmc, mmc->block_dev.hwpart); 1362 if (err) 1363 return err; 1364 1365 if (IS_SD(mmc)) 1366 err = sd_change_freq(mmc); 1367 else 1368 err = mmc_change_freq(mmc); 1369 1370 if (err) 1371 return err; 1372 1373 /* Restrict card's capabilities by what the host can do */ 1374 mmc->card_caps &= mmc->cfg->host_caps; 1375 1376 if (IS_SD(mmc)) { 1377 if (mmc->card_caps & MMC_MODE_4BIT) { 1378 cmd.cmdidx = MMC_CMD_APP_CMD; 1379 cmd.resp_type = MMC_RSP_R1; 1380 cmd.cmdarg = mmc->rca << 16; 1381 1382 err = mmc_send_cmd(mmc, &cmd, NULL); 1383 if (err) 1384 return err; 1385 1386 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1387 cmd.resp_type = MMC_RSP_R1; 1388 cmd.cmdarg = 2; 1389 err = mmc_send_cmd(mmc, &cmd, NULL); 1390 if (err) 1391 return err; 1392 1393 mmc_set_bus_width(mmc, 4); 1394 } 1395 1396 if (mmc->card_caps & MMC_MODE_HS) 1397 mmc->tran_speed = 50000000; 1398 else 1399 mmc->tran_speed = 25000000; 1400 } else if (mmc->version >= MMC_VERSION_4) { 1401 /* Only version 4 of MMC supports wider bus widths */ 1402 int idx; 1403 1404 /* An array of possible bus widths in order of preference */ 1405 static unsigned ext_csd_bits[] = { 1406 EXT_CSD_DDR_BUS_WIDTH_8, 1407 EXT_CSD_DDR_BUS_WIDTH_4, 1408 EXT_CSD_BUS_WIDTH_8, 1409 EXT_CSD_BUS_WIDTH_4, 1410 EXT_CSD_BUS_WIDTH_1, 1411 }; 1412 1413 /* An array to map CSD bus widths to host cap bits */ 1414 static unsigned ext_to_hostcaps[] = { 1415 [EXT_CSD_DDR_BUS_WIDTH_4] = 1416 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, 1417 [EXT_CSD_DDR_BUS_WIDTH_8] = 1418 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, 1419 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, 1420 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, 1421 }; 1422 1423 /* An array to map chosen bus width to an integer */ 1424 static unsigned widths[] = { 1425 8, 4, 8, 4, 1, 1426 }; 1427 1428 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { 1429 unsigned int extw = ext_csd_bits[idx]; 1430 unsigned int caps = ext_to_hostcaps[extw]; 1431 1432 /* 1433 * If the bus width is still not changed, 1434 * don't try to set the default again. 1435 * Otherwise, recover from switch attempts 1436 * by switching to 1-bit bus width. 1437 */ 1438 if (extw == EXT_CSD_BUS_WIDTH_1 && 1439 mmc->bus_width == 1) { 1440 err = 0; 1441 break; 1442 } 1443 1444 /* 1445 * Check to make sure the card and controller support 1446 * these capabilities 1447 */ 1448 if ((mmc->card_caps & caps) != caps) 1449 continue; 1450 1451 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1452 EXT_CSD_BUS_WIDTH, extw); 1453 1454 if (err) 1455 continue; 1456 1457 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; 1458 mmc_set_bus_width(mmc, widths[idx]); 1459 1460 err = mmc_send_ext_csd(mmc, test_csd); 1461 1462 if (err) 1463 continue; 1464 1465 /* Only compare read only fields */ 1466 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1467 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1468 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1469 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1470 ext_csd[EXT_CSD_REV] 1471 == test_csd[EXT_CSD_REV] && 1472 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1473 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1474 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1475 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1476 break; 1477 else 1478 err = SWITCH_ERR; 1479 } 1480 1481 if (err) 1482 return err; 1483 1484 if (mmc->card_caps & MMC_MODE_HS) { 1485 if (mmc->card_caps & MMC_MODE_HS_52MHz) 1486 mmc->tran_speed = 52000000; 1487 else 1488 mmc->tran_speed = 26000000; 1489 } 1490 } 1491 1492 mmc_set_clock(mmc, mmc->tran_speed); 1493 1494 /* Fix the block length for DDR mode */ 1495 if (mmc->ddr_mode) { 1496 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 1497 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 1498 } 1499 1500 /* fill in device description */ 1501 mmc->block_dev.lun = 0; 1502 mmc->block_dev.hwpart = 0; 1503 mmc->block_dev.type = 0; 1504 mmc->block_dev.blksz = mmc->read_bl_len; 1505 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); 1506 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); 1507 #if !defined(CONFIG_SPL_BUILD) || \ 1508 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 1509 !defined(CONFIG_USE_TINY_PRINTF)) 1510 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", 1511 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 1512 (mmc->cid[3] >> 16) & 0xffff); 1513 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 1514 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 1515 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 1516 (mmc->cid[2] >> 24) & 0xff); 1517 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 1518 (mmc->cid[2] >> 16) & 0xf); 1519 #else 1520 mmc->block_dev.vendor[0] = 0; 1521 mmc->block_dev.product[0] = 0; 1522 mmc->block_dev.revision[0] = 0; 1523 #endif 1524 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 1525 part_init(&mmc->block_dev); 1526 #endif 1527 1528 return 0; 1529 } 1530 1531 static int mmc_send_if_cond(struct mmc *mmc) 1532 { 1533 struct mmc_cmd cmd; 1534 int err; 1535 1536 cmd.cmdidx = SD_CMD_SEND_IF_COND; 1537 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 1538 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 1539 cmd.resp_type = MMC_RSP_R7; 1540 1541 err = mmc_send_cmd(mmc, &cmd, NULL); 1542 1543 if (err) 1544 return err; 1545 1546 if ((cmd.response[0] & 0xff) != 0xaa) 1547 return UNUSABLE_ERR; 1548 else 1549 mmc->version = SD_VERSION_2; 1550 1551 return 0; 1552 } 1553 1554 /* not used any more */ 1555 int __deprecated mmc_register(struct mmc *mmc) 1556 { 1557 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1558 printf("%s is deprecated! use mmc_create() instead.\n", __func__); 1559 #endif 1560 return -1; 1561 } 1562 1563 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) 1564 { 1565 struct mmc *mmc; 1566 1567 /* quick validation */ 1568 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || 1569 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) 1570 return NULL; 1571 1572 mmc = calloc(1, sizeof(*mmc)); 1573 if (mmc == NULL) 1574 return NULL; 1575 1576 mmc->cfg = cfg; 1577 mmc->priv = priv; 1578 1579 /* the following chunk was mmc_register() */ 1580 1581 /* Setup dsr related values */ 1582 mmc->dsr_imp = 0; 1583 mmc->dsr = 0xffffffff; 1584 /* Setup the universal parts of the block interface just once */ 1585 mmc->block_dev.if_type = IF_TYPE_MMC; 1586 mmc->block_dev.devnum = cur_dev_num++; 1587 mmc->block_dev.removable = 1; 1588 mmc->block_dev.block_read = mmc_bread; 1589 mmc->block_dev.block_write = mmc_bwrite; 1590 mmc->block_dev.block_erase = mmc_berase; 1591 1592 /* setup initial part type */ 1593 mmc->block_dev.part_type = mmc->cfg->part_type; 1594 1595 INIT_LIST_HEAD(&mmc->link); 1596 1597 list_add_tail(&mmc->link, &mmc_devices); 1598 1599 return mmc; 1600 } 1601 1602 void mmc_destroy(struct mmc *mmc) 1603 { 1604 /* only freeing memory for now */ 1605 free(mmc); 1606 } 1607 1608 static int mmc_get_dev(int dev, struct blk_desc **descp) 1609 { 1610 struct mmc *mmc = find_mmc_device(dev); 1611 int ret; 1612 1613 if (!mmc) 1614 return -ENODEV; 1615 ret = mmc_init(mmc); 1616 if (ret) 1617 return ret; 1618 1619 *descp = &mmc->block_dev; 1620 1621 return 0; 1622 } 1623 1624 /* board-specific MMC power initializations. */ 1625 __weak void board_mmc_power_init(void) 1626 { 1627 } 1628 1629 int mmc_start_init(struct mmc *mmc) 1630 { 1631 int err; 1632 1633 /* we pretend there's no card when init is NULL */ 1634 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { 1635 mmc->has_init = 0; 1636 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1637 printf("MMC: no card present\n"); 1638 #endif 1639 return NO_CARD_ERR; 1640 } 1641 1642 if (mmc->has_init) 1643 return 0; 1644 1645 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1646 mmc_adapter_card_type_ident(); 1647 #endif 1648 board_mmc_power_init(); 1649 1650 /* made sure it's not NULL earlier */ 1651 err = mmc->cfg->ops->init(mmc); 1652 1653 if (err) 1654 return err; 1655 1656 mmc->ddr_mode = 0; 1657 mmc_set_bus_width(mmc, 1); 1658 mmc_set_clock(mmc, 1); 1659 1660 /* Reset the Card */ 1661 err = mmc_go_idle(mmc); 1662 1663 if (err) 1664 return err; 1665 1666 /* The internal partition reset to user partition(0) at every CMD0*/ 1667 mmc->block_dev.hwpart = 0; 1668 1669 /* Test for SD version 2 */ 1670 err = mmc_send_if_cond(mmc); 1671 1672 /* Now try to get the SD card's operating condition */ 1673 err = sd_send_op_cond(mmc); 1674 1675 /* If the command timed out, we check for an MMC card */ 1676 if (err == TIMEOUT) { 1677 err = mmc_send_op_cond(mmc); 1678 1679 if (err) { 1680 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1681 printf("Card did not respond to voltage select!\n"); 1682 #endif 1683 return UNUSABLE_ERR; 1684 } 1685 } 1686 1687 if (!err) 1688 mmc->init_in_progress = 1; 1689 1690 return err; 1691 } 1692 1693 static int mmc_complete_init(struct mmc *mmc) 1694 { 1695 int err = 0; 1696 1697 mmc->init_in_progress = 0; 1698 if (mmc->op_cond_pending) 1699 err = mmc_complete_op_cond(mmc); 1700 1701 if (!err) 1702 err = mmc_startup(mmc); 1703 if (err) 1704 mmc->has_init = 0; 1705 else 1706 mmc->has_init = 1; 1707 return err; 1708 } 1709 1710 int mmc_init(struct mmc *mmc) 1711 { 1712 int err = 0; 1713 unsigned start; 1714 1715 if (mmc->has_init) 1716 return 0; 1717 1718 start = get_timer(0); 1719 1720 if (!mmc->init_in_progress) 1721 err = mmc_start_init(mmc); 1722 1723 if (!err) 1724 err = mmc_complete_init(mmc); 1725 debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); 1726 return err; 1727 } 1728 1729 int mmc_set_dsr(struct mmc *mmc, u16 val) 1730 { 1731 mmc->dsr = val; 1732 return 0; 1733 } 1734 1735 /* CPU-specific MMC initializations */ 1736 __weak int cpu_mmc_init(bd_t *bis) 1737 { 1738 return -1; 1739 } 1740 1741 /* board-specific MMC initializations. */ 1742 __weak int board_mmc_init(bd_t *bis) 1743 { 1744 return -1; 1745 } 1746 1747 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 1748 1749 void print_mmc_devices(char separator) 1750 { 1751 struct mmc *m; 1752 struct list_head *entry; 1753 char *mmc_type; 1754 1755 list_for_each(entry, &mmc_devices) { 1756 m = list_entry(entry, struct mmc, link); 1757 1758 if (m->has_init) 1759 mmc_type = IS_SD(m) ? "SD" : "eMMC"; 1760 else 1761 mmc_type = NULL; 1762 1763 printf("%s: %d", m->cfg->name, m->block_dev.devnum); 1764 if (mmc_type) 1765 printf(" (%s)", mmc_type); 1766 1767 if (entry->next != &mmc_devices) { 1768 printf("%c", separator); 1769 if (separator != '\n') 1770 puts (" "); 1771 } 1772 } 1773 1774 printf("\n"); 1775 } 1776 1777 #else 1778 void print_mmc_devices(char separator) { } 1779 #endif 1780 1781 int get_mmc_num(void) 1782 { 1783 return cur_dev_num; 1784 } 1785 1786 void mmc_set_preinit(struct mmc *mmc, int preinit) 1787 { 1788 mmc->preinit = preinit; 1789 } 1790 1791 static void do_preinit(void) 1792 { 1793 struct mmc *m; 1794 struct list_head *entry; 1795 1796 list_for_each(entry, &mmc_devices) { 1797 m = list_entry(entry, struct mmc, link); 1798 1799 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 1800 mmc_set_preinit(m, 1); 1801 #endif 1802 if (m->preinit) 1803 mmc_start_init(m); 1804 } 1805 } 1806 1807 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) 1808 static int mmc_probe(bd_t *bis) 1809 { 1810 return 0; 1811 } 1812 #elif defined(CONFIG_DM_MMC) 1813 static int mmc_probe(bd_t *bis) 1814 { 1815 int ret, i; 1816 struct uclass *uc; 1817 struct udevice *dev; 1818 1819 ret = uclass_get(UCLASS_MMC, &uc); 1820 if (ret) 1821 return ret; 1822 1823 /* 1824 * Try to add them in sequence order. Really with driver model we 1825 * should allow holes, but the current MMC list does not allow that. 1826 * So if we request 0, 1, 3 we will get 0, 1, 2. 1827 */ 1828 for (i = 0; ; i++) { 1829 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 1830 if (ret == -ENODEV) 1831 break; 1832 } 1833 uclass_foreach_dev(dev, uc) { 1834 ret = device_probe(dev); 1835 if (ret) 1836 printf("%s - probe failed: %d\n", dev->name, ret); 1837 } 1838 1839 return 0; 1840 } 1841 #else 1842 static int mmc_probe(bd_t *bis) 1843 { 1844 if (board_mmc_init(bis) < 0) 1845 cpu_mmc_init(bis); 1846 1847 return 0; 1848 } 1849 #endif 1850 1851 int mmc_initialize(bd_t *bis) 1852 { 1853 static int initialized = 0; 1854 int ret; 1855 if (initialized) /* Avoid initializing mmc multiple times */ 1856 return 0; 1857 initialized = 1; 1858 1859 INIT_LIST_HEAD (&mmc_devices); 1860 cur_dev_num = 0; 1861 1862 ret = mmc_probe(bis); 1863 if (ret) 1864 return ret; 1865 1866 #ifndef CONFIG_SPL_BUILD 1867 print_mmc_devices(','); 1868 #endif 1869 1870 do_preinit(); 1871 return 0; 1872 } 1873 1874 #ifdef CONFIG_SUPPORT_EMMC_BOOT 1875 /* 1876 * This function changes the size of boot partition and the size of rpmb 1877 * partition present on EMMC devices. 1878 * 1879 * Input Parameters: 1880 * struct *mmc: pointer for the mmc device strcuture 1881 * bootsize: size of boot partition 1882 * rpmbsize: size of rpmb partition 1883 * 1884 * Returns 0 on success. 1885 */ 1886 1887 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, 1888 unsigned long rpmbsize) 1889 { 1890 int err; 1891 struct mmc_cmd cmd; 1892 1893 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ 1894 cmd.cmdidx = MMC_CMD_RES_MAN; 1895 cmd.resp_type = MMC_RSP_R1b; 1896 cmd.cmdarg = MMC_CMD62_ARG1; 1897 1898 err = mmc_send_cmd(mmc, &cmd, NULL); 1899 if (err) { 1900 debug("mmc_boot_partition_size_change: Error1 = %d\n", err); 1901 return err; 1902 } 1903 1904 /* Boot partition changing mode */ 1905 cmd.cmdidx = MMC_CMD_RES_MAN; 1906 cmd.resp_type = MMC_RSP_R1b; 1907 cmd.cmdarg = MMC_CMD62_ARG2; 1908 1909 err = mmc_send_cmd(mmc, &cmd, NULL); 1910 if (err) { 1911 debug("mmc_boot_partition_size_change: Error2 = %d\n", err); 1912 return err; 1913 } 1914 /* boot partition size is multiple of 128KB */ 1915 bootsize = (bootsize * 1024) / 128; 1916 1917 /* Arg: boot partition size */ 1918 cmd.cmdidx = MMC_CMD_RES_MAN; 1919 cmd.resp_type = MMC_RSP_R1b; 1920 cmd.cmdarg = bootsize; 1921 1922 err = mmc_send_cmd(mmc, &cmd, NULL); 1923 if (err) { 1924 debug("mmc_boot_partition_size_change: Error3 = %d\n", err); 1925 return err; 1926 } 1927 /* RPMB partition size is multiple of 128KB */ 1928 rpmbsize = (rpmbsize * 1024) / 128; 1929 /* Arg: RPMB partition size */ 1930 cmd.cmdidx = MMC_CMD_RES_MAN; 1931 cmd.resp_type = MMC_RSP_R1b; 1932 cmd.cmdarg = rpmbsize; 1933 1934 err = mmc_send_cmd(mmc, &cmd, NULL); 1935 if (err) { 1936 debug("mmc_boot_partition_size_change: Error4 = %d\n", err); 1937 return err; 1938 } 1939 return 0; 1940 } 1941 1942 /* 1943 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH 1944 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH 1945 * and BOOT_MODE. 1946 * 1947 * Returns 0 on success. 1948 */ 1949 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) 1950 { 1951 int err; 1952 1953 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, 1954 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | 1955 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | 1956 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); 1957 1958 if (err) 1959 return err; 1960 return 0; 1961 } 1962 1963 /* 1964 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) 1965 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and 1966 * PARTITION_ACCESS. 1967 * 1968 * Returns 0 on success. 1969 */ 1970 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) 1971 { 1972 int err; 1973 1974 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 1975 EXT_CSD_BOOT_ACK(ack) | 1976 EXT_CSD_BOOT_PART_NUM(part_num) | 1977 EXT_CSD_PARTITION_ACCESS(access)); 1978 1979 if (err) 1980 return err; 1981 return 0; 1982 } 1983 1984 /* 1985 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value 1986 * for enable. Note that this is a write-once field for non-zero values. 1987 * 1988 * Returns 0 on success. 1989 */ 1990 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) 1991 { 1992 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, 1993 enable); 1994 } 1995 #endif 1996 1997 U_BOOT_LEGACY_BLK(mmc) = { 1998 .if_typename = "mmc", 1999 .if_type = IF_TYPE_MMC, 2000 .max_devs = -1, 2001 .get_dev = mmc_get_dev, 2002 .select_hwpart = mmc_select_hwpartp, 2003 }; 2004