1*83d290c5STom Rini // SPDX-License-Identifier: BSD-3-Clause
2230fe9b2SPavel Machek /*
3bd08ce8fSTien Fong Chee * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4230fe9b2SPavel Machek * All rights reserved.
5230fe9b2SPavel Machek */
6230fe9b2SPavel Machek
7230fe9b2SPavel Machek #include <common.h>
8230fe9b2SPavel Machek #include <asm/io.h>
91221ce45SMasahiro Yamada #include <linux/errno.h>
10230fe9b2SPavel Machek #include <asm/arch/fpga_manager.h>
11230fe9b2SPavel Machek #include <asm/arch/reset_manager.h>
12230fe9b2SPavel Machek #include <asm/arch/system_manager.h>
13230fe9b2SPavel Machek
14230fe9b2SPavel Machek /* Timeout count */
15230fe9b2SPavel Machek #define FPGA_TIMEOUT_CNT 0x1000000
16230fe9b2SPavel Machek
17230fe9b2SPavel Machek static struct socfpga_fpga_manager *fpgamgr_regs =
18230fe9b2SPavel Machek (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
19230fe9b2SPavel Machek
fpgamgr_dclkcnt_set(unsigned long cnt)206867e19aSTien Fong Chee int fpgamgr_dclkcnt_set(unsigned long cnt)
21230fe9b2SPavel Machek {
22230fe9b2SPavel Machek unsigned long i;
23230fe9b2SPavel Machek
24230fe9b2SPavel Machek /* Clear any existing done status */
25230fe9b2SPavel Machek if (readl(&fpgamgr_regs->dclkstat))
26230fe9b2SPavel Machek writel(0x1, &fpgamgr_regs->dclkstat);
27230fe9b2SPavel Machek
28230fe9b2SPavel Machek /* Write the dclkcnt */
29230fe9b2SPavel Machek writel(cnt, &fpgamgr_regs->dclkcnt);
30230fe9b2SPavel Machek
31230fe9b2SPavel Machek /* Wait till the dclkcnt done */
32230fe9b2SPavel Machek for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
33230fe9b2SPavel Machek if (!readl(&fpgamgr_regs->dclkstat))
34230fe9b2SPavel Machek continue;
35230fe9b2SPavel Machek
36230fe9b2SPavel Machek writel(0x1, &fpgamgr_regs->dclkstat);
37230fe9b2SPavel Machek return 0;
38230fe9b2SPavel Machek }
39230fe9b2SPavel Machek
40230fe9b2SPavel Machek return -ETIMEDOUT;
41230fe9b2SPavel Machek }
42230fe9b2SPavel Machek
43230fe9b2SPavel Machek /* Write the RBF data to FPGA Manager */
fpgamgr_program_write(const void * rbf_data,size_t rbf_size)446867e19aSTien Fong Chee void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
45230fe9b2SPavel Machek {
46230fe9b2SPavel Machek uint32_t src = (uint32_t)rbf_data;
47230fe9b2SPavel Machek uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
48230fe9b2SPavel Machek
49230fe9b2SPavel Machek /* Number of loops for 32-byte long copying. */
50230fe9b2SPavel Machek uint32_t loops32 = rbf_size / 32;
51230fe9b2SPavel Machek /* Number of loops for 4-byte long copying + trailing bytes */
52230fe9b2SPavel Machek uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
53230fe9b2SPavel Machek
54230fe9b2SPavel Machek asm volatile(
55bd08ce8fSTien Fong Chee " cmp %2, #0\n"
56bd08ce8fSTien Fong Chee " beq 2f\n"
57230fe9b2SPavel Machek "1: ldmia %0!, {r0-r7}\n"
58230fe9b2SPavel Machek " stmia %1!, {r0-r7}\n"
59230fe9b2SPavel Machek " sub %1, #32\n"
60230fe9b2SPavel Machek " subs %2, #1\n"
61230fe9b2SPavel Machek " bne 1b\n"
62bd08ce8fSTien Fong Chee "2: cmp %3, #0\n"
63bd08ce8fSTien Fong Chee " beq 4f\n"
64bd08ce8fSTien Fong Chee "3: ldr %2, [%0], #4\n"
65230fe9b2SPavel Machek " str %2, [%1]\n"
66230fe9b2SPavel Machek " subs %3, #1\n"
67bd08ce8fSTien Fong Chee " bne 3b\n"
68bd08ce8fSTien Fong Chee "4: nop\n"
69230fe9b2SPavel Machek : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
70230fe9b2SPavel Machek : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
71230fe9b2SPavel Machek }
72230fe9b2SPavel Machek
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