xref: /openbmc/u-boot/drivers/clk/aspeed/clk_ast2600.c (revision fd98b62831ed9249f1656f1760ddc354b2455eaa)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  */
5 
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <dm/lists.h>
11 #include <asm/arch/scu_ast2600.h>
12 #include <dt-bindings/clock/ast2600-clock.h>
13 #include <dt-bindings/reset/ast2600-reset.h>
14 
15 /*
16  * MAC Clock Delay settings, taken from Aspeed SDK
17  */
18 #define RGMII_TXCLK_ODLY	8
19 #define RMII_RXCLK_IDLY		2
20 
21 #define MAC_DEF_DELAY_1G	0x00410410
22 #define MAC_DEF_DELAY_100M	0x00410410
23 #define MAC_DEF_DELAY_10M	0x00410410
24 
25 #define MAC34_DEF_DELAY_1G	0x00104208
26 #define MAC34_DEF_DELAY_100M	0x00104208
27 #define MAC34_DEF_DELAY_10M	0x00104208
28 
29 /*
30  * TGMII Clock Duty constants, taken from Aspeed SDK
31  */
32 #define RGMII2_TXCK_DUTY	0x66
33 #define RGMII1_TXCK_DUTY	0x64
34 
35 #define D2PLL_DEFAULT_RATE	(250 * 1000 * 1000)
36 
37 DECLARE_GLOBAL_DATA_PTR;
38 
39 /*
40  * Clock divider/multiplier configuration struct.
41  * For H-PLL and M-PLL the formula is
42  * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
43  * M - Numerator
44  * N - Denumerator
45  * P - Post Divider
46  * They have the same layout in their control register.
47  *
48  * D-PLL and D2-PLL have extra divider (OD + 1), which is not
49  * yet needed and ignored by clock configurations.
50  */
51 union ast2600_pll_reg {
52 	unsigned int w;
53 	struct {
54 		unsigned int m : 13;		/* bit[12:0]	*/
55 		unsigned int n : 6;		/* bit[18:13]	*/
56 		unsigned int p : 4;		/* bit[22:19]	*/
57 		unsigned int off : 1;		/* bit[23]	*/
58 		unsigned int bypass : 1;	/* bit[24]	*/
59 		unsigned int reset : 1;		/* bit[25]	*/
60 		unsigned int reserved : 6;	/* bit[31:26]	*/
61 	} b;
62 };
63 
64 struct ast2600_pll_cfg {
65 	union ast2600_pll_reg reg;
66 	unsigned int ext_reg;
67 };
68 
69 struct ast2600_pll_desc {
70 	u32 in;
71 	u32 out;
72 	struct ast2600_pll_cfg cfg;
73 };
74 
75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = {
76     {.in = AST2600_CLK_IN, .out = 400000000,
77     .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1,
78     .cfg.ext_reg = 0x31,
79     },
80     {.in = AST2600_CLK_IN, .out = 200000000,
81     .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15,
82     .cfg.ext_reg = 0x3f
83     },
84     {.in = AST2600_CLK_IN, .out = 334000000,
85     .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9,
86     .cfg.ext_reg = 0x14d
87     },
88 
89     {.in = AST2600_CLK_IN, .out = 1000000000,
90     .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0,
91     .cfg.ext_reg = 0x3d
92     },
93 
94     {.in = AST2600_CLK_IN, .out = 50000000,
95     .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15,
96     .cfg.ext_reg = 0x31
97     },
98 };
99 
100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx)
101 {
102 	u32 clkin = AST2600_CLK_IN;
103 	u32 pll_reg = 0;
104 	unsigned int mult, div = 1;
105 
106 	switch(pll_idx) {
107 		case ASPEED_CLK_HPLL:
108 			pll_reg = readl(&scu->h_pll_param);
109 			break;
110 		case ASPEED_CLK_MPLL:
111 			pll_reg = readl(&scu->m_pll_param);
112 			break;
113 		case ASPEED_CLK_DPLL:
114 			pll_reg = readl(&scu->d_pll_param);
115 			break;
116 		case ASPEED_CLK_EPLL:
117 			pll_reg = readl(&scu->e_pll_param);
118 			break;
119 
120 	}
121 	if (pll_reg & BIT(24)) {
122 		/* Pass through mode */
123 		mult = div = 1;
124 	} else {
125 		/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
126 		union ast2600_pll_reg reg;
127 		reg.w = pll_reg;
128 		mult = (reg.b.m + 1) / (reg.b.n + 1);
129 		div = (reg.b.p + 1);
130 	}
131 	return ((clkin * mult)/div);
132 
133 }
134 
135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu)
136 {
137 	u32 clkin = AST2600_CLK_IN;
138 	u32 apll_reg = readl(&scu->a_pll_param);
139 	unsigned int mult, div = 1;
140 
141 	if (apll_reg & BIT(20)) {
142 		/* Pass through mode */
143 		mult = div = 1;
144 	} else {
145 		/* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
146 		u32 m = (apll_reg >> 5) & 0x3f;
147 		u32 od = (apll_reg >> 4) & 0x1;
148 		u32 n = apll_reg & 0xf;
149 
150 		mult = (2 - od) * (m + 2);
151 		div = n + 1;
152 	}
153 	return ((clkin * mult)/div);
154 }
155 
156 static u32 ast2600_a0_axi_ahb_div_table[] = {
157 	2, 2, 3, 5,
158 };
159 
160 static u32 ast2600_a1_axi_ahb_div_table[] = {
161 	4, 6, 2, 4,
162 };
163 
164 static u32 ast2600_get_hclk(struct ast2600_scu *scu)
165 {
166 	u32 hw_rev = readl(&scu->chip_id0);
167 	u32 hwstrap1 = readl(&scu->hwstrap1);
168 	u32 axi_div = 1;
169 	u32 ahb_div = 0;
170 	u32 rate = 0;
171 
172 	if(hwstrap1 & BIT(16))
173 		axi_div = 1;
174 	else
175 		axi_div = 2;
176 
177 	if (hw_rev & BIT(16))
178 		ahb_div = ast2600_a1_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3];
179 	else
180 		ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3];
181 
182 	rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
183 
184 	return (rate / axi_div / ahb_div);
185 }
186 
187 static u32 ast2600_hpll_pclk1_div_table[] = {
188 	4, 8, 12, 16, 20, 24, 28, 32,
189 };
190 
191 static u32 ast2600_hpll_pclk2_div_table[] = {
192 	2, 4, 6, 8, 10, 12, 14, 16,
193 };
194 
195 static u32 ast2600_get_pclk1(struct ast2600_scu *scu)
196 {
197 	u32 clk_sel1 = readl(&scu->clk_sel1);
198 	u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)];
199 	u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
200 
201 	return (rate / apb_div);
202 }
203 
204 static u32 ast2600_get_pclk2(struct ast2600_scu *scu)
205 {
206 	u32 clk_sel4 = readl(&scu->clk_sel4);
207 	u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)];
208 	u32 rate = ast2600_get_hclk(scu);
209 
210 	return (rate / apb_div);
211 }
212 
213 static u32 ast2600_get_uxclk_rate(struct ast2600_scu *scu)
214 {
215 	u32 clk_in = 0;
216 	u32 uxclk_sel = readl(&scu->clk_sel4);
217 
218 	uxclk_sel &= 0x3;
219 	switch(uxclk_sel) {
220 		case 0:
221 			clk_in = ast2600_get_apll_rate(scu) / 4;
222 			break;
223 		case 1:
224 			clk_in = ast2600_get_apll_rate(scu) / 2;
225 			break;
226 		case 2:
227 			clk_in = ast2600_get_apll_rate(scu);
228 			break;
229 		case 3:
230 			clk_in = ast2600_get_hclk(scu);
231 			break;
232 	}
233 
234 	return clk_in;
235 }
236 
237 static u32 ast2600_get_huxclk_rate(struct ast2600_scu *scu)
238 {
239 	u32 clk_in = 0;
240 	u32 huclk_sel = readl(&scu->clk_sel4);
241 
242 	huclk_sel = ((huclk_sel >> 3) & 0x3);
243 	switch(huclk_sel) {
244 		case 0:
245 			clk_in = ast2600_get_apll_rate(scu) / 4;
246 			break;
247 		case 1:
248 			clk_in = ast2600_get_apll_rate(scu) / 2;
249 			break;
250 		case 2:
251 			clk_in = ast2600_get_apll_rate(scu);
252 			break;
253 		case 3:
254 			clk_in = ast2600_get_hclk(scu);
255 			break;
256 	}
257 
258 	return clk_in;
259 }
260 
261 static u32 ast2600_get_uart_from_uxclk_rate(struct ast2600_scu *scu)
262 {
263 	u32 clk_in = ast2600_get_uxclk_rate(scu);
264 	u32 div_reg = readl(&scu->uart_24m_ref_uxclk);
265 	unsigned int mult, div;
266 
267 	u32 n = (div_reg >> 8) & 0x3ff;
268 	u32 r = div_reg & 0xff;
269 
270 	mult = r;
271 	div = (n * 4);
272 	return (clk_in * mult)/div;
273 }
274 
275 static u32 ast2600_get_uart_from_huxclk_rate(struct ast2600_scu *scu)
276 {
277 	u32 clk_in = ast2600_get_huxclk_rate(scu);
278 	u32 div_reg = readl(&scu->uart_24m_ref_huxclk);
279 
280 	unsigned int mult, div;
281 
282 	u32 n = (div_reg >> 8) & 0x3ff;
283 	u32 r = div_reg & 0xff;
284 
285 	mult = r;
286 	div = (n * 4);
287 	return (clk_in * mult)/div;
288 }
289 
290 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu)
291 {
292 	u32 clkin = 0;
293 	u32 clk_sel = readl(&scu->clk_sel4);
294 	u32 div = (clk_sel >> 28) & 0x7;
295 
296 	if(clk_sel & BIT(8)) {
297 		clkin = ast2600_get_apll_rate(scu);
298 	} else {
299 		clkin = ast2600_get_hclk(scu);
300 	}
301 	div = (div + 1) << 1;
302 
303 	return (clkin / div);
304 }
305 
306 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu)
307 {
308 	u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL);
309 	u32 clk_sel = readl(&scu->clk_sel1);
310 	u32 div = (clk_sel >> 12) & 0x7;
311 
312 	div = (div + 1) << 2;
313 
314 	return (clkin / div);
315 }
316 
317 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx)
318 {
319 	u32 uart_sel = readl(&scu->clk_sel4);
320 	u32 uart_sel5 = readl(&scu->clk_sel5);
321 	ulong uart_clk = 0;
322 
323 	switch(uart_idx) {
324 		case 1:
325 		case 2:
326 		case 3:
327 		case 4:
328 		case 6:
329 			if(uart_sel & BIT(uart_idx - 1))
330 				uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ;
331 			else
332 				uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ;
333 			break;
334 		case 5: //24mhz is come form usb phy 48Mhz
335 			{
336 			u8 uart5_clk_sel = 0;
337 			//high bit
338 			if (readl(&scu->misc_ctrl1) & BIT(12))
339 				uart5_clk_sel = 0x2;
340 			else
341 				uart5_clk_sel = 0x0;
342 
343 			if (readl(&scu->clk_sel2) & BIT(14))
344 				uart5_clk_sel |= 0x1;
345 
346 			switch(uart5_clk_sel) {
347 				case 0:
348 					uart_clk = 24000000;
349 					break;
350 				case 1:
351 					uart_clk = 0;
352 					break;
353 				case 2:
354 					uart_clk = 24000000/13;
355 					break;
356 				case 3:
357 					uart_clk = 192000000/13;
358 					break;
359 			}
360 			}
361 			break;
362 		case 7:
363 		case 8:
364 		case 9:
365 		case 10:
366 		case 11:
367 		case 12:
368 		case 13:
369 			if(uart_sel5 & BIT(uart_idx - 1))
370 				uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ;
371 			else
372 				uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ;
373 			break;
374 	}
375 
376 	return uart_clk;
377 }
378 
379 static ulong ast2600_clk_get_rate(struct clk *clk)
380 {
381 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
382 	ulong rate = 0;
383 
384 	switch (clk->id) {
385 	case ASPEED_CLK_HPLL:
386 	case ASPEED_CLK_EPLL:
387 	case ASPEED_CLK_DPLL:
388 	case ASPEED_CLK_MPLL:
389 		rate = ast2600_get_pll_rate(priv->scu, clk->id);
390 		break;
391 	case ASPEED_CLK_AHB:
392 		rate = ast2600_get_hclk(priv->scu);
393 		break;
394 	case ASPEED_CLK_APB1:
395 		rate = ast2600_get_pclk1(priv->scu);
396 		break;
397 	case ASPEED_CLK_APB2:
398 		rate = ast2600_get_pclk2(priv->scu);
399 		break;
400 	case ASPEED_CLK_APLL:
401 		rate = ast2600_get_apll_rate(priv->scu);
402 		break;
403 	case ASPEED_CLK_GATE_UART1CLK:
404 		rate = ast2600_get_uart_clk_rate(priv->scu, 1);
405 		break;
406 	case ASPEED_CLK_GATE_UART2CLK:
407 		rate = ast2600_get_uart_clk_rate(priv->scu, 2);
408 		break;
409 	case ASPEED_CLK_GATE_UART3CLK:
410 		rate = ast2600_get_uart_clk_rate(priv->scu, 3);
411 		break;
412 	case ASPEED_CLK_GATE_UART4CLK:
413 		rate = ast2600_get_uart_clk_rate(priv->scu, 4);
414 		break;
415 	case ASPEED_CLK_GATE_UART5CLK:
416 		rate = ast2600_get_uart_clk_rate(priv->scu, 5);
417 		break;
418 	case ASPEED_CLK_SDIO:
419 		rate = ast2600_get_sdio_clk_rate(priv->scu);
420 		break;
421 	case ASPEED_CLK_EMMC:
422 		rate = ast2600_get_emmc_clk_rate(priv->scu);
423 		break;
424 	default:
425 		pr_debug("can't get clk rate \n");
426 		return -ENOENT;
427 		break;
428 	}
429 
430 	return rate;
431 }
432 
433 /**
434  * @brief	lookup PLL divider config by input/output rate
435  * @param[in]	*pll - PLL descriptor
436  * @return	true - if PLL divider config is found, false - else
437  *
438  * The function caller shall fill "pll->in" and "pll->out", then this function
439  * will search the lookup table to find a valid PLL divider configuration.
440  */
441 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll)
442 {
443 	u32 i;
444 	bool is_found = false;
445 
446 	for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) {
447 		const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i];
448 		if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) {
449 			is_found = true;
450 			pll->cfg.reg.w = def_cfg->cfg.reg.w;
451 			pll->cfg.ext_reg = def_cfg->cfg.ext_reg;
452 			break;
453 		}
454 	}
455 	return is_found;
456 }
457 static u32 ast2600_configure_pll(struct ast2600_scu *scu,
458 				 struct ast2600_pll_cfg *p_cfg, int pll_idx)
459 {
460 	u32 addr, addr_ext;
461 	u32 reg;
462 
463 	switch (pll_idx) {
464 	case ASPEED_CLK_HPLL:
465 		addr = (u32)(&scu->h_pll_param);
466 		addr_ext = (u32)(&scu->h_pll_ext_param);
467 		break;
468 	case ASPEED_CLK_MPLL:
469 		addr = (u32)(&scu->m_pll_param);
470 		addr_ext = (u32)(&scu->m_pll_ext_param);
471 		break;
472 	case ASPEED_CLK_DPLL:
473 		addr = (u32)(&scu->d_pll_param);
474 		addr_ext = (u32)(&scu->d_pll_ext_param);
475 		break;
476 	case ASPEED_CLK_EPLL:
477 		addr = (u32)(&scu->e_pll_param);
478 		addr_ext = (u32)(&scu->e_pll_ext_param);
479 		break;
480 	default:
481 		debug("unknown PLL index\n");
482 		return 1;
483 	}
484 
485 	p_cfg->reg.b.bypass = 0;
486 	p_cfg->reg.b.off = 1;
487 	p_cfg->reg.b.reset = 1;
488 
489 	reg = readl(addr);
490 	reg &= ~GENMASK(25, 0);
491 	reg |= p_cfg->reg.w;
492 	writel(reg, addr);
493 
494 	/* write extend parameter */
495 	writel(p_cfg->ext_reg, addr_ext);
496 	udelay(100);
497 	p_cfg->reg.b.off = 0;
498 	p_cfg->reg.b.reset = 0;
499 	reg &= ~GENMASK(25, 0);
500 	reg |= p_cfg->reg.w;
501 	writel(reg, addr);
502 
503 	/* polling PLL lock status */
504 	while(0 == (readl(addr_ext) & BIT(31)));
505 
506 	return 0;
507 }
508 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)
509 {
510 	struct ast2600_pll_desc mpll;
511 
512 	mpll.in = AST2600_CLK_IN;
513 	mpll.out = rate;
514 	if (false == ast2600_search_clock_config(&mpll)) {
515 		printf("error!! unable to find valid DDR clock setting\n");
516 		return 0;
517 	}
518 	ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL);
519 
520 	return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);
521 }
522 
523 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)
524 {
525 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
526 
527 	ulong new_rate;
528 	switch (clk->id) {
529 	case ASPEED_CLK_MPLL:
530 		new_rate = ast2600_configure_ddr(priv->scu, rate);
531 		break;
532 	default:
533 		return -ENOENT;
534 	}
535 
536 	return new_rate;
537 }
538 
539 #define SCU_CLKSTOP_MAC1		(20)
540 #define SCU_CLKSTOP_MAC2		(21)
541 #define SCU_CLKSTOP_MAC3		(20)
542 #define SCU_CLKSTOP_MAC4		(21)
543 
544 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu)
545 {
546 	u32 clksel;
547 	u32 clkdelay;
548 
549 	struct ast2600_pll_desc epll;
550 
551 	epll.in = AST2600_CLK_IN;
552 	epll.out = 1000000000;
553 	if (false == ast2600_search_clock_config(&epll)) {
554 		printf(
555 		    "error!! unable to find valid ETHNET MAC clock setting\n");
556 		debug("%s: epll cfg = 0x%08x 0x%08x\n", __func__,
557 		      epll.cfg.reg.w, epll.cfg.ext_reg);
558 		debug("%s: epll cfg = %02x %02x %02x\n", __func__,
559 		      epll.cfg.reg.b.m, epll.cfg.reg.b.n, epll.cfg.reg.b.p);
560 		return 0;
561 	}
562 	ast2600_configure_pll(scu, &(epll.cfg), ASPEED_CLK_EPLL);
563 
564 	/* select MAC#1 and MAC#2 clock source = EPLL / 8 */
565 	clksel = readl(&scu->clk_sel2);
566 	clksel &= ~BIT(23);
567 	clksel |= 0x7 << 20;
568 	writel(clksel, &scu->clk_sel2);
569 
570 	/*
571 	BIT(31): select RGMII 125M from internal source
572 	BIT(28): RGMII 125M output enable
573 	BIT(25:0): 1G default delay
574 	*/
575 	clkdelay = MAC_DEF_DELAY_1G | BIT(31) | BIT(28);
576 	writel(clkdelay, &scu->mac12_clk_delay);
577 
578 	/* set 100M/10M default delay */
579 	writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M);
580 	writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M);
581 
582 	/* MAC AHB = HPLL / 6 */
583 	clksel = readl(&scu->clk_sel1);
584 	clksel &= ~GENMASK(18, 16);
585 	clksel |= 0x2 << 16;
586 	writel(clksel, &scu->clk_sel1);
587 
588 	return 0;
589 }
590 
591 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu)
592 {
593 	u32 reg;
594 
595 	ast2600_configure_mac12_clk(scu);
596 
597 	/*
598 	BIT[31]   RGMII 125M source: 0 = from IO pin
599 	BIT[25:0] MAC 1G delay
600 	*/
601 	reg = readl(&scu->mac34_clk_delay);
602 	reg &= ~(BIT(31) | GENMASK(25, 0));
603 	reg |= MAC34_DEF_DELAY_1G;
604 	writel(reg, &scu->mac34_clk_delay);
605 	writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M);
606 	writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M);
607 
608 	/* clock source seletion and divider */
609 	reg = readl(&scu->clk_sel4);
610 	reg &= ~GENMASK(26, 24);	/* MAC AHB = HCLK / 2 */
611 	reg &= ~GENMASK(18, 16);
612 	reg |= 0x3 << 16;		/* RMII 50M = SLICLK_200M / 4 */
613 	writel(reg, &scu->clk_sel4);
614 
615 	/* set driving strength */
616 	reg = readl(&scu->pinmux_ctrl16);
617 	reg &= GENMASK(3, 0);
618 	reg |= (0x2 << 0) | (0x2 << 2);
619 	writel(reg, &scu->pinmux_ctrl16);
620 
621 	return 0;
622 }
623 #if 0
624 /**
625  * ast2600 RGMII clock source tree
626  *
627  *    125M from external PAD -------->|\
628  *    HPLL -->|\                      | |---->RGMII 125M for MAC#1 & MAC#2
629  *            | |---->| divider |---->|/                             +
630  *    EPLL -->|/                                                     |
631  *                                                                   |
632  *    +---------<-----------|PAD output enable|<---------------------+
633  *    |
634  *    +--->|PAD input enable|----->|\
635  *                                 | |----> RGMII 125M for MAC#3 & MAC#4
636  *    SLICLK 200M -->|divider|---->|/
637  *
638  *
639  * ast2600 RMII/NCSI clock source tree
640  *
641  *    HPLL -->|\
642  *            | |---->| divider |----> RMII 50M for MAC#1 & MAC#2
643  *    EPLL -->|/
644  *
645  *    HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4
646 */
647 struct ast2600_rgmii_clk_config {
648 	u32 mac_1_2_src;	/* 0=external PAD, 1=internal PLL */
649 	u32 int_clk_src;	/* 0=EPLL, 1=HPLL */
650 	u32 int_clk_div;
651 
652 	u32 mac_3_4_src;	/* 0=external PAD, 1=SLICLK */
653 	u32 sli_clk_div;	/* reserved */
654 };
655 
656 static void ast2600_init_rgmii_clk(struct ast2600_scu *scu, int index)
657 {
658 	debug("%s not ready\n", __func__);
659 }
660 
661 static void ast2600_init_rmii_clk(struct ast2600_scu *scu, int index)
662 {
663 	debug("%s not ready\n", __func__);
664 }
665 #endif
666 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index)
667 {
668 	u32 reset_bit;
669 	u32 clkstop_bit;
670 
671 	if (index < 3)
672 		ast2600_configure_mac12_clk(scu);
673 	else
674 		ast2600_configure_mac34_clk(scu);
675 
676 	switch (index) {
677 	case 1:
678 		reset_bit = BIT(ASPEED_RESET_MAC1);
679 		clkstop_bit = BIT(SCU_CLKSTOP_MAC1);
680 		writel(reset_bit, &scu->sysreset_ctrl1);
681 		udelay(100);
682 		writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
683 		mdelay(10);
684 		writel(reset_bit, &scu->sysreset_clr_ctrl1);
685 
686 		break;
687 	case 2:
688 		reset_bit = BIT(ASPEED_RESET_MAC2);
689 		clkstop_bit = BIT(SCU_CLKSTOP_MAC2);
690 		writel(reset_bit, &scu->sysreset_ctrl1);
691 		udelay(100);
692 		writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
693 		mdelay(10);
694 		writel(reset_bit, &scu->sysreset_clr_ctrl1);
695 		break;
696 	case 3:
697 		reset_bit = BIT(ASPEED_RESET_MAC3 - 32);
698 		clkstop_bit = BIT(SCU_CLKSTOP_MAC3);
699 		writel(reset_bit, &scu->sysreset_ctrl2);
700 		udelay(100);
701 		writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
702 		mdelay(10);
703 		writel(reset_bit, &scu->sysreset_clr_ctrl2);
704 		break;
705 	case 4:
706 		reset_bit = BIT(ASPEED_RESET_MAC4 - 32);
707 		clkstop_bit = BIT(SCU_CLKSTOP_MAC4);
708 		writel(reset_bit, &scu->sysreset_ctrl2);
709 		udelay(100);
710 		writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
711 		mdelay(10);
712 		writel(reset_bit, &scu->sysreset_clr_ctrl2);
713 		break;
714 	default:
715 		return -EINVAL;
716 	}
717 
718 	return 0;
719 }
720 
721 #define SCU_CLKSTOP_SDIO 4
722 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu)
723 {
724 	u32 reset_bit;
725 	u32 clkstop_bit;
726 
727 	reset_bit = BIT(ASPEED_RESET_SD - 32);
728 	clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
729 
730 	writel(reset_bit, &scu->sysreset_clr_ctrl2);
731 	udelay(100);
732 	//enable clk
733 	writel(clkstop_bit, &scu->clk_stop_clr_ctrl2);
734 	mdelay(10);
735 	writel(reset_bit, &scu->sysreset_ctrl2);
736 
737 	return 0;
738 }
739 
740 #define SCU_CLKSTOP_EXTSD 31
741 #define SCU_CLK_SD_MASK				(0x7 << 28)
742 #define SCU_CLK_SD_DIV(x)			(x << 28)
743 
744 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu)
745 {
746 	u32 clk_sel = readl(&scu->clk_sel4);
747 	u32 enableclk_bit;
748 
749 	enableclk_bit = BIT(SCU_CLKSTOP_EXTSD);
750 
751 	//default use apll for clock source 800/2 = 400
752 	clk_sel &= ~SCU_CLK_SD_MASK;
753 	clk_sel |= SCU_CLK_SD_DIV(0) | BIT(8);
754 	writel(clk_sel, &scu->clk_sel4);
755 
756 	//enable clk
757 	setbits_le32(&scu->clk_sel4, enableclk_bit);
758 
759 	return 0;
760 }
761 
762 #define SCU_CLKSTOP_EMMC 27
763 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu)
764 {
765 	u32 reset_bit;
766 	u32 clkstop_bit;
767 
768 	reset_bit = BIT(ASPEED_RESET_EMMC);
769 	clkstop_bit = BIT(SCU_CLKSTOP_EMMC);
770 
771 	writel(reset_bit, &scu->sysreset_clr_ctrl1);
772 	udelay(100);
773 	//enable clk
774 	writel(clkstop_bit, &scu->clk_stop_clr_ctrl1);
775 	mdelay(10);
776 	writel(reset_bit, &scu->sysreset_ctrl2);
777 
778 	return 0;
779 }
780 
781 #define SCU_CLKSTOP_EXTEMMC 15
782 #define SCU_CLK_EMMC_MASK			(0x7 << 12)
783 #define SCU_CLK_EMMC_DIV(x)			(x << 12)
784 
785 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu)
786 {
787 	u32 clk_sel = readl(&scu->clk_sel1);
788 	u32 enableclk_bit;
789 
790 	enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC);
791 
792 	clk_sel &= ~SCU_CLK_SD_MASK;
793 	clk_sel |= SCU_CLK_SD_DIV(1);
794 	writel(clk_sel, &scu->clk_sel1);
795 
796 	//enable clk
797 	setbits_le32(&scu->clk_sel1, enableclk_bit);
798 
799 	return 0;
800 }
801 
802 static int ast2600_clk_enable(struct clk *clk)
803 {
804 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
805 
806 	switch (clk->id) {
807 		case ASPEED_CLK_GATE_MAC1CLK:
808 			ast2600_configure_mac(priv->scu, 1);
809 			break;
810 		case ASPEED_CLK_GATE_MAC2CLK:
811 			ast2600_configure_mac(priv->scu, 2);
812 			break;
813 		case ASPEED_CLK_GATE_MAC3CLK:
814 			ast2600_configure_mac(priv->scu, 3);
815 			break;
816 		case ASPEED_CLK_GATE_MAC4CLK:
817 			ast2600_configure_mac(priv->scu, 4);
818 			break;
819 		case ASPEED_CLK_GATE_SDCLK:
820 			ast2600_enable_sdclk(priv->scu);
821 			break;
822 		case ASPEED_CLK_GATE_SDEXTCLK:
823 			ast2600_enable_extsdclk(priv->scu);
824 			break;
825 		case ASPEED_CLK_GATE_EMMCCLK:
826 			ast2600_enable_emmcclk(priv->scu);
827 			break;
828 		case ASPEED_CLK_GATE_EMMCEXTCLK:
829 			ast2600_enable_extemmcclk(priv->scu);
830 			break;
831 		default:
832 			pr_debug("can't enable clk \n");
833 			return -ENOENT;
834 			break;
835 	}
836 
837 	return 0;
838 }
839 
840 struct clk_ops ast2600_clk_ops = {
841 	.get_rate = ast2600_clk_get_rate,
842 	.set_rate = ast2600_clk_set_rate,
843 	.enable = ast2600_clk_enable,
844 };
845 
846 static int ast2600_clk_probe(struct udevice *dev)
847 {
848 	struct ast2600_clk_priv *priv = dev_get_priv(dev);
849 
850 	priv->scu = devfdt_get_addr_ptr(dev);
851 	if (IS_ERR(priv->scu))
852 		return PTR_ERR(priv->scu);
853 
854 	return 0;
855 }
856 
857 static int ast2600_clk_bind(struct udevice *dev)
858 {
859 	int ret;
860 
861 	/* The reset driver does not have a device node, so bind it here */
862 	ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
863 	if (ret)
864 		debug("Warning: No reset driver: ret=%d\n", ret);
865 
866 	return 0;
867 }
868 
869 #if CONFIG_IS_ENABLED(CMD_CLK)
870 struct aspeed_clks {
871 	ulong id;
872 	const char *name;
873 };
874 
875 static struct aspeed_clks aspeed_clk_names[] = {
876 	{ ASPEED_CLK_HPLL, "hpll" },
877 	{ ASPEED_CLK_MPLL, "mpll" },
878 	{ ASPEED_CLK_APLL, "apll" },
879 	{ ASPEED_CLK_EPLL, "epll" },
880 	{ ASPEED_CLK_DPLL, "dpll" },
881 	{ ASPEED_CLK_AHB, "hclk" },
882 	{ ASPEED_CLK_APB1, "pclk1" },
883 	{ ASPEED_CLK_APB2, "pclk2" },
884 };
885 
886 int soc_clk_dump(void)
887 {
888 	struct udevice *dev;
889 	struct clk clk;
890 	unsigned long rate;
891 	int i, ret;
892 
893 	ret = uclass_get_device_by_driver(UCLASS_CLK,
894 					  DM_GET_DRIVER(aspeed_scu), &dev);
895 	if (ret)
896 		return ret;
897 
898 	printf("Clk\t\tHz\n");
899 
900 	for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) {
901 		clk.id = aspeed_clk_names[i].id;
902 		ret = clk_request(dev, &clk);
903 		if (ret < 0) {
904 			debug("%s clk_request() failed: %d\n", __func__, ret);
905 			continue;
906 		}
907 
908 		ret = clk_get_rate(&clk);
909 		rate = ret;
910 
911 		clk_free(&clk);
912 
913 		if (ret == -ENOTSUPP) {
914 			printf("clk ID %lu not supported yet\n",
915 			       aspeed_clk_names[i].id);
916 			continue;
917 		}
918 		if (ret < 0) {
919 			printf("%s %lu: get_rate err: %d\n",
920 			       __func__, aspeed_clk_names[i].id, ret);
921 			continue;
922 		}
923 
924 		printf("%s(%3lu):\t%lu\n",
925 		       aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate);
926 	}
927 
928 	return 0;
929 }
930 #endif
931 
932 static const struct udevice_id ast2600_clk_ids[] = {
933 	{ .compatible = "aspeed,ast2600-scu", },
934 	{ }
935 };
936 
937 U_BOOT_DRIVER(aspeed_scu) = {
938 	.name		= "aspeed_scu",
939 	.id		= UCLASS_CLK,
940 	.of_match	= ast2600_clk_ids,
941 	.priv_auto_alloc_size = sizeof(struct ast2600_clk_priv),
942 	.ops		= &ast2600_clk_ops,
943 	.bind		= ast2600_clk_bind,
944 	.probe		= ast2600_clk_probe,
945 };
946