1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <dm/lists.h> 12 #include <asm/arch/scu_ast2600.h> 13 #include <dt-bindings/clock/ast2600-clock.h> 14 #include <dt-bindings/reset/ast2600-reset.h> 15 16 /* 17 * MAC Clock Delay settings, taken from Aspeed SDK 18 */ 19 #define RGMII_TXCLK_ODLY 8 20 #define RMII_RXCLK_IDLY 2 21 22 /* 23 * TGMII Clock Duty constants, taken from Aspeed SDK 24 */ 25 #define RGMII2_TXCK_DUTY 0x66 26 #define RGMII1_TXCK_DUTY 0x64 27 28 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* 33 * Clock divider/multiplier configuration struct. 34 * For H-PLL and M-PLL the formula is 35 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 36 * M - Numerator 37 * N - Denumerator 38 * P - Post Divider 39 * They have the same layout in their control register. 40 * 41 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 42 * yet needed and ignored by clock configurations. 43 */ 44 struct ast2600_div_config { 45 unsigned int num; 46 unsigned int denum; 47 unsigned int post_div; 48 }; 49 50 /* 51 * Get the rate of the M-PLL clock from input clock frequency and 52 * the value of the M-PLL Parameter Register. 53 */ 54 extern u32 ast2600_get_mpll_rate(struct ast2600_scu *scu) 55 { 56 u32 clkin = AST2600_CLK_IN; 57 u32 mpll_reg = readl(&scu->m_pll_param); 58 unsigned int mult, div = 1; 59 60 if (mpll_reg & BIT(24)) { 61 /* Pass through mode */ 62 mult = div = 1; 63 } else { 64 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 65 u32 m = mpll_reg & 0x1fff; 66 u32 n = (mpll_reg >> 13) & 0x3f; 67 u32 p = (mpll_reg >> 19) & 0xf; 68 mult = (m + 1) / (n + 1); 69 div = (p + 1); 70 } 71 return ((clkin * mult)/div); 72 73 } 74 75 /* 76 * Get the rate of the H-PLL clock from input clock frequency and 77 * the value of the H-PLL Parameter Register. 78 */ 79 extern u32 ast2600_get_hpll_rate(struct ast2600_scu *scu) 80 { 81 u32 clkin = AST2600_CLK_IN; 82 u32 hpll_reg = readl(&scu->h_pll_param); 83 unsigned int mult, div = 1; 84 85 if (hpll_reg & BIT(24)) { 86 /* Pass through mode */ 87 mult = div = 1; 88 } else { 89 /* F = 25Mhz * [(M + 1) / (n + 1)] / (p + 1) */ 90 u32 m = (hpll_reg & 0x1fff); 91 u32 n = (hpll_reg >> 13) & 0x3f; 92 u32 p = (hpll_reg >> 19) & 0xf; 93 mult = (m + 1) / (n + 1); 94 div = (p + 1); 95 } 96 return ((clkin * mult)/div); 97 } 98 99 extern u32 ast2600_get_dpll_rate(struct ast2600_scu *scu) 100 { 101 u32 clk_in = AST2600_CLK_IN; 102 u32 dpll_reg = readl(&scu->d_pll_param); 103 unsigned int mult, div = 1; 104 105 if (dpll_reg & BIT(24)) { 106 /* Pass through mode */ 107 mult = div = 1; 108 } else { 109 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)*/ 110 u32 m = dpll_reg & 0x1fff; 111 u32 n = (dpll_reg >> 13) & 0x3f; 112 u32 p = (dpll_reg >> 19) & 0x7; 113 mult = ((m + 1) / (n + 1)); 114 div = (p + 1); 115 } 116 return (clk_in * mult)/div; 117 } 118 119 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 120 { 121 u32 clk_in = AST2600_CLK_IN; 122 u32 apll_reg = readl(&scu->a_pll_param); 123 unsigned int mult, div = 1; 124 125 if (apll_reg & BIT(20)) { 126 /* Pass through mode */ 127 mult = div = 1; 128 } else { 129 /* F = 25Mhz * (2-OD) * [(M + 2) / (n + 1)] */ 130 u32 m = (apll_reg >> 5) & 0x3f; 131 u32 od = (apll_reg >> 4) & 0x1; 132 u32 n = apll_reg & 0xf; 133 134 mult = (2 - od) * ((m + 2) / (n + 1)); 135 } 136 return (clk_in * mult)/div; 137 } 138 139 extern u32 ast2600_get_epll_rate(struct ast2600_scu *scu) 140 { 141 u32 clk_in = AST2600_CLK_IN; 142 u32 epll_reg = readl(&scu->e_pll_param); 143 unsigned int mult, div = 1; 144 145 if (epll_reg & BIT(24)) { 146 /* Pass through mode */ 147 mult = div = 1; 148 } else { 149 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)*/ 150 u32 m = epll_reg & 0x1fff; 151 u32 n = (epll_reg >> 13) & 0x3f; 152 u32 p = (epll_reg >> 19) & 0x7; 153 154 mult = ((m + 1) / (n + 1)); 155 div = (p + 1); 156 } 157 return (clk_in * mult)/div; 158 } 159 160 static u32 ast2600_a0_axi_ahb_div_table[] = { 161 2, 2, 3, 5, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div_table[] = { 165 4, 6, 2, 4, 166 }; 167 168 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 169 { 170 u32 hw_rev = readl(&scu->chip_id0); 171 u32 hwstrap1 = readl(&scu->hwstrap1); 172 u32 axi_div = 1; 173 u32 ahb_div = 0; 174 u32 rate = 0; 175 176 if((hwstrap1 >> 16) & 0x1) 177 axi_div = 1; 178 else 179 axi_div = 2; 180 181 if (hw_rev & BIT(16)) 182 ahb_div = ast2600_a1_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 183 else 184 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 185 186 rate = ast2600_get_hpll_rate(scu); 187 188 return (rate / axi_div / ahb_div); 189 } 190 191 static u32 ast2600_hpll_pclk_div_table[] = { 192 4, 8, 12, 16, 20, 24, 28, 32, 193 }; 194 195 static u32 ast2600_get_pclk(struct ast2600_scu *scu) 196 { 197 u32 clk_sel1 = readl(&scu->clk_sel1); 198 u32 apb_div = ast2600_hpll_pclk_div_table[((clk_sel1 >> 23) & 0x7)]; 199 u32 rate = ast2600_get_hpll_rate(scu); 200 201 return (rate / apb_div); 202 } 203 204 205 static u32 ast2600_get_uxclk_rate(struct ast2600_scu *scu) 206 { 207 u32 clk_in = 0; 208 u32 uxclk_sel = readl(&scu->clk_sel4); 209 210 uxclk_sel &= 0x3; 211 switch(uxclk_sel) { 212 case 0: 213 clk_in = ast2600_get_apll_rate(scu) / 4; 214 break; 215 case 1: 216 clk_in = ast2600_get_apll_rate(scu) / 2; 217 break; 218 case 2: 219 clk_in = ast2600_get_apll_rate(scu); 220 break; 221 case 3: 222 clk_in = ast2600_get_hclk(scu); 223 break; 224 } 225 226 return clk_in; 227 } 228 229 static u32 ast2600_get_huxclk_rate(struct ast2600_scu *scu) 230 { 231 u32 clk_in = 0; 232 u32 huclk_sel = readl(&scu->clk_sel4); 233 234 huclk_sel = ((huclk_sel >> 3) & 0x3); 235 switch(huclk_sel) { 236 case 0: 237 clk_in = ast2600_get_apll_rate(scu) / 4; 238 break; 239 case 1: 240 clk_in = ast2600_get_apll_rate(scu) / 2; 241 break; 242 case 2: 243 clk_in = ast2600_get_apll_rate(scu); 244 break; 245 case 3: 246 clk_in = ast2600_get_hclk(scu); 247 break; 248 } 249 250 return clk_in; 251 } 252 253 static u32 ast2600_get_uart_from_uxclk_rate(struct ast2600_scu *scu) 254 { 255 u32 clk_in = ast2600_get_uxclk_rate(scu); 256 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 257 unsigned int mult, div; 258 259 u32 n = (div_reg >> 8) & 0x3ff; 260 u32 r = div_reg & 0xff; 261 262 mult = r; 263 div = (n * 4); 264 return (clk_in * mult)/div; 265 } 266 267 static u32 ast2600_get_uart_from_huxclk_rate(struct ast2600_scu *scu) 268 { 269 u32 clk_in = ast2600_get_huxclk_rate(scu); 270 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 271 272 unsigned int mult, div; 273 274 u32 n = (div_reg >> 8) & 0x3ff; 275 u32 r = div_reg & 0xff; 276 277 mult = r; 278 div = (n * 4); 279 return (clk_in * mult)/div; 280 } 281 282 static ulong ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 283 { 284 u32 uart_sel = readl(&scu->clk_sel4); 285 u32 uart_sel5 = readl(&scu->clk_sel5); 286 ulong uart_clk = 0; 287 288 switch(uart_idx) { 289 case 1: 290 case 2: 291 case 3: 292 case 4: 293 case 6: 294 if(uart_sel & BIT(uart_idx - 1)) 295 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 296 else 297 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 298 break; 299 case 5: //24mhz is come form usb phy 48Mhz 300 { 301 u8 uart5_clk_sel = 0; 302 //high bit 303 if (readl(&scu->misc_ctrl1) & BIT(12)) 304 uart5_clk_sel = 0x2; 305 else 306 uart5_clk_sel = 0x0; 307 308 if (readl(&scu->clk_sel2) & BIT(14)) 309 uart5_clk_sel |= 0x1; 310 311 switch(uart5_clk_sel) { 312 case 0: 313 uart_clk = 24000000; 314 break; 315 case 1: 316 uart_clk = 0; 317 break; 318 case 2: 319 uart_clk = 24000000/13; 320 break; 321 case 3: 322 uart_clk = 192000000/13; 323 break; 324 } 325 } 326 break; 327 case 7: 328 case 8: 329 case 9: 330 case 10: 331 case 11: 332 case 12: 333 case 13: 334 if(uart_sel5 & BIT(uart_idx - 1)) 335 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 336 else 337 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 338 break; 339 } 340 341 return uart_clk; 342 } 343 344 static ulong ast2600_clk_get_rate(struct clk *clk) 345 { 346 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 347 ulong rate = 0; 348 349 switch (clk->id) { 350 case ASPEED_CLK_HPLL: 351 rate = ast2600_get_hpll_rate(priv->scu); 352 break; 353 case ASPEED_CLK_MPLL: 354 rate = ast2600_get_mpll_rate(priv->scu); 355 break; 356 case ASPEED_CLK_AHB: 357 rate = ast2600_get_hclk(priv->scu); 358 break; 359 case ASPEED_CLK_APB: 360 rate = ast2600_get_pclk(priv->scu); 361 break; 362 case ASPEED_CLK_GATE_UART1CLK: 363 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 364 break; 365 case ASPEED_CLK_GATE_UART2CLK: 366 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 367 break; 368 case ASPEED_CLK_GATE_UART3CLK: 369 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 370 break; 371 case ASPEED_CLK_GATE_UART4CLK: 372 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 373 break; 374 case ASPEED_CLK_GATE_UART5CLK: 375 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 376 break; 377 default: 378 pr_debug("can't get clk rate \n"); 379 return -ENOENT; 380 break; 381 } 382 383 return rate; 384 } 385 386 struct aspeed_clock_config { 387 ulong input_rate; 388 ulong rate; 389 struct ast2600_div_config cfg; 390 }; 391 392 static const struct aspeed_clock_config aspeed_clock_config_defaults[] = { 393 { 25000000, 400000000, { .num = 95, .denum = 2, .post_div = 1 } }, 394 }; 395 396 static bool aspeed_get_clock_config_default(ulong input_rate, 397 ulong requested_rate, 398 struct ast2600_div_config *cfg) 399 { 400 int i; 401 402 for (i = 0; i < ARRAY_SIZE(aspeed_clock_config_defaults); i++) { 403 const struct aspeed_clock_config *default_cfg = 404 &aspeed_clock_config_defaults[i]; 405 if (default_cfg->input_rate == input_rate && 406 default_cfg->rate == requested_rate) { 407 *cfg = default_cfg->cfg; 408 return true; 409 } 410 } 411 412 return false; 413 } 414 415 /* 416 * @input_rate - the rate of input clock in Hz 417 * @requested_rate - desired output rate in Hz 418 * @div - this is an IN/OUT parameter, at input all fields of the config 419 * need to be set to their maximum allowed values. 420 * The result (the best config we could find), would also be returned 421 * in this structure. 422 * 423 * @return The clock rate, when the resulting div_config is used. 424 */ 425 static ulong aspeed_calc_clock_config(ulong input_rate, ulong requested_rate, 426 struct ast2600_div_config *cfg) 427 { 428 /* 429 * The assumption is that kHz precision is good enough and 430 * also enough to avoid overflow when multiplying. 431 */ 432 const ulong input_rate_khz = input_rate / 1000; 433 const ulong rate_khz = requested_rate / 1000; 434 const struct ast2600_div_config max_vals = *cfg; 435 struct ast2600_div_config it = { 0, 0, 0 }; 436 ulong delta = rate_khz; 437 ulong new_rate_khz = 0; 438 439 /* 440 * Look for a well known frequency first. 441 */ 442 if (aspeed_get_clock_config_default(input_rate, requested_rate, cfg)) 443 return requested_rate; 444 445 for (; it.denum <= max_vals.denum; ++it.denum) { 446 for (it.post_div = 0; it.post_div <= max_vals.post_div; 447 ++it.post_div) { 448 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 449 * (it.denum + 1); 450 if (it.num > max_vals.num) 451 continue; 452 453 new_rate_khz = (input_rate_khz 454 * ((it.num + 1) / (it.denum + 1))) 455 / (it.post_div + 1); 456 457 /* Keep the rate below requested one. */ 458 if (new_rate_khz > rate_khz) 459 continue; 460 461 if (new_rate_khz - rate_khz < delta) { 462 delta = new_rate_khz - rate_khz; 463 *cfg = it; 464 if (delta == 0) 465 return new_rate_khz * 1000; 466 } 467 } 468 } 469 470 return new_rate_khz * 1000; 471 } 472 473 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 474 { 475 u32 clkin = AST2600_CLK_IN; 476 u32 mpll_reg; 477 struct ast2600_div_config div_cfg = { 478 .num = 0x1fff, /* SCU220 bit[12:0] */ 479 .denum = 0x3f, /* SCU220 bit[18:13] */ 480 .post_div = 0xf, /* SCU220 bit[22:19] */ 481 }; 482 483 aspeed_calc_clock_config(clkin, rate, &div_cfg); 484 485 mpll_reg = readl(&scu->m_pll_param); 486 mpll_reg &= ~0x7fffff; 487 mpll_reg |= (div_cfg.post_div << 19) 488 | (div_cfg.denum << 13) 489 | (div_cfg.num << 0); 490 491 writel(mpll_reg, &scu->m_pll_param); 492 493 return ast2600_get_mpll_rate(scu); 494 } 495 496 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 497 { 498 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 499 500 ulong new_rate; 501 switch (clk->id) { 502 case ASPEED_CLK_MPLL: 503 new_rate = ast2600_configure_ddr(priv->scu, rate); 504 break; 505 default: 506 return -ENOENT; 507 } 508 509 return new_rate; 510 } 511 512 #define SCU_CLKSTOP_MAC1 (20) 513 #define SCU_CLKSTOP_MAC2 (21) 514 #define SCU_CLKSTOP_MAC3 (20) 515 #define SCU_CLKSTOP_MAC4 (21) 516 517 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 518 { 519 u32 reset_bit; 520 u32 clkstop_bit; 521 522 523 switch (index) { 524 case 1: 525 reset_bit = BIT(ASPEED_RESET_MAC1); 526 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 527 writel(reset_bit, &scu->sysreset_ctrl1); 528 udelay(100); 529 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 530 mdelay(10); 531 writel(reset_bit, &scu->sysreset_clr_ctrl1); 532 533 break; 534 case 2: 535 reset_bit = BIT(ASPEED_RESET_MAC2); 536 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 537 writel(reset_bit, &scu->sysreset_ctrl1); 538 udelay(100); 539 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 540 mdelay(10); 541 writel(reset_bit, &scu->sysreset_clr_ctrl1); 542 break; 543 case 3: 544 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 545 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 546 writel(reset_bit, &scu->sysreset_ctrl2); 547 udelay(100); 548 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 549 mdelay(10); 550 writel(reset_bit, &scu->sysreset_clr_ctrl2); 551 break; 552 case 4: 553 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 554 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 555 writel(reset_bit, &scu->sysreset_ctrl2); 556 udelay(100); 557 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 558 mdelay(10); 559 writel(reset_bit, &scu->sysreset_clr_ctrl2); 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 return 0; 566 } 567 568 static int ast2600_clk_enable(struct clk *clk) 569 { 570 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 571 572 switch (clk->id) { 573 case ASPEED_CLK_GATE_MAC1CLK: 574 ast2600_configure_mac(priv->scu, 1); 575 break; 576 case ASPEED_CLK_GATE_MAC2CLK: 577 ast2600_configure_mac(priv->scu, 2); 578 break; 579 case ASPEED_CLK_GATE_MAC3CLK: 580 ast2600_configure_mac(priv->scu, 3); 581 break; 582 case ASPEED_CLK_GATE_MAC4CLK: 583 ast2600_configure_mac(priv->scu, 4); 584 break; 585 default: 586 pr_debug("can't enable clk \n"); 587 return -ENOENT; 588 break; 589 } 590 591 return 0; 592 } 593 594 struct clk_ops ast2600_clk_ops = { 595 .get_rate = ast2600_clk_get_rate, 596 .set_rate = ast2600_clk_set_rate, 597 .enable = ast2600_clk_enable, 598 }; 599 600 static int ast2600_clk_probe(struct udevice *dev) 601 { 602 struct ast2600_clk_priv *priv = dev_get_priv(dev); 603 604 priv->scu = devfdt_get_addr_ptr(dev); 605 if (IS_ERR(priv->scu)) 606 return PTR_ERR(priv->scu); 607 608 return 0; 609 } 610 611 static int ast2600_clk_bind(struct udevice *dev) 612 { 613 int ret; 614 615 /* The reset driver does not have a device node, so bind it here */ 616 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 617 if (ret) 618 debug("Warning: No reset driver: ret=%d\n", ret); 619 620 return 0; 621 } 622 623 static const struct udevice_id ast2600_clk_ids[] = { 624 { .compatible = "aspeed,ast2600-scu", }, 625 { } 626 }; 627 628 U_BOOT_DRIVER(aspeed_scu) = { 629 .name = "aspeed_scu", 630 .id = UCLASS_CLK, 631 .of_match = ast2600_clk_ids, 632 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 633 .ops = &ast2600_clk_ops, 634 .bind = ast2600_clk_bind, 635 .probe = ast2600_clk_probe, 636 }; 637