1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <dm/lists.h> 12 #include <asm/arch/scu_ast2600.h> 13 #include <dt-bindings/clock/ast2600-clock.h> 14 #include <dt-bindings/reset/ast2600-reset.h> 15 16 /* 17 * MAC Clock Delay settings, taken from Aspeed SDK 18 */ 19 #define RGMII_TXCLK_ODLY 8 20 #define RMII_RXCLK_IDLY 2 21 22 /* 23 * TGMII Clock Duty constants, taken from Aspeed SDK 24 */ 25 #define RGMII2_TXCK_DUTY 0x66 26 #define RGMII1_TXCK_DUTY 0x64 27 28 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* 33 * Clock divider/multiplier configuration struct. 34 * For H-PLL and M-PLL the formula is 35 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 36 * M - Numerator 37 * N - Denumerator 38 * P - Post Divider 39 * They have the same layout in their control register. 40 * 41 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 42 * yet needed and ignored by clock configurations. 43 */ 44 struct ast2600_div_config { 45 unsigned int num; 46 unsigned int denum; 47 unsigned int post_div; 48 }; 49 50 /* 51 * Get the rate of the M-PLL clock from input clock frequency and 52 * the value of the M-PLL Parameter Register. 53 */ 54 extern u32 ast2600_get_mpll_rate(struct ast2600_scu *scu) 55 { 56 u32 clkin = AST2600_CLK_IN; 57 u32 mpll_reg = readl(&scu->m_pll_param); 58 unsigned int mult, div = 1; 59 60 if (mpll_reg & BIT(24)) { 61 /* Pass through mode */ 62 mult = div = 1; 63 } else { 64 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 65 u32 m = mpll_reg & 0x1fff; 66 u32 n = (mpll_reg >> 13) & 0x3f; 67 u32 p = (mpll_reg >> 19) & 0xf; 68 mult = (m + 1) / (n + 1); 69 div = (p + 1); 70 } 71 return ((clkin * mult)/div); 72 73 } 74 75 /* 76 * Get the rate of the H-PLL clock from input clock frequency and 77 * the value of the H-PLL Parameter Register. 78 */ 79 extern u32 ast2600_get_hpll_rate(struct ast2600_scu *scu) 80 { 81 u32 clkin = AST2600_CLK_IN; 82 u32 hpll_reg = readl(&scu->h_pll_param); 83 unsigned int mult, div = 1; 84 85 if (hpll_reg & BIT(24)) { 86 /* Pass through mode */ 87 mult = div = 1; 88 } else { 89 /* F = 25Mhz * [(M + 1) / (n + 1)] / (p + 1) */ 90 u32 m = (hpll_reg & 0x1fff); 91 u32 n = (hpll_reg >> 13) & 0x3f; 92 u32 p = (hpll_reg >> 19) & 0xf; 93 mult = (m + 1) / (n + 1); 94 div = (p + 1); 95 } 96 return ((clkin * mult)/div); 97 } 98 99 extern u32 ast2600_get_dpll_rate(struct ast2600_scu *scu) 100 { 101 u32 clk_in = AST2600_CLK_IN; 102 u32 dpll_reg = readl(&scu->d_pll_param); 103 unsigned int mult, div = 1; 104 105 if (dpll_reg & BIT(24)) { 106 /* Pass through mode */ 107 mult = div = 1; 108 } else { 109 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)*/ 110 u32 m = dpll_reg & 0x1fff; 111 u32 n = (dpll_reg >> 13) & 0x3f; 112 u32 p = (dpll_reg >> 19) & 0x7; 113 mult = ((m + 1) / (n + 1)); 114 div = (p + 1); 115 } 116 return (clk_in * mult)/div; 117 } 118 119 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 120 { 121 u32 clk_in = AST2600_CLK_IN; 122 u32 apll_reg = readl(&scu->a_pll_param); 123 unsigned int mult, div = 1; 124 125 if (apll_reg & BIT(20)) { 126 /* Pass through mode */ 127 mult = div = 1; 128 } else { 129 /* F = 25Mhz * (2-OD) * [(M + 2) / (n + 1)] */ 130 u32 m = (apll_reg >> 5) & 0x3f; 131 u32 od = (apll_reg >> 4) & 0x1; 132 u32 n = apll_reg & 0xf; 133 134 mult = (2 - od) * ((m + 2) / (n + 1)); 135 } 136 return (clk_in * mult)/div; 137 } 138 139 extern u32 ast2600_get_epll_rate(struct ast2600_scu *scu) 140 { 141 u32 clk_in = AST2600_CLK_IN; 142 u32 epll_reg = readl(&scu->e_pll_param); 143 unsigned int mult, div = 1; 144 145 if (epll_reg & BIT(24)) { 146 /* Pass through mode */ 147 mult = div = 1; 148 } else { 149 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1)*/ 150 u32 m = epll_reg & 0x1fff; 151 u32 n = (epll_reg >> 13) & 0x3f; 152 u32 p = (epll_reg >> 19) & 0x7; 153 154 mult = ((m + 1) / (n + 1)); 155 div = (p + 1); 156 } 157 return (clk_in * mult)/div; 158 } 159 160 static u32 ast2600_a0_axi_ahb_div_table[] = { 161 2, 2, 3, 5, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div_table[] = { 165 4, 6, 2, 4, 166 }; 167 168 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 169 { 170 u32 hw_rev = readl(&scu->chip_id0); 171 u32 hwstrap1 = readl(&scu->hwstrap1); 172 u32 axi_div = 1; 173 u32 ahb_div = 0; 174 u32 rate = 0; 175 176 if((hwstrap1 >> 16) & 0x1) 177 axi_div = 1; 178 else 179 axi_div = 2; 180 181 if (hw_rev & BIT(16)) 182 ahb_div = ast2600_a1_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 183 else 184 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 185 186 rate = ast2600_get_hpll_rate(scu); 187 rate = rate / axi_div / ahb_div; 188 189 return rate; 190 } 191 192 193 static u32 ast2600_get_uxclk_rate(struct ast2600_scu *scu) 194 { 195 u32 clk_in = 0; 196 u32 uxclk_sel = readl(&scu->clk_sel4); 197 198 uxclk_sel &= 0x3; 199 switch(uxclk_sel) { 200 case 0: 201 clk_in = ast2600_get_apll_rate(scu) / 4; 202 break; 203 case 1: 204 clk_in = ast2600_get_apll_rate(scu) / 2; 205 break; 206 case 2: 207 clk_in = ast2600_get_apll_rate(scu); 208 break; 209 case 3: 210 clk_in = ast2600_get_hclk(scu); 211 break; 212 } 213 214 return clk_in; 215 } 216 217 static u32 ast2600_get_huxclk_rate(struct ast2600_scu *scu) 218 { 219 u32 clk_in = 0; 220 u32 huclk_sel = readl(&scu->clk_sel4); 221 222 huclk_sel = ((huclk_sel >> 3) & 0x3); 223 switch(huclk_sel) { 224 case 0: 225 clk_in = ast2600_get_apll_rate(scu) / 4; 226 break; 227 case 1: 228 clk_in = ast2600_get_apll_rate(scu) / 2; 229 break; 230 case 2: 231 clk_in = ast2600_get_apll_rate(scu); 232 break; 233 case 3: 234 clk_in = ast2600_get_hclk(scu); 235 break; 236 } 237 238 return clk_in; 239 } 240 241 static u32 ast2600_get_uart_from_uxclk_rate(struct ast2600_scu *scu) 242 { 243 u32 clk_in = ast2600_get_uxclk_rate(scu); 244 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 245 unsigned int mult, div; 246 247 u32 n = (div_reg >> 8) & 0x3ff; 248 u32 r = div_reg & 0xff; 249 250 mult = r; 251 div = (n * 4); 252 return (clk_in * mult)/div; 253 } 254 255 static u32 ast2600_get_uart_from_huxclk_rate(struct ast2600_scu *scu) 256 { 257 u32 clk_in = ast2600_get_huxclk_rate(scu); 258 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 259 260 unsigned int mult, div; 261 262 u32 n = (div_reg >> 8) & 0x3ff; 263 u32 r = div_reg & 0xff; 264 265 mult = r; 266 div = (n * 4); 267 return (clk_in * mult)/div; 268 } 269 270 static ulong ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 271 { 272 u32 uart_sel = readl(&scu->clk_sel4); 273 u32 uart_sel5 = readl(&scu->clk_sel5); 274 ulong uart_clk = 0; 275 276 switch(uart_idx) { 277 case 1: 278 case 2: 279 case 3: 280 case 4: 281 case 6: 282 if(uart_sel & BIT(uart_idx - 1)) 283 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 284 else 285 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 286 break; 287 case 5: //24mhz is come form usb phy 48Mhz 288 { 289 u8 uart5_clk_sel = 0; 290 //high bit 291 if (readl(&scu->misc_ctrl1) & BIT(12)) 292 uart5_clk_sel = 0x2; 293 else 294 uart5_clk_sel = 0x0; 295 296 if (readl(&scu->clk_sel2) & BIT(14)) 297 uart5_clk_sel |= 0x1; 298 299 switch(uart5_clk_sel) { 300 case 0: 301 uart_clk = 24000000; 302 break; 303 case 1: 304 uart_clk = 0; 305 break; 306 case 2: 307 uart_clk = 24000000/13; 308 break; 309 case 3: 310 uart_clk = 192000000/13; 311 break; 312 } 313 } 314 break; 315 case 7: 316 case 8: 317 case 9: 318 case 10: 319 case 11: 320 case 12: 321 case 13: 322 if(uart_sel5 & BIT(uart_idx - 1)) 323 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 324 else 325 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 326 break; 327 } 328 329 return uart_clk; 330 } 331 332 static u32 ast2600_hpll_pclk_div_table[] = { 333 4, 8, 12, 16, 20, 24, 28, 32, 334 }; 335 static ulong ast2600_clk_get_rate(struct clk *clk) 336 { 337 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 338 ulong rate = 0; 339 340 switch (clk->id) { 341 case ASPEED_CLK_HPLL: 342 rate = ast2600_get_hpll_rate(priv->scu); 343 break; 344 case ASPEED_CLK_MPLL: 345 rate = ast2600_get_mpll_rate(priv->scu); 346 break; 347 //HCLK 348 case ASPEED_CLK_AHB: 349 rate = ast2600_get_hclk(priv->scu); 350 break; 351 //pclk 352 case ASPEED_CLK_APB: 353 { 354 u32 clk_sel1 = readl(&priv->scu->clk_sel1); 355 u32 apb_div = ast2600_hpll_pclk_div_table[((clk_sel1 >> 23) & 0x7)]; 356 rate = ast2600_get_hpll_rate(priv->scu); 357 rate = rate / apb_div; 358 } 359 break; 360 case ASPEED_CLK_GATE_UART1CLK: 361 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 362 break; 363 case ASPEED_CLK_GATE_UART2CLK: 364 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 365 break; 366 case ASPEED_CLK_GATE_UART3CLK: 367 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 368 break; 369 case ASPEED_CLK_GATE_UART4CLK: 370 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 371 break; 372 case ASPEED_CLK_GATE_UART5CLK: 373 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 374 break; 375 default: 376 pr_debug("can't get clk rate \n"); 377 return -ENOENT; 378 break; 379 } 380 381 return rate; 382 } 383 384 struct aspeed_clock_config { 385 ulong input_rate; 386 ulong rate; 387 struct ast2600_div_config cfg; 388 }; 389 390 static const struct aspeed_clock_config aspeed_clock_config_defaults[] = { 391 { 25000000, 400000000, { .num = 95, .denum = 2, .post_div = 1 } }, 392 }; 393 394 static bool aspeed_get_clock_config_default(ulong input_rate, 395 ulong requested_rate, 396 struct ast2600_div_config *cfg) 397 { 398 int i; 399 400 for (i = 0; i < ARRAY_SIZE(aspeed_clock_config_defaults); i++) { 401 const struct aspeed_clock_config *default_cfg = 402 &aspeed_clock_config_defaults[i]; 403 if (default_cfg->input_rate == input_rate && 404 default_cfg->rate == requested_rate) { 405 *cfg = default_cfg->cfg; 406 return true; 407 } 408 } 409 410 return false; 411 } 412 413 /* 414 * @input_rate - the rate of input clock in Hz 415 * @requested_rate - desired output rate in Hz 416 * @div - this is an IN/OUT parameter, at input all fields of the config 417 * need to be set to their maximum allowed values. 418 * The result (the best config we could find), would also be returned 419 * in this structure. 420 * 421 * @return The clock rate, when the resulting div_config is used. 422 */ 423 static ulong aspeed_calc_clock_config(ulong input_rate, ulong requested_rate, 424 struct ast2600_div_config *cfg) 425 { 426 /* 427 * The assumption is that kHz precision is good enough and 428 * also enough to avoid overflow when multiplying. 429 */ 430 const ulong input_rate_khz = input_rate / 1000; 431 const ulong rate_khz = requested_rate / 1000; 432 const struct ast2600_div_config max_vals = *cfg; 433 struct ast2600_div_config it = { 0, 0, 0 }; 434 ulong delta = rate_khz; 435 ulong new_rate_khz = 0; 436 437 /* 438 * Look for a well known frequency first. 439 */ 440 if (aspeed_get_clock_config_default(input_rate, requested_rate, cfg)) 441 return requested_rate; 442 443 for (; it.denum <= max_vals.denum; ++it.denum) { 444 for (it.post_div = 0; it.post_div <= max_vals.post_div; 445 ++it.post_div) { 446 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 447 * (it.denum + 1); 448 if (it.num > max_vals.num) 449 continue; 450 451 new_rate_khz = (input_rate_khz 452 * ((it.num + 1) / (it.denum + 1))) 453 / (it.post_div + 1); 454 455 /* Keep the rate below requested one. */ 456 if (new_rate_khz > rate_khz) 457 continue; 458 459 if (new_rate_khz - rate_khz < delta) { 460 delta = new_rate_khz - rate_khz; 461 *cfg = it; 462 if (delta == 0) 463 return new_rate_khz * 1000; 464 } 465 } 466 } 467 468 return new_rate_khz * 1000; 469 } 470 471 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 472 { 473 u32 clkin = AST2600_CLK_IN; 474 u32 mpll_reg; 475 struct ast2600_div_config div_cfg = { 476 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 477 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 478 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 479 }; 480 481 aspeed_calc_clock_config(clkin, rate, &div_cfg); 482 483 mpll_reg = readl(&scu->m_pll_param); 484 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 485 | SCU_MPLL_DENUM_MASK); 486 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 487 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 488 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 489 490 writel(mpll_reg, &scu->m_pll_param); 491 492 return ast2600_get_mpll_rate(scu); 493 } 494 495 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 496 { 497 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 498 499 ulong new_rate; 500 switch (clk->id) { 501 case ASPEED_CLK_MPLL: 502 new_rate = ast2600_configure_ddr(priv->scu, rate); 503 break; 504 default: 505 return -ENOENT; 506 } 507 508 return new_rate; 509 } 510 511 #define SCU_CLKSTOP_MAC1 (20) 512 #define SCU_CLKSTOP_MAC2 (21) 513 #define SCU_CLKSTOP_MAC3 (20) 514 #define SCU_CLKSTOP_MAC4 (21) 515 516 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 517 { 518 u32 reset_bit; 519 u32 clkstop_bit; 520 521 522 switch (index) { 523 case 1: 524 reset_bit = BIT(ASPEED_RESET_MAC1); 525 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 526 writel(reset_bit, &scu->sysreset_ctrl1); 527 udelay(100); 528 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 529 mdelay(10); 530 writel(reset_bit, &scu->sysreset_clr_ctrl1); 531 532 break; 533 case 2: 534 reset_bit = BIT(ASPEED_RESET_MAC2); 535 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 536 writel(reset_bit, &scu->sysreset_ctrl1); 537 udelay(100); 538 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 539 mdelay(10); 540 writel(reset_bit, &scu->sysreset_clr_ctrl1); 541 break; 542 case 3: 543 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 544 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 545 writel(reset_bit, &scu->sysreset_ctrl2); 546 udelay(100); 547 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 548 mdelay(10); 549 writel(reset_bit, &scu->sysreset_clr_ctrl2); 550 break; 551 case 4: 552 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 553 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 554 writel(reset_bit, &scu->sysreset_ctrl2); 555 udelay(100); 556 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 557 mdelay(10); 558 writel(reset_bit, &scu->sysreset_clr_ctrl2); 559 break; 560 default: 561 return -EINVAL; 562 } 563 564 return 0; 565 } 566 567 static int ast2600_clk_enable(struct clk *clk) 568 { 569 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 570 571 switch (clk->id) { 572 case ASPEED_CLK_GATE_MAC1CLK: 573 ast2600_configure_mac(priv->scu, 1); 574 break; 575 case ASPEED_CLK_GATE_MAC2CLK: 576 ast2600_configure_mac(priv->scu, 2); 577 break; 578 case ASPEED_CLK_GATE_MAC3CLK: 579 ast2600_configure_mac(priv->scu, 3); 580 break; 581 case ASPEED_CLK_GATE_MAC4CLK: 582 ast2600_configure_mac(priv->scu, 4); 583 break; 584 default: 585 pr_debug("can't enable clk \n"); 586 return -ENOENT; 587 break; 588 } 589 590 return 0; 591 } 592 593 struct clk_ops ast2600_clk_ops = { 594 .get_rate = ast2600_clk_get_rate, 595 .set_rate = ast2600_clk_set_rate, 596 .enable = ast2600_clk_enable, 597 }; 598 599 static int ast2600_clk_probe(struct udevice *dev) 600 { 601 struct ast2600_clk_priv *priv = dev_get_priv(dev); 602 603 priv->scu = devfdt_get_addr_ptr(dev); 604 if (IS_ERR(priv->scu)) 605 return PTR_ERR(priv->scu); 606 607 return 0; 608 } 609 610 static int ast2600_clk_bind(struct udevice *dev) 611 { 612 int ret; 613 614 /* The reset driver does not have a device node, so bind it here */ 615 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 616 if (ret) 617 debug("Warning: No reset driver: ret=%d\n", ret); 618 619 return 0; 620 } 621 622 static const struct udevice_id ast2600_clk_ids[] = { 623 { .compatible = "aspeed,ast2600-scu", }, 624 { } 625 }; 626 627 U_BOOT_DRIVER(aspeed_scu) = { 628 .name = "aspeed_scu", 629 .id = UCLASS_CLK, 630 .of_match = ast2600_clk_ids, 631 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 632 .ops = &ast2600_clk_ops, 633 .bind = ast2600_clk_bind, 634 .probe = ast2600_clk_probe, 635 }; 636