1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x00410410 22 #define MAC_DEF_DELAY_100M 0x00410410 23 #define MAC_DEF_DELAY_10M 0x00410410 24 25 #define MAC34_DEF_DELAY_1G 0x00104208 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 mult = (reg.b.m + 1) / (reg.b.n + 1); 129 div = (reg.b.p + 1); 130 } 131 return ((clkin * mult)/div); 132 133 } 134 135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 136 { 137 u32 clkin = AST2600_CLK_IN; 138 u32 apll_reg = readl(&scu->a_pll_param); 139 unsigned int mult, div = 1; 140 141 if (apll_reg & BIT(20)) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 146 u32 m = (apll_reg >> 5) & 0x3f; 147 u32 od = (apll_reg >> 4) & 0x1; 148 u32 n = apll_reg & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return ((clkin * mult)/div); 154 } 155 156 static u32 ast2600_a0_axi_ahb_div_table[] = { 157 2, 2, 3, 4, 158 }; 159 160 static u32 ast2600_a1_axi_ahb_div0_table[] = { 161 3, 2, 3, 4, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div1_table[] = { 165 3, 4, 6, 8, 166 }; 167 168 static u32 ast2600_a1_axi_ahb_default_table[] = { 169 3, 4, 3, 4, 2, 2, 2, 2, 170 }; 171 172 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 173 { 174 u32 hw_rev = readl(&scu->chip_id0); 175 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 176 u32 axi_div = 1; 177 u32 ahb_div = 0; 178 u32 rate = 0; 179 180 if (hw_rev & BIT(16)) { 181 if(hwstrap1 & BIT(16)) { 182 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 183 axi_div = 1; 184 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 185 } else { 186 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 187 axi_div = 2; 188 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 189 } 190 } else { 191 //a0 : fix axi = hpll / 2 192 axi_div = 2; 193 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 194 } 195 196 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 197 return (rate / axi_div / ahb_div); 198 } 199 200 static u32 ast2600_hpll_pclk1_div_table[] = { 201 4, 8, 12, 16, 20, 24, 28, 32, 202 }; 203 204 static u32 ast2600_hpll_pclk2_div_table[] = { 205 2, 4, 6, 8, 10, 12, 14, 16, 206 }; 207 208 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 209 { 210 u32 clk_sel1 = readl(&scu->clk_sel1); 211 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 212 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 213 214 return (rate / apb_div); 215 } 216 217 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 218 { 219 u32 clk_sel4 = readl(&scu->clk_sel4); 220 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 221 u32 rate = ast2600_get_hclk(scu); 222 223 return (rate / apb_div); 224 } 225 226 static u32 ast2600_get_uxclk_rate(struct ast2600_scu *scu) 227 { 228 u32 clk_in = 0; 229 u32 uxclk_sel = readl(&scu->clk_sel4); 230 231 uxclk_sel &= 0x3; 232 switch(uxclk_sel) { 233 case 0: 234 clk_in = ast2600_get_apll_rate(scu) / 4; 235 break; 236 case 1: 237 clk_in = ast2600_get_apll_rate(scu) / 2; 238 break; 239 case 2: 240 clk_in = ast2600_get_apll_rate(scu); 241 break; 242 case 3: 243 clk_in = ast2600_get_hclk(scu); 244 break; 245 } 246 247 return clk_in; 248 } 249 250 static u32 ast2600_get_huxclk_rate(struct ast2600_scu *scu) 251 { 252 u32 clk_in = 0; 253 u32 huclk_sel = readl(&scu->clk_sel4); 254 255 huclk_sel = ((huclk_sel >> 3) & 0x3); 256 switch(huclk_sel) { 257 case 0: 258 clk_in = ast2600_get_apll_rate(scu) / 4; 259 break; 260 case 1: 261 clk_in = ast2600_get_apll_rate(scu) / 2; 262 break; 263 case 2: 264 clk_in = ast2600_get_apll_rate(scu); 265 break; 266 case 3: 267 clk_in = ast2600_get_hclk(scu); 268 break; 269 } 270 271 return clk_in; 272 } 273 274 static u32 ast2600_get_uart_from_uxclk_rate(struct ast2600_scu *scu) 275 { 276 u32 clk_in = ast2600_get_uxclk_rate(scu); 277 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 278 unsigned int mult, div; 279 280 u32 n = (div_reg >> 8) & 0x3ff; 281 u32 r = div_reg & 0xff; 282 283 mult = r; 284 div = (n * 4); 285 return (clk_in * mult)/div; 286 } 287 288 static u32 ast2600_get_uart_from_huxclk_rate(struct ast2600_scu *scu) 289 { 290 u32 clk_in = ast2600_get_huxclk_rate(scu); 291 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 292 293 unsigned int mult, div; 294 295 u32 n = (div_reg >> 8) & 0x3ff; 296 u32 r = div_reg & 0xff; 297 298 mult = r; 299 div = (n * 4); 300 return (clk_in * mult)/div; 301 } 302 303 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 304 { 305 u32 clkin = 0; 306 u32 clk_sel = readl(&scu->clk_sel4); 307 u32 div = (clk_sel >> 28) & 0x7; 308 309 if(clk_sel & BIT(8)) { 310 clkin = ast2600_get_apll_rate(scu); 311 } else { 312 clkin = ast2600_get_hclk(scu); 313 } 314 div = (div + 1) << 1; 315 316 return (clkin / div); 317 } 318 319 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 320 { 321 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 322 u32 clk_sel = readl(&scu->clk_sel1); 323 u32 div = (clk_sel >> 12) & 0x7; 324 325 div = (div + 1) << 2; 326 327 return (clkin / div); 328 } 329 330 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 331 { 332 u32 uart_sel = readl(&scu->clk_sel4); 333 u32 uart_sel5 = readl(&scu->clk_sel5); 334 ulong uart_clk = 0; 335 336 switch(uart_idx) { 337 case 1: 338 case 2: 339 case 3: 340 case 4: 341 case 6: 342 if(uart_sel & BIT(uart_idx - 1)) 343 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 344 else 345 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 346 break; 347 case 5: //24mhz is come form usb phy 48Mhz 348 { 349 u8 uart5_clk_sel = 0; 350 //high bit 351 if (readl(&scu->misc_ctrl1) & BIT(12)) 352 uart5_clk_sel = 0x2; 353 else 354 uart5_clk_sel = 0x0; 355 356 if (readl(&scu->clk_sel2) & BIT(14)) 357 uart5_clk_sel |= 0x1; 358 359 switch(uart5_clk_sel) { 360 case 0: 361 uart_clk = 24000000; 362 break; 363 case 1: 364 uart_clk = 0; 365 break; 366 case 2: 367 uart_clk = 24000000/13; 368 break; 369 case 3: 370 uart_clk = 192000000/13; 371 break; 372 } 373 } 374 break; 375 case 7: 376 case 8: 377 case 9: 378 case 10: 379 case 11: 380 case 12: 381 case 13: 382 if(uart_sel5 & BIT(uart_idx - 1)) 383 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 384 else 385 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 386 break; 387 } 388 389 return uart_clk; 390 } 391 392 static ulong ast2600_clk_get_rate(struct clk *clk) 393 { 394 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 395 ulong rate = 0; 396 397 switch (clk->id) { 398 case ASPEED_CLK_HPLL: 399 case ASPEED_CLK_EPLL: 400 case ASPEED_CLK_DPLL: 401 case ASPEED_CLK_MPLL: 402 rate = ast2600_get_pll_rate(priv->scu, clk->id); 403 break; 404 case ASPEED_CLK_AHB: 405 rate = ast2600_get_hclk(priv->scu); 406 break; 407 case ASPEED_CLK_APB1: 408 rate = ast2600_get_pclk1(priv->scu); 409 break; 410 case ASPEED_CLK_APB2: 411 rate = ast2600_get_pclk2(priv->scu); 412 break; 413 case ASPEED_CLK_APLL: 414 rate = ast2600_get_apll_rate(priv->scu); 415 break; 416 case ASPEED_CLK_GATE_UART1CLK: 417 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 418 break; 419 case ASPEED_CLK_GATE_UART2CLK: 420 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 421 break; 422 case ASPEED_CLK_GATE_UART3CLK: 423 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 424 break; 425 case ASPEED_CLK_GATE_UART4CLK: 426 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 427 break; 428 case ASPEED_CLK_GATE_UART5CLK: 429 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 430 break; 431 case ASPEED_CLK_SDIO: 432 rate = ast2600_get_sdio_clk_rate(priv->scu); 433 break; 434 case ASPEED_CLK_EMMC: 435 rate = ast2600_get_emmc_clk_rate(priv->scu); 436 break; 437 default: 438 pr_debug("can't get clk rate \n"); 439 return -ENOENT; 440 break; 441 } 442 443 return rate; 444 } 445 446 /** 447 * @brief lookup PLL divider config by input/output rate 448 * @param[in] *pll - PLL descriptor 449 * @return true - if PLL divider config is found, false - else 450 * 451 * The function caller shall fill "pll->in" and "pll->out", then this function 452 * will search the lookup table to find a valid PLL divider configuration. 453 */ 454 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 455 { 456 u32 i; 457 bool is_found = false; 458 459 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 460 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 461 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 462 is_found = true; 463 pll->cfg.reg.w = def_cfg->cfg.reg.w; 464 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 465 break; 466 } 467 } 468 return is_found; 469 } 470 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 471 struct ast2600_pll_cfg *p_cfg, int pll_idx) 472 { 473 u32 addr, addr_ext; 474 u32 reg; 475 476 switch (pll_idx) { 477 case ASPEED_CLK_HPLL: 478 addr = (u32)(&scu->h_pll_param); 479 addr_ext = (u32)(&scu->h_pll_ext_param); 480 break; 481 case ASPEED_CLK_MPLL: 482 addr = (u32)(&scu->m_pll_param); 483 addr_ext = (u32)(&scu->m_pll_ext_param); 484 break; 485 case ASPEED_CLK_DPLL: 486 addr = (u32)(&scu->d_pll_param); 487 addr_ext = (u32)(&scu->d_pll_ext_param); 488 break; 489 case ASPEED_CLK_EPLL: 490 addr = (u32)(&scu->e_pll_param); 491 addr_ext = (u32)(&scu->e_pll_ext_param); 492 break; 493 default: 494 debug("unknown PLL index\n"); 495 return 1; 496 } 497 498 p_cfg->reg.b.bypass = 0; 499 p_cfg->reg.b.off = 1; 500 p_cfg->reg.b.reset = 1; 501 502 reg = readl(addr); 503 reg &= ~GENMASK(25, 0); 504 reg |= p_cfg->reg.w; 505 writel(reg, addr); 506 507 /* write extend parameter */ 508 writel(p_cfg->ext_reg, addr_ext); 509 udelay(100); 510 p_cfg->reg.b.off = 0; 511 p_cfg->reg.b.reset = 0; 512 reg &= ~GENMASK(25, 0); 513 reg |= p_cfg->reg.w; 514 writel(reg, addr); 515 516 /* polling PLL lock status */ 517 while(0 == (readl(addr_ext) & BIT(31))); 518 519 return 0; 520 } 521 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 522 { 523 struct ast2600_pll_desc mpll; 524 525 mpll.in = AST2600_CLK_IN; 526 mpll.out = rate; 527 if (false == ast2600_search_clock_config(&mpll)) { 528 printf("error!! unable to find valid DDR clock setting\n"); 529 return 0; 530 } 531 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 532 533 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 534 } 535 536 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 537 { 538 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 539 540 ulong new_rate; 541 switch (clk->id) { 542 case ASPEED_CLK_MPLL: 543 new_rate = ast2600_configure_ddr(priv->scu, rate); 544 break; 545 default: 546 return -ENOENT; 547 } 548 549 return new_rate; 550 } 551 552 #define SCU_CLKSTOP_MAC1 (20) 553 #define SCU_CLKSTOP_MAC2 (21) 554 #define SCU_CLKSTOP_MAC3 (20) 555 #define SCU_CLKSTOP_MAC4 (21) 556 557 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 558 { 559 #if 0 560 struct ast2600_pll_desc epll; 561 562 epll.in = AST2600_CLK_IN; 563 epll.out = 1000000000; 564 if (false == ast2600_search_clock_config(&epll)) { 565 printf( 566 "error!! unable to find valid ETHNET MAC clock setting\n"); 567 debug("%s: epll cfg = 0x%08x 0x%08x\n", __func__, 568 epll.cfg.reg.w, epll.cfg.ext_reg); 569 debug("%s: epll cfg = %02x %02x %02x\n", __func__, 570 epll.cfg.reg.b.m, epll.cfg.reg.b.n, epll.cfg.reg.b.p); 571 return 0; 572 } 573 ast2600_configure_pll(scu, &(epll.cfg), ASPEED_CLK_EPLL); 574 575 /* select MAC#1 and MAC#2 clock source = EPLL / 8 */ 576 clksel = readl(&scu->clk_sel2); 577 clksel &= ~BIT(23); 578 clksel |= 0x7 << 20; 579 writel(clksel, &scu->clk_sel2); 580 #endif 581 /* scu340[25:0]: 1G default delay */ 582 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 583 MAC_DEF_DELAY_1G); 584 585 /* set 100M/10M default delay */ 586 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 587 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 588 589 /* MAC AHB = HPLL / 6 */ 590 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 591 592 return 0; 593 } 594 595 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 596 { 597 ast2600_configure_mac12_clk(scu); 598 599 /* 600 * scu350[31] RGMII 125M source: 0 = from IO pin 601 * scu350[25:0] MAC 1G delay 602 */ 603 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 604 MAC34_DEF_DELAY_1G); 605 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 606 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 607 608 /* 609 * clock source seletion and divider 610 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 611 * scu310[18:16] : RMII 50M = HCLK_200M / 4 612 */ 613 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 614 ((0x0 << 24) | (0x3 << 16))); 615 616 /* 617 * set driving strength 618 * scu458[3:2] : MAC4 driving strength 619 * scu458[1:0] : MAC3 driving strength 620 */ 621 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 622 (0x2 << 2) | (0x2 << 0)); 623 624 return 0; 625 } 626 627 /** 628 * ast2600 RGMII clock source tree 629 * 630 * 125M from external PAD -------->|\ 631 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 632 * | |---->| divider |---->|/ + 633 * EPLL -->|/ | 634 * | 635 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 636 * | 637 * +--------------------------->|\ 638 * | |----> RGMII 125M for MAC#3 & MAC#4 639 * HCLK 200M ---->|divider|---->|/ 640 * 641 * To simplify the control flow: 642 * 1. RGMII 1/2 always use EPLL as the internal clock source 643 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 644 * 645 * 125M from external PAD -------->|\ 646 * | |---->RGMII 125M for MAC#1 & MAC#2 647 * EPLL---->| divider |--->|/ + 648 * | 649 * +<--------------------|RGMIICK PAD output enable|<-------------+ 650 * | 651 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 652 */ 653 #define RGMIICK_SRC_PAD 0 654 #define RGMIICK_SRC_EPLL 1 /* recommended */ 655 #define RGMIICK_SRC_HPLL 2 656 657 #define RGMIICK_DIV2 1 658 #define RGMIICK_DIV3 2 659 #define RGMIICK_DIV4 3 660 #define RGMIICK_DIV5 4 661 #define RGMIICK_DIV6 5 662 #define RGMIICK_DIV7 6 663 #define RGMIICK_DIV8 7 /* recommended */ 664 665 #define RMIICK_DIV4 0 666 #define RMIICK_DIV8 1 667 #define RMIICK_DIV12 2 668 #define RMIICK_DIV16 3 669 #define RMIICK_DIV20 4 /* recommended */ 670 #define RMIICK_DIV24 5 671 #define RMIICK_DIV28 6 672 #define RMIICK_DIV32 7 673 674 struct ast2600_mac_clk_div { 675 u32 src; /* 0=external PAD, 1=internal PLL */ 676 u32 fin; /* divider input speed */ 677 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 678 u32 fout; /* fout = fin / n */ 679 }; 680 681 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 682 .src = ASPEED_CLK_EPLL, 683 .fin = 1000000000, 684 .n = RGMIICK_DIV8, 685 .fout = 125000000, 686 }; 687 688 struct ast2600_mac_clk_div rmii_clk_defconfig = { 689 .src = ASPEED_CLK_EPLL, 690 .fin = 1000000000, 691 .n = RMIICK_DIV20, 692 .fout = 50000000, 693 }; 694 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 695 struct ast2600_mac_clk_div *p_cfg) 696 { 697 struct ast2600_pll_desc pll; 698 699 pll.in = AST2600_CLK_IN; 700 pll.out = p_cfg->fin; 701 if (false == ast2600_search_clock_config(&pll)) { 702 printf("error!! unable to find valid ETHNET MAC clock " 703 "setting\n"); 704 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 705 pll.cfg.ext_reg); 706 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 707 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 708 return; 709 } 710 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 711 } 712 713 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 714 struct ast2600_mac_clk_div *p_cfg) 715 { 716 u32 reg_304 = readl(&p_scu->clk_sel2); 717 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 718 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 719 720 reg_340 &= ~GENMASK(31, 29); 721 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 722 reg_340 |= BIT(28); 723 if ((p_cfg->src == ASPEED_CLK_EPLL) || 724 (p_cfg->src == ASPEED_CLK_HPLL)) { 725 /* 726 * re-init PLL if the current PLL output frequency doesn't match 727 * the divider setting 728 */ 729 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 730 ast2600_init_mac_pll(p_scu, p_cfg); 731 } 732 /* scu340[31]: select RGMII 125M from internal source */ 733 reg_340 |= BIT(31); 734 } 735 736 reg_304 &= ~GENMASK(23, 20); 737 738 /* set clock divider */ 739 reg_304 |= (p_cfg->n & 0x7) << 20; 740 741 /* select internal clock source */ 742 if (ASPEED_CLK_HPLL == p_cfg->src) { 743 reg_304 |= BIT(23); 744 } 745 746 /* RGMII 3/4 clock source select */ 747 reg_350 &= ~BIT(31); 748 #if 0 749 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 750 reg_350 |= BIT(31); 751 } 752 753 /* set clock divider */ 754 reg_310 &= ~GENMASK(22, 20); 755 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 756 #endif 757 758 writel(reg_304, &p_scu->clk_sel2); 759 writel(reg_340, &p_scu->mac12_clk_delay); 760 writel(reg_350, &p_scu->mac34_clk_delay); 761 } 762 763 /** 764 * ast2600 RMII/NCSI clock source tree 765 * 766 * HPLL -->|\ 767 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 768 * EPLL -->|/ 769 * 770 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 771 */ 772 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 773 struct ast2600_mac_clk_div *p_cfg) 774 { 775 u32 reg_304; 776 u32 reg_310; 777 778 if ((p_cfg->src == ASPEED_CLK_EPLL) || 779 (p_cfg->src == ASPEED_CLK_HPLL)) { 780 /* 781 * re-init PLL if the current PLL output frequency doesn't match 782 * the divider setting 783 */ 784 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 785 ast2600_init_mac_pll(p_scu, p_cfg); 786 } 787 } 788 789 reg_304 = readl(&p_scu->clk_sel2); 790 reg_310 = readl(&p_scu->clk_sel4); 791 792 reg_304 &= ~GENMASK(19, 16); 793 794 /* set RMII 1/2 clock divider */ 795 reg_304 |= (p_cfg->n & 0x7) << 16; 796 797 /* RMII clock source selection */ 798 if (ASPEED_CLK_HPLL == p_cfg->src) { 799 reg_304 |= BIT(19); 800 } 801 802 /* set RMII 3/4 clock divider */ 803 reg_310 &= ~GENMASK(18, 16); 804 reg_310 |= (0x3 << 16); 805 806 writel(reg_304, &p_scu->clk_sel2); 807 writel(reg_310, &p_scu->clk_sel4); 808 } 809 810 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 811 { 812 u32 reset_bit; 813 u32 clkstop_bit; 814 815 /* check board level setup */ 816 u32 mac_1_2_cfg = readl(&scu->hwstrap1) & GENMASK(7, 6); 817 u32 mac_3_4_cfg = readl(&scu->hwstrap2) & GENMASK(1, 0); 818 819 if ((mac_1_2_cfg == 0) && (mac_3_4_cfg != 0)) { 820 /** 821 * HW limitation: 822 * impossible to set MAC 3/4 = RGMII when MAC 1/2 = RMII 823 */ 824 printf("%s: unsupported configuration\n", __func__); 825 return -EINVAL; 826 } else if (mac_1_2_cfg | mac_3_4_cfg) { 827 /* setup RGMII clock */ 828 ast2600_init_rgmii_clk(scu, &rgmii_clk_defconfig); 829 } else { 830 /* setup RMII clock */ 831 ast2600_init_rmii_clk(scu, &rmii_clk_defconfig); 832 } 833 834 if (index < 3) 835 ast2600_configure_mac12_clk(scu); 836 else 837 ast2600_configure_mac34_clk(scu); 838 839 switch (index) { 840 case 1: 841 reset_bit = BIT(ASPEED_RESET_MAC1); 842 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 843 writel(reset_bit, &scu->sysreset_ctrl1); 844 udelay(100); 845 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 846 mdelay(10); 847 writel(reset_bit, &scu->sysreset_clr_ctrl1); 848 849 break; 850 case 2: 851 reset_bit = BIT(ASPEED_RESET_MAC2); 852 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 853 writel(reset_bit, &scu->sysreset_ctrl1); 854 udelay(100); 855 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 856 mdelay(10); 857 writel(reset_bit, &scu->sysreset_clr_ctrl1); 858 break; 859 case 3: 860 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 861 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 862 writel(reset_bit, &scu->sysreset_ctrl2); 863 udelay(100); 864 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 865 mdelay(10); 866 writel(reset_bit, &scu->sysreset_clr_ctrl2); 867 break; 868 case 4: 869 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 870 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 871 writel(reset_bit, &scu->sysreset_ctrl2); 872 udelay(100); 873 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 874 mdelay(10); 875 writel(reset_bit, &scu->sysreset_clr_ctrl2); 876 break; 877 default: 878 return -EINVAL; 879 } 880 881 return 0; 882 } 883 884 #define SCU_CLKSTOP_SDIO 4 885 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 886 { 887 u32 reset_bit; 888 u32 clkstop_bit; 889 890 reset_bit = BIT(ASPEED_RESET_SD - 32); 891 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 892 893 writel(reset_bit, &scu->sysreset_ctrl2); 894 895 udelay(100); 896 //enable clk 897 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 898 mdelay(10); 899 writel(reset_bit, &scu->sysreset_clr_ctrl2); 900 901 return 0; 902 } 903 904 #define SCU_CLKSTOP_EXTSD 31 905 #define SCU_CLK_SD_MASK (0x7 << 28) 906 #define SCU_CLK_SD_DIV(x) (x << 28) 907 908 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 909 { 910 u32 clk_sel = readl(&scu->clk_sel4); 911 u32 enableclk_bit; 912 913 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 914 915 //default use apll for clock source 800/4 = 200 : controller max is 200mhz 916 clk_sel &= ~SCU_CLK_SD_MASK; 917 clk_sel |= SCU_CLK_SD_DIV(1) | BIT(8); 918 writel(clk_sel, &scu->clk_sel4); 919 920 //enable clk 921 setbits_le32(&scu->clk_sel4, enableclk_bit); 922 923 return 0; 924 } 925 926 #define SCU_CLKSTOP_EMMC 27 927 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 928 { 929 u32 reset_bit; 930 u32 clkstop_bit; 931 932 reset_bit = BIT(ASPEED_RESET_EMMC); 933 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 934 935 writel(reset_bit, &scu->sysreset_ctrl1); 936 udelay(100); 937 //enable clk 938 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 939 mdelay(10); 940 writel(reset_bit, &scu->sysreset_clr_ctrl1); 941 942 return 0; 943 } 944 945 #define SCU_CLKSTOP_EXTEMMC 15 946 #define SCU_CLK_EMMC_MASK (0x7 << 12) 947 #define SCU_CLK_EMMC_DIV(x) (x << 12) 948 949 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 950 { 951 u32 clk_sel = readl(&scu->clk_sel1); 952 u32 enableclk_bit; 953 954 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 955 956 clk_sel &= ~SCU_CLK_SD_MASK; 957 clk_sel |= SCU_CLK_SD_DIV(1); 958 writel(clk_sel, &scu->clk_sel1); 959 960 //enable clk 961 setbits_le32(&scu->clk_sel1, enableclk_bit); 962 963 return 0; 964 } 965 966 static int ast2600_clk_enable(struct clk *clk) 967 { 968 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 969 970 switch (clk->id) { 971 case ASPEED_CLK_GATE_MAC1CLK: 972 ast2600_configure_mac(priv->scu, 1); 973 break; 974 case ASPEED_CLK_GATE_MAC2CLK: 975 ast2600_configure_mac(priv->scu, 2); 976 break; 977 case ASPEED_CLK_GATE_MAC3CLK: 978 ast2600_configure_mac(priv->scu, 3); 979 break; 980 case ASPEED_CLK_GATE_MAC4CLK: 981 ast2600_configure_mac(priv->scu, 4); 982 break; 983 case ASPEED_CLK_GATE_SDCLK: 984 ast2600_enable_sdclk(priv->scu); 985 break; 986 case ASPEED_CLK_GATE_SDEXTCLK: 987 ast2600_enable_extsdclk(priv->scu); 988 break; 989 case ASPEED_CLK_GATE_EMMCCLK: 990 ast2600_enable_emmcclk(priv->scu); 991 break; 992 case ASPEED_CLK_GATE_EMMCEXTCLK: 993 ast2600_enable_extemmcclk(priv->scu); 994 break; 995 default: 996 pr_debug("can't enable clk \n"); 997 return -ENOENT; 998 break; 999 } 1000 1001 return 0; 1002 } 1003 1004 struct clk_ops ast2600_clk_ops = { 1005 .get_rate = ast2600_clk_get_rate, 1006 .set_rate = ast2600_clk_set_rate, 1007 .enable = ast2600_clk_enable, 1008 }; 1009 1010 static int ast2600_clk_probe(struct udevice *dev) 1011 { 1012 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1013 1014 priv->scu = devfdt_get_addr_ptr(dev); 1015 if (IS_ERR(priv->scu)) 1016 return PTR_ERR(priv->scu); 1017 1018 return 0; 1019 } 1020 1021 static int ast2600_clk_bind(struct udevice *dev) 1022 { 1023 int ret; 1024 1025 /* The reset driver does not have a device node, so bind it here */ 1026 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1027 if (ret) 1028 debug("Warning: No reset driver: ret=%d\n", ret); 1029 1030 return 0; 1031 } 1032 1033 #if CONFIG_IS_ENABLED(CMD_CLK) 1034 struct aspeed_clks { 1035 ulong id; 1036 const char *name; 1037 }; 1038 1039 static struct aspeed_clks aspeed_clk_names[] = { 1040 { ASPEED_CLK_HPLL, "hpll" }, 1041 { ASPEED_CLK_MPLL, "mpll" }, 1042 { ASPEED_CLK_APLL, "apll" }, 1043 { ASPEED_CLK_EPLL, "epll" }, 1044 { ASPEED_CLK_DPLL, "dpll" }, 1045 { ASPEED_CLK_AHB, "hclk" }, 1046 { ASPEED_CLK_APB1, "pclk1" }, 1047 { ASPEED_CLK_APB2, "pclk2" }, 1048 }; 1049 1050 int soc_clk_dump(void) 1051 { 1052 struct udevice *dev; 1053 struct clk clk; 1054 unsigned long rate; 1055 int i, ret; 1056 1057 ret = uclass_get_device_by_driver(UCLASS_CLK, 1058 DM_GET_DRIVER(aspeed_scu), &dev); 1059 if (ret) 1060 return ret; 1061 1062 printf("Clk\t\tHz\n"); 1063 1064 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1065 clk.id = aspeed_clk_names[i].id; 1066 ret = clk_request(dev, &clk); 1067 if (ret < 0) { 1068 debug("%s clk_request() failed: %d\n", __func__, ret); 1069 continue; 1070 } 1071 1072 ret = clk_get_rate(&clk); 1073 rate = ret; 1074 1075 clk_free(&clk); 1076 1077 if (ret == -ENOTSUPP) { 1078 printf("clk ID %lu not supported yet\n", 1079 aspeed_clk_names[i].id); 1080 continue; 1081 } 1082 if (ret < 0) { 1083 printf("%s %lu: get_rate err: %d\n", 1084 __func__, aspeed_clk_names[i].id, ret); 1085 continue; 1086 } 1087 1088 printf("%s(%3lu):\t%lu\n", 1089 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1090 } 1091 1092 return 0; 1093 } 1094 #endif 1095 1096 static const struct udevice_id ast2600_clk_ids[] = { 1097 { .compatible = "aspeed,ast2600-scu", }, 1098 { } 1099 }; 1100 1101 U_BOOT_DRIVER(aspeed_scu) = { 1102 .name = "aspeed_scu", 1103 .id = UCLASS_CLK, 1104 .of_match = ast2600_clk_ids, 1105 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1106 .ops = &ast2600_clk_ops, 1107 .bind = ast2600_clk_bind, 1108 .probe = ast2600_clk_probe, 1109 }; 1110