1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 38 #define CHIP_REVISION_ID GENMASK(23, 16) 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* 43 * Clock divider/multiplier configuration struct. 44 * For H-PLL and M-PLL the formula is 45 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 46 * M - Numerator 47 * N - Denumerator 48 * P - Post Divider 49 * They have the same layout in their control register. 50 * 51 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 52 * yet needed and ignored by clock configurations. 53 */ 54 union ast2600_pll_reg { 55 unsigned int w; 56 struct { 57 unsigned int m : 13; /* bit[12:0] */ 58 unsigned int n : 6; /* bit[18:13] */ 59 unsigned int p : 4; /* bit[22:19] */ 60 unsigned int off : 1; /* bit[23] */ 61 unsigned int bypass : 1; /* bit[24] */ 62 unsigned int reset : 1; /* bit[25] */ 63 unsigned int reserved : 6; /* bit[31:26] */ 64 } b; 65 }; 66 67 struct ast2600_pll_cfg { 68 union ast2600_pll_reg reg; 69 unsigned int ext_reg; 70 }; 71 72 struct ast2600_pll_desc { 73 u32 in; 74 u32 out; 75 struct ast2600_pll_cfg cfg; 76 }; 77 78 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 79 {.in = AST2600_CLK_IN, .out = 400000000, 80 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 81 .cfg.ext_reg = 0x31, 82 }, 83 {.in = AST2600_CLK_IN, .out = 200000000, 84 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 85 .cfg.ext_reg = 0x3f 86 }, 87 {.in = AST2600_CLK_IN, .out = 334000000, 88 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 89 .cfg.ext_reg = 0x14d 90 }, 91 92 {.in = AST2600_CLK_IN, .out = 1000000000, 93 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 94 .cfg.ext_reg = 0x3d 95 }, 96 97 {.in = AST2600_CLK_IN, .out = 50000000, 98 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 99 .cfg.ext_reg = 0x31 100 }, 101 }; 102 103 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 104 { 105 u32 clkin = AST2600_CLK_IN; 106 u32 pll_reg = 0; 107 unsigned int mult, div = 1; 108 109 switch(pll_idx) { 110 case ASPEED_CLK_HPLL: 111 pll_reg = readl(&scu->h_pll_param); 112 break; 113 case ASPEED_CLK_MPLL: 114 pll_reg = readl(&scu->m_pll_param); 115 break; 116 case ASPEED_CLK_DPLL: 117 pll_reg = readl(&scu->d_pll_param); 118 break; 119 case ASPEED_CLK_EPLL: 120 pll_reg = readl(&scu->e_pll_param); 121 break; 122 } 123 if (pll_reg & BIT(24)) { 124 /* Pass through mode */ 125 mult = div = 1; 126 } else { 127 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 128 union ast2600_pll_reg reg; 129 reg.w = pll_reg; 130 if(pll_idx == ASPEED_CLK_HPLL) { 131 /* 132 HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 133 fix 0xBF when SCU500[10]=0 and SCU500[8]=1 134 SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 135 HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 136 HPLL Divider (P) = SCU200[22:19] (default 0x0) 137 HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 138 fix 0x5F when SCU500[10]=0 and SCU500[8]=1 139 SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 140 */ 141 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 142 if(hwstrap1 & BIT(10)) 143 reg.b.m = 0x5F; 144 else { 145 if(hwstrap1 & BIT(8)) 146 reg.b.m = 0xBF; 147 //otherwise keep default 0x8F 148 } 149 } 150 mult = (reg.b.m + 1) / (reg.b.n + 1); 151 div = (reg.b.p + 1); 152 } 153 return ((clkin * mult)/div); 154 } 155 156 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 157 { 158 u32 hw_rev = readl(&scu->chip_id1); 159 u32 clkin = AST2600_CLK_IN; 160 u32 apll_reg = readl(&scu->a_pll_param); 161 unsigned int mult, div = 1; 162 163 if (((hw_rev & CHIP_REVISION_ID) >> 16) == 3) { 164 //ast2600a2 165 if (apll_reg & BIT(24)) { 166 /* Pass through mode */ 167 mult = div = 1; 168 } else { 169 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 170 u32 m = apll_reg & 0x1fff; 171 u32 n = (apll_reg >> 13) & 0x3f; 172 u32 p = (apll_reg >> 19) & 0xf; 173 174 mult = (m + 1); 175 div = (n + 1) * (p + 1); 176 } 177 178 } else { 179 if (apll_reg & BIT(20)) { 180 /* Pass through mode */ 181 mult = div = 1; 182 } else { 183 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 184 u32 m = (apll_reg >> 5) & 0x3f; 185 u32 od = (apll_reg >> 4) & 0x1; 186 u32 n = apll_reg & 0xf; 187 188 mult = (2 - od) * (m + 2); 189 div = n + 1; 190 } 191 } 192 return ((clkin * mult)/div); 193 } 194 195 static u32 ast2600_a0_axi_ahb_div_table[] = { 196 2, 2, 3, 4, 197 }; 198 199 static u32 ast2600_a1_axi_ahb_div0_table[] = { 200 3, 2, 3, 4, 201 }; 202 203 static u32 ast2600_a1_axi_ahb_div1_table[] = { 204 3, 4, 6, 8, 205 }; 206 207 static u32 ast2600_a1_axi_ahb_default_table[] = { 208 3, 4, 3, 4, 2, 2, 2, 2, 209 }; 210 211 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 212 { 213 u32 hw_rev = readl(&scu->chip_id1); 214 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 215 u32 axi_div = 1; 216 u32 ahb_div = 0; 217 u32 rate = 0; 218 219 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 220 //ast2600a1 221 if(hwstrap1 & BIT(16)) { 222 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 223 axi_div = 1; 224 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 225 } else { 226 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 227 axi_div = 2; 228 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 229 } 230 } else { 231 //ast2600a0 : fix axi = hpll / 2 232 axi_div = 2; 233 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 234 } 235 236 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 237 return (rate / axi_div / ahb_div); 238 } 239 240 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 241 { 242 u32 rate; 243 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 244 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 245 246 return (rate /((bclk_sel + 1) * 4)); 247 } 248 249 static u32 ast2600_hpll_pclk1_div_table[] = { 250 4, 8, 12, 16, 20, 24, 28, 32, 251 }; 252 253 static u32 ast2600_hpll_pclk2_div_table[] = { 254 2, 4, 6, 8, 10, 12, 14, 16, 255 }; 256 257 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 258 { 259 u32 clk_sel1 = readl(&scu->clk_sel1); 260 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 261 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 262 263 return (rate / apb_div); 264 } 265 266 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 267 { 268 u32 clk_sel4 = readl(&scu->clk_sel4); 269 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 270 u32 rate = ast2600_get_hclk(scu); 271 272 return (rate / apb_div); 273 } 274 275 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 276 { 277 u32 clk_in = 0; 278 u32 uxclk_sel = readl(&scu->clk_sel5); 279 280 uxclk_sel &= 0x3; 281 switch(uxclk_sel) { 282 case 0: 283 clk_in = ast2600_get_apll_rate(scu) / 4; 284 break; 285 case 1: 286 clk_in = ast2600_get_apll_rate(scu) / 2; 287 break; 288 case 2: 289 clk_in = ast2600_get_apll_rate(scu); 290 break; 291 case 3: 292 clk_in = ast2600_get_hclk(scu); 293 break; 294 } 295 296 return clk_in; 297 } 298 299 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 300 { 301 u32 clk_in = 0; 302 u32 huclk_sel = readl(&scu->clk_sel5); 303 304 huclk_sel = ((huclk_sel >> 3) & 0x3); 305 switch(huclk_sel) { 306 case 0: 307 clk_in = ast2600_get_apll_rate(scu) / 4; 308 break; 309 case 1: 310 clk_in = ast2600_get_apll_rate(scu) / 2; 311 break; 312 case 2: 313 clk_in = ast2600_get_apll_rate(scu); 314 break; 315 case 3: 316 clk_in = ast2600_get_hclk(scu); 317 break; 318 } 319 320 return clk_in; 321 } 322 323 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 324 { 325 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 326 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 327 unsigned int mult, div; 328 329 u32 n = (div_reg >> 8) & 0x3ff; 330 u32 r = div_reg & 0xff; 331 332 mult = r; 333 div = (n * 2); 334 return (clk_in * mult)/div; 335 } 336 337 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 338 { 339 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 340 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 341 342 unsigned int mult, div; 343 344 u32 n = (div_reg >> 8) & 0x3ff; 345 u32 r = div_reg & 0xff; 346 347 mult = r; 348 div = (n * 2); 349 return (clk_in * mult)/div; 350 } 351 352 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 353 { 354 u32 clkin = 0; 355 u32 clk_sel = readl(&scu->clk_sel4); 356 u32 div = (clk_sel >> 28) & 0x7; 357 358 if(clk_sel & BIT(8)) { 359 clkin = ast2600_get_apll_rate(scu); 360 } else { 361 clkin = ast2600_get_hclk(scu); 362 } 363 div = (div + 1) << 1; 364 365 return (clkin / div); 366 } 367 368 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 369 { 370 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 371 u32 clk_sel = readl(&scu->clk_sel1); 372 u32 div = (clk_sel >> 12) & 0x7; 373 374 div = (div + 1) << 2; 375 376 return (clkin / div); 377 } 378 379 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 380 { 381 u32 uart_sel = readl(&scu->clk_sel4); 382 u32 uart_sel5 = readl(&scu->clk_sel5); 383 ulong uart_clk = 0; 384 385 switch(uart_idx) { 386 case 1: 387 case 2: 388 case 3: 389 case 4: 390 case 6: 391 if(uart_sel & BIT(uart_idx - 1)) 392 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 393 else 394 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 395 break; 396 case 5: //24mhz is come form usb phy 48Mhz 397 { 398 u8 uart5_clk_sel = 0; 399 //high bit 400 if (readl(&scu->misc_ctrl1) & BIT(12)) 401 uart5_clk_sel = 0x2; 402 else 403 uart5_clk_sel = 0x0; 404 405 if (readl(&scu->clk_sel2) & BIT(14)) 406 uart5_clk_sel |= 0x1; 407 408 switch(uart5_clk_sel) { 409 case 0: 410 uart_clk = 24000000; 411 break; 412 case 1: 413 uart_clk = 192000000; 414 break; 415 case 2: 416 uart_clk = 24000000/13; 417 break; 418 case 3: 419 uart_clk = 192000000/13; 420 break; 421 } 422 } 423 break; 424 case 7: 425 case 8: 426 case 9: 427 case 10: 428 case 11: 429 case 12: 430 case 13: 431 if(uart_sel5 & BIT(uart_idx - 1)) 432 uart_clk = ast2600_get_uart_huxclk_rate(scu); 433 else 434 uart_clk = ast2600_get_uart_uxclk_rate(scu); 435 break; 436 } 437 438 return uart_clk; 439 } 440 441 static ulong ast2600_clk_get_rate(struct clk *clk) 442 { 443 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 444 ulong rate = 0; 445 446 switch (clk->id) { 447 case ASPEED_CLK_HPLL: 448 case ASPEED_CLK_EPLL: 449 case ASPEED_CLK_DPLL: 450 case ASPEED_CLK_MPLL: 451 rate = ast2600_get_pll_rate(priv->scu, clk->id); 452 break; 453 case ASPEED_CLK_AHB: 454 rate = ast2600_get_hclk(priv->scu); 455 break; 456 case ASPEED_CLK_APB1: 457 rate = ast2600_get_pclk1(priv->scu); 458 break; 459 case ASPEED_CLK_APB2: 460 rate = ast2600_get_pclk2(priv->scu); 461 break; 462 case ASPEED_CLK_APLL: 463 rate = ast2600_get_apll_rate(priv->scu); 464 break; 465 case ASPEED_CLK_GATE_UART1CLK: 466 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 467 break; 468 case ASPEED_CLK_GATE_UART2CLK: 469 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 470 break; 471 case ASPEED_CLK_GATE_UART3CLK: 472 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 473 break; 474 case ASPEED_CLK_GATE_UART4CLK: 475 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 476 break; 477 case ASPEED_CLK_GATE_UART5CLK: 478 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 479 break; 480 case ASPEED_CLK_BCLK: 481 rate = ast2600_get_bclk_rate(priv->scu); 482 break; 483 case ASPEED_CLK_SDIO: 484 rate = ast2600_get_sdio_clk_rate(priv->scu); 485 break; 486 case ASPEED_CLK_EMMC: 487 rate = ast2600_get_emmc_clk_rate(priv->scu); 488 break; 489 case ASPEED_CLK_UARTX: 490 rate = ast2600_get_uart_uxclk_rate(priv->scu); 491 break; 492 case ASPEED_CLK_HUARTX: 493 rate = ast2600_get_uart_huxclk_rate(priv->scu); 494 break; 495 default: 496 pr_debug("can't get clk rate \n"); 497 return -ENOENT; 498 break; 499 } 500 501 return rate; 502 } 503 504 /** 505 * @brief lookup PLL divider config by input/output rate 506 * @param[in] *pll - PLL descriptor 507 * @return true - if PLL divider config is found, false - else 508 * 509 * The function caller shall fill "pll->in" and "pll->out", then this function 510 * will search the lookup table to find a valid PLL divider configuration. 511 */ 512 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 513 { 514 u32 i; 515 bool is_found = false; 516 517 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 518 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 519 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 520 is_found = true; 521 pll->cfg.reg.w = def_cfg->cfg.reg.w; 522 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 523 break; 524 } 525 } 526 return is_found; 527 } 528 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 529 struct ast2600_pll_cfg *p_cfg, int pll_idx) 530 { 531 u32 addr, addr_ext; 532 u32 reg; 533 534 switch (pll_idx) { 535 case ASPEED_CLK_HPLL: 536 addr = (u32)(&scu->h_pll_param); 537 addr_ext = (u32)(&scu->h_pll_ext_param); 538 break; 539 case ASPEED_CLK_MPLL: 540 addr = (u32)(&scu->m_pll_param); 541 addr_ext = (u32)(&scu->m_pll_ext_param); 542 break; 543 case ASPEED_CLK_DPLL: 544 addr = (u32)(&scu->d_pll_param); 545 addr_ext = (u32)(&scu->d_pll_ext_param); 546 break; 547 case ASPEED_CLK_EPLL: 548 addr = (u32)(&scu->e_pll_param); 549 addr_ext = (u32)(&scu->e_pll_ext_param); 550 break; 551 default: 552 debug("unknown PLL index\n"); 553 return 1; 554 } 555 556 p_cfg->reg.b.bypass = 0; 557 p_cfg->reg.b.off = 1; 558 p_cfg->reg.b.reset = 1; 559 560 reg = readl(addr); 561 reg &= ~GENMASK(25, 0); 562 reg |= p_cfg->reg.w; 563 writel(reg, addr); 564 565 /* write extend parameter */ 566 writel(p_cfg->ext_reg, addr_ext); 567 udelay(100); 568 p_cfg->reg.b.off = 0; 569 p_cfg->reg.b.reset = 0; 570 reg &= ~GENMASK(25, 0); 571 reg |= p_cfg->reg.w; 572 writel(reg, addr); 573 574 /* polling PLL lock status */ 575 while(0 == (readl(addr_ext) & BIT(31))); 576 577 return 0; 578 } 579 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 580 { 581 struct ast2600_pll_desc mpll; 582 583 mpll.in = AST2600_CLK_IN; 584 mpll.out = rate; 585 if (false == ast2600_search_clock_config(&mpll)) { 586 printf("error!! unable to find valid DDR clock setting\n"); 587 return 0; 588 } 589 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 590 591 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 592 } 593 594 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 595 { 596 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 597 598 ulong new_rate; 599 switch (clk->id) { 600 case ASPEED_CLK_MPLL: 601 new_rate = ast2600_configure_ddr(priv->scu, rate); 602 break; 603 default: 604 return -ENOENT; 605 } 606 607 return new_rate; 608 } 609 610 #define SCU_CLKSTOP_MAC1 (20) 611 #define SCU_CLKSTOP_MAC2 (21) 612 #define SCU_CLKSTOP_MAC3 (20) 613 #define SCU_CLKSTOP_MAC4 (21) 614 615 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 616 { 617 /* scu340[25:0]: 1G default delay */ 618 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 619 MAC_DEF_DELAY_1G); 620 621 /* set 100M/10M default delay */ 622 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 623 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 624 625 /* MAC AHB = HPLL / 6 */ 626 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 627 628 return 0; 629 } 630 631 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 632 { 633 634 /* 635 * scu350[31] RGMII 125M source: 0 = from IO pin 636 * scu350[25:0] MAC 1G delay 637 */ 638 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 639 MAC34_DEF_DELAY_1G); 640 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 641 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 642 643 /* 644 * clock source seletion and divider 645 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 646 * scu310[18:16] : RMII 50M = HCLK_200M / 4 647 */ 648 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 649 ((0x0 << 24) | (0x3 << 16))); 650 651 /* 652 * set driving strength 653 * scu458[3:2] : MAC4 driving strength 654 * scu458[1:0] : MAC3 driving strength 655 */ 656 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 657 (0x3 << 2) | (0x3 << 0)); 658 659 return 0; 660 } 661 662 /** 663 * ast2600 RGMII clock source tree 664 * 665 * 125M from external PAD -------->|\ 666 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 667 * | |---->| divider |---->|/ + 668 * EPLL -->|/ | 669 * | 670 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 671 * | 672 * +--------------------------->|\ 673 * | |----> RGMII 125M for MAC#3 & MAC#4 674 * HCLK 200M ---->|divider|---->|/ 675 * 676 * To simplify the control flow: 677 * 1. RGMII 1/2 always use EPLL as the internal clock source 678 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 679 * 680 * 125M from external PAD -------->|\ 681 * | |---->RGMII 125M for MAC#1 & MAC#2 682 * EPLL---->| divider |--->|/ + 683 * | 684 * +<--------------------|RGMIICK PAD output enable|<-------------+ 685 * | 686 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 687 */ 688 #define RGMIICK_SRC_PAD 0 689 #define RGMIICK_SRC_EPLL 1 /* recommended */ 690 #define RGMIICK_SRC_HPLL 2 691 692 #define RGMIICK_DIV2 1 693 #define RGMIICK_DIV3 2 694 #define RGMIICK_DIV4 3 695 #define RGMIICK_DIV5 4 696 #define RGMIICK_DIV6 5 697 #define RGMIICK_DIV7 6 698 #define RGMIICK_DIV8 7 /* recommended */ 699 700 #define RMIICK_DIV4 0 701 #define RMIICK_DIV8 1 702 #define RMIICK_DIV12 2 703 #define RMIICK_DIV16 3 704 #define RMIICK_DIV20 4 /* recommended */ 705 #define RMIICK_DIV24 5 706 #define RMIICK_DIV28 6 707 #define RMIICK_DIV32 7 708 709 struct ast2600_mac_clk_div { 710 u32 src; /* 0=external PAD, 1=internal PLL */ 711 u32 fin; /* divider input speed */ 712 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 713 u32 fout; /* fout = fin / n */ 714 }; 715 716 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 717 .src = ASPEED_CLK_EPLL, 718 .fin = 1000000000, 719 .n = RGMIICK_DIV8, 720 .fout = 125000000, 721 }; 722 723 struct ast2600_mac_clk_div rmii_clk_defconfig = { 724 .src = ASPEED_CLK_EPLL, 725 .fin = 1000000000, 726 .n = RMIICK_DIV20, 727 .fout = 50000000, 728 }; 729 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 730 struct ast2600_mac_clk_div *p_cfg) 731 { 732 struct ast2600_pll_desc pll; 733 734 pll.in = AST2600_CLK_IN; 735 pll.out = p_cfg->fin; 736 if (false == ast2600_search_clock_config(&pll)) { 737 printf("error!! unable to find valid ETHNET MAC clock " 738 "setting\n"); 739 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 740 pll.cfg.ext_reg); 741 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 742 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 743 return; 744 } 745 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 746 } 747 748 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 749 struct ast2600_mac_clk_div *p_cfg) 750 { 751 u32 reg_304 = readl(&p_scu->clk_sel2); 752 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 753 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 754 755 reg_340 &= ~GENMASK(31, 29); 756 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 757 reg_340 |= BIT(28); 758 if ((p_cfg->src == ASPEED_CLK_EPLL) || 759 (p_cfg->src == ASPEED_CLK_HPLL)) { 760 /* 761 * re-init PLL if the current PLL output frequency doesn't match 762 * the divider setting 763 */ 764 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 765 ast2600_init_mac_pll(p_scu, p_cfg); 766 } 767 /* scu340[31]: select RGMII 125M from internal source */ 768 reg_340 |= BIT(31); 769 } 770 771 reg_304 &= ~GENMASK(23, 20); 772 773 /* set clock divider */ 774 reg_304 |= (p_cfg->n & 0x7) << 20; 775 776 /* select internal clock source */ 777 if (ASPEED_CLK_HPLL == p_cfg->src) { 778 reg_304 |= BIT(23); 779 } 780 781 /* RGMII 3/4 clock source select */ 782 reg_350 &= ~BIT(31); 783 #if 0 784 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 785 reg_350 |= BIT(31); 786 } 787 788 /* set clock divider */ 789 reg_310 &= ~GENMASK(22, 20); 790 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 791 #endif 792 793 writel(reg_304, &p_scu->clk_sel2); 794 writel(reg_340, &p_scu->mac12_clk_delay); 795 writel(reg_350, &p_scu->mac34_clk_delay); 796 } 797 798 /** 799 * ast2600 RMII/NCSI clock source tree 800 * 801 * HPLL -->|\ 802 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 803 * EPLL -->|/ 804 * 805 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 806 */ 807 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 808 struct ast2600_mac_clk_div *p_cfg) 809 { 810 u32 reg_304; 811 u32 reg_310; 812 813 if ((p_cfg->src == ASPEED_CLK_EPLL) || 814 (p_cfg->src == ASPEED_CLK_HPLL)) { 815 /* 816 * re-init PLL if the current PLL output frequency doesn't match 817 * the divider setting 818 */ 819 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 820 ast2600_init_mac_pll(p_scu, p_cfg); 821 } 822 } 823 824 reg_304 = readl(&p_scu->clk_sel2); 825 reg_310 = readl(&p_scu->clk_sel4); 826 827 reg_304 &= ~GENMASK(19, 16); 828 829 /* set RMII 1/2 clock divider */ 830 reg_304 |= (p_cfg->n & 0x7) << 16; 831 832 /* RMII clock source selection */ 833 if (ASPEED_CLK_HPLL == p_cfg->src) { 834 reg_304 |= BIT(19); 835 } 836 837 /* set RMII 3/4 clock divider */ 838 reg_310 &= ~GENMASK(18, 16); 839 reg_310 |= (0x3 << 16); 840 841 writel(reg_304, &p_scu->clk_sel2); 842 writel(reg_310, &p_scu->clk_sel4); 843 } 844 845 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 846 { 847 u32 reset_bit; 848 u32 clkstop_bit; 849 850 switch (index) { 851 case 1: 852 reset_bit = BIT(ASPEED_RESET_MAC1); 853 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 854 writel(reset_bit, &scu->sysreset_ctrl1); 855 udelay(100); 856 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 857 mdelay(10); 858 writel(reset_bit, &scu->sysreset_clr_ctrl1); 859 860 break; 861 case 2: 862 reset_bit = BIT(ASPEED_RESET_MAC2); 863 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 864 writel(reset_bit, &scu->sysreset_ctrl1); 865 udelay(100); 866 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 867 mdelay(10); 868 writel(reset_bit, &scu->sysreset_clr_ctrl1); 869 break; 870 case 3: 871 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 872 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 873 writel(reset_bit, &scu->sysreset_ctrl2); 874 udelay(100); 875 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 876 mdelay(10); 877 writel(reset_bit, &scu->sysreset_clr_ctrl2); 878 break; 879 case 4: 880 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 881 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 882 writel(reset_bit, &scu->sysreset_ctrl2); 883 udelay(100); 884 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 885 mdelay(10); 886 writel(reset_bit, &scu->sysreset_clr_ctrl2); 887 break; 888 default: 889 return -EINVAL; 890 } 891 892 return 0; 893 } 894 895 #define SCU_CLKSTOP_SDIO 4 896 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 897 { 898 u32 reset_bit; 899 u32 clkstop_bit; 900 901 reset_bit = BIT(ASPEED_RESET_SD - 32); 902 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 903 904 writel(reset_bit, &scu->sysreset_ctrl2); 905 906 udelay(100); 907 //enable clk 908 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 909 mdelay(10); 910 writel(reset_bit, &scu->sysreset_clr_ctrl2); 911 912 return 0; 913 } 914 915 #define SCU_CLKSTOP_EXTSD 31 916 #define SCU_CLK_SD_MASK (0x7 << 28) 917 #define SCU_CLK_SD_DIV(x) (x << 28) 918 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 919 920 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 921 { 922 u32 clk_sel = readl(&scu->clk_sel4); 923 u32 enableclk_bit; 924 u32 rate = 0; 925 u32 div = 0; 926 int i = 0; 927 928 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 929 930 //ast2600 sd controller max clk is 200Mhz : use apll for clock source 800/4 = 200 : controller max is 200mhz 931 rate = ast2600_get_apll_rate(scu); 932 for(i = 0; i < 8; i++) { 933 div = (i + 1) * 2; 934 if ((rate / div) <= 200000000) 935 break; 936 } 937 clk_sel &= ~SCU_CLK_SD_MASK; 938 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 939 writel(clk_sel, &scu->clk_sel4); 940 941 //enable clk 942 setbits_le32(&scu->clk_sel4, enableclk_bit); 943 944 return 0; 945 } 946 947 #define SCU_CLKSTOP_EMMC 27 948 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 949 { 950 u32 reset_bit; 951 u32 clkstop_bit; 952 953 reset_bit = BIT(ASPEED_RESET_EMMC); 954 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 955 956 writel(reset_bit, &scu->sysreset_ctrl1); 957 udelay(100); 958 //enable clk 959 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 960 mdelay(10); 961 writel(reset_bit, &scu->sysreset_clr_ctrl1); 962 963 return 0; 964 } 965 966 #define SCU_CLKSTOP_EXTEMMC 15 967 #define SCU_CLK_EMMC_MASK (0x7 << 12) 968 #define SCU_CLK_EMMC_DIV(x) (x << 12) 969 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) //AST2600A1 970 971 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 972 { 973 u32 revision_id = readl(&scu->chip_id1); 974 u32 clk_sel = readl(&scu->clk_sel1); 975 u32 enableclk_bit; 976 u32 rate = 0; 977 u32 div = 0; 978 int i = 0; 979 980 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 981 982 //ast2600 eMMC controller max clk is 200Mhz 983 /********************************************************************************************* 984 HPll -> 1/2 -- 985 \ 986 --> SCU300[11] -> SCU300[14:12] [1/N] -> EMMC12C[15:8] [1/N] --> eMMC clk 987 / 988 MPLL - ----- -> 989 *********************************************************************************************/ 990 if(((revision_id & CHIP_REVISION_ID) >> 16)) { 991 //AST2600A1 : use mpll to be clk source 992 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 993 for(i = 0; i < 8; i++) { 994 div = (i + 1) * 2; 995 if ((rate / div) <= 200000000) 996 break; 997 } 998 999 clk_sel &= ~SCU_CLK_EMMC_MASK; 1000 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1001 writel(clk_sel, &scu->clk_sel1); 1002 1003 } else { 1004 //AST2600A0 : use hpll to be clk source 1005 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1006 1007 for(i = 0; i < 8; i++) { 1008 div = (i + 1) * 4; 1009 if ((rate / div) <= 200000000) 1010 break; 1011 } 1012 1013 clk_sel &= ~SCU_CLK_EMMC_MASK; 1014 clk_sel |= SCU_CLK_EMMC_DIV(i); 1015 writel(clk_sel, &scu->clk_sel1); 1016 } 1017 1018 //enable clk 1019 setbits_le32(&scu->clk_sel1, enableclk_bit); 1020 1021 return 0; 1022 } 1023 1024 #define SCU_CLKSTOP_FSICLK 30 1025 1026 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1027 { 1028 u32 reset_bit; 1029 u32 clkstop_bit; 1030 1031 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1032 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1033 1034 /* The FSI clock is shared between masters. If it's already on 1035 * don't touch it, as that will reset the existing master. */ 1036 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1037 debug("%s: already running, not touching it\n", __func__); 1038 return 0; 1039 } 1040 1041 writel(reset_bit, &scu->sysreset_ctrl2); 1042 udelay(100); 1043 //enable clk 1044 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1045 mdelay(10); 1046 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1047 1048 return 0; 1049 } 1050 1051 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1052 { 1053 u32 reset_bit; 1054 u32 clkstop_bit; 1055 1056 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1057 clkstop_bit = BIT(14); 1058 1059 writel(reset_bit, &scu->sysreset_ctrl1); 1060 udelay(100); 1061 //enable phy clk 1062 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1063 mdelay(20); 1064 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1065 1066 return 0; 1067 } 1068 1069 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1070 { 1071 u32 reset_bit; 1072 u32 clkstop_bit; 1073 1074 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1075 clkstop_bit = BIT(7); 1076 1077 writel(reset_bit, &scu->sysreset_ctrl1); 1078 udelay(100); 1079 //enable phy clk 1080 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1081 mdelay(20); 1082 1083 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1084 1085 return 0; 1086 } 1087 1088 static int ast2600_clk_enable(struct clk *clk) 1089 { 1090 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1091 1092 switch (clk->id) { 1093 case ASPEED_CLK_GATE_MAC1CLK: 1094 ast2600_configure_mac(priv->scu, 1); 1095 break; 1096 case ASPEED_CLK_GATE_MAC2CLK: 1097 ast2600_configure_mac(priv->scu, 2); 1098 break; 1099 case ASPEED_CLK_GATE_MAC3CLK: 1100 ast2600_configure_mac(priv->scu, 3); 1101 break; 1102 case ASPEED_CLK_GATE_MAC4CLK: 1103 ast2600_configure_mac(priv->scu, 4); 1104 break; 1105 case ASPEED_CLK_GATE_SDCLK: 1106 ast2600_enable_sdclk(priv->scu); 1107 break; 1108 case ASPEED_CLK_GATE_SDEXTCLK: 1109 ast2600_enable_extsdclk(priv->scu); 1110 break; 1111 case ASPEED_CLK_GATE_EMMCCLK: 1112 ast2600_enable_emmcclk(priv->scu); 1113 break; 1114 case ASPEED_CLK_GATE_EMMCEXTCLK: 1115 ast2600_enable_extemmcclk(priv->scu); 1116 break; 1117 case ASPEED_CLK_GATE_FSICLK: 1118 ast2600_enable_fsiclk(priv->scu); 1119 break; 1120 case ASPEED_CLK_GATE_USBPORT1CLK: 1121 ast2600_enable_usbahclk(priv->scu); 1122 break; 1123 case ASPEED_CLK_GATE_USBPORT2CLK: 1124 ast2600_enable_usbbhclk(priv->scu); 1125 break; 1126 default: 1127 pr_debug("can't enable clk \n"); 1128 return -ENOENT; 1129 break; 1130 } 1131 1132 return 0; 1133 } 1134 1135 struct clk_ops ast2600_clk_ops = { 1136 .get_rate = ast2600_clk_get_rate, 1137 .set_rate = ast2600_clk_set_rate, 1138 .enable = ast2600_clk_enable, 1139 }; 1140 1141 static int ast2600_clk_probe(struct udevice *dev) 1142 { 1143 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1144 u32 uart_clk_source; 1145 1146 priv->scu = devfdt_get_addr_ptr(dev); 1147 if (IS_ERR(priv->scu)) 1148 return PTR_ERR(priv->scu); 1149 1150 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1151 0x0); 1152 1153 if(uart_clk_source) { 1154 if(uart_clk_source & GENMASK(5, 0)) 1155 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1156 if(uart_clk_source & GENMASK(12, 6)) 1157 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1158 } 1159 1160 1161 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1162 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1163 ast2600_configure_mac12_clk(priv->scu); 1164 ast2600_configure_mac34_clk(priv->scu); 1165 1166 /* RSA clock = HPLL/3 */ 1167 setbits_le32(&priv->scu->clk_sel1, BIT(19)); 1168 setbits_le32(&priv->scu->clk_sel1, BIT(27)); 1169 1170 return 0; 1171 } 1172 1173 static int ast2600_clk_bind(struct udevice *dev) 1174 { 1175 int ret; 1176 1177 /* The reset driver does not have a device node, so bind it here */ 1178 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1179 if (ret) 1180 debug("Warning: No reset driver: ret=%d\n", ret); 1181 1182 return 0; 1183 } 1184 1185 #if CONFIG_IS_ENABLED(CMD_CLK) 1186 struct aspeed_clks { 1187 ulong id; 1188 const char *name; 1189 }; 1190 1191 static struct aspeed_clks aspeed_clk_names[] = { 1192 { ASPEED_CLK_HPLL, "hpll" }, 1193 { ASPEED_CLK_MPLL, "mpll" }, 1194 { ASPEED_CLK_APLL, "apll" }, 1195 { ASPEED_CLK_EPLL, "epll" }, 1196 { ASPEED_CLK_DPLL, "dpll" }, 1197 { ASPEED_CLK_AHB, "hclk" }, 1198 { ASPEED_CLK_APB1, "pclk1" }, 1199 { ASPEED_CLK_APB2, "pclk2" }, 1200 { ASPEED_CLK_BCLK, "bclk" }, 1201 { ASPEED_CLK_UARTX, "uxclk" }, 1202 { ASPEED_CLK_HUARTX, "huxclk" }, 1203 }; 1204 1205 int soc_clk_dump(void) 1206 { 1207 struct udevice *dev; 1208 struct clk clk; 1209 unsigned long rate; 1210 int i, ret; 1211 1212 ret = uclass_get_device_by_driver(UCLASS_CLK, 1213 DM_GET_DRIVER(aspeed_scu), &dev); 1214 if (ret) 1215 return ret; 1216 1217 printf("Clk\t\tHz\n"); 1218 1219 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1220 clk.id = aspeed_clk_names[i].id; 1221 ret = clk_request(dev, &clk); 1222 if (ret < 0) { 1223 debug("%s clk_request() failed: %d\n", __func__, ret); 1224 continue; 1225 } 1226 1227 ret = clk_get_rate(&clk); 1228 rate = ret; 1229 1230 clk_free(&clk); 1231 1232 if (ret == -ENOTSUPP) { 1233 printf("clk ID %lu not supported yet\n", 1234 aspeed_clk_names[i].id); 1235 continue; 1236 } 1237 if (ret < 0) { 1238 printf("%s %lu: get_rate err: %d\n", 1239 __func__, aspeed_clk_names[i].id, ret); 1240 continue; 1241 } 1242 1243 printf("%s(%3lu):\t%lu\n", 1244 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1245 } 1246 1247 return 0; 1248 } 1249 #endif 1250 1251 static const struct udevice_id ast2600_clk_ids[] = { 1252 { .compatible = "aspeed,ast2600-scu", }, 1253 { } 1254 }; 1255 1256 U_BOOT_DRIVER(aspeed_scu) = { 1257 .name = "aspeed_scu", 1258 .id = UCLASS_CLK, 1259 .of_match = ast2600_clk_ids, 1260 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1261 .ops = &ast2600_clk_ops, 1262 .bind = ast2600_clk_bind, 1263 .probe = ast2600_clk_probe, 1264 }; 1265