1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x00410410 22 #define MAC_DEF_DELAY_100M 0x00410410 23 #define MAC_DEF_DELAY_10M 0x00410410 24 25 #define MAC34_DEF_DELAY_1G 0x00104208 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 mult = (reg.b.m + 1) / (reg.b.n + 1); 129 div = (reg.b.p + 1); 130 } 131 return ((clkin * mult)/div); 132 133 } 134 135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 136 { 137 u32 clkin = AST2600_CLK_IN; 138 u32 apll_reg = readl(&scu->a_pll_param); 139 unsigned int mult, div = 1; 140 141 if (apll_reg & BIT(20)) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 146 u32 m = (apll_reg >> 5) & 0x3f; 147 u32 od = (apll_reg >> 4) & 0x1; 148 u32 n = apll_reg & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return ((clkin * mult)/div); 154 } 155 156 static u32 ast2600_a0_axi_ahb_div_table[] = { 157 2, 2, 3, 5, 158 }; 159 160 static u32 ast2600_a1_axi_ahb_div_table[] = { 161 4, 6, 2, 4, 162 }; 163 164 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 165 { 166 u32 hw_rev = readl(&scu->chip_id0); 167 u32 hwstrap1 = readl(&scu->hwstrap1); 168 u32 axi_div = 1; 169 u32 ahb_div = 0; 170 u32 rate = 0; 171 172 if(hwstrap1 & BIT(16)) 173 axi_div = 1; 174 else 175 axi_div = 2; 176 177 if (hw_rev & BIT(16)) 178 ahb_div = ast2600_a1_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 179 else 180 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 181 182 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 183 184 return (rate / axi_div / ahb_div); 185 } 186 187 static u32 ast2600_hpll_pclk1_div_table[] = { 188 4, 8, 12, 16, 20, 24, 28, 32, 189 }; 190 191 static u32 ast2600_hpll_pclk2_div_table[] = { 192 2, 4, 6, 8, 10, 12, 14, 16, 193 }; 194 195 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 196 { 197 u32 clk_sel1 = readl(&scu->clk_sel1); 198 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 199 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 200 201 return (rate / apb_div); 202 } 203 204 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 205 { 206 u32 clk_sel4 = readl(&scu->clk_sel4); 207 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 208 u32 rate = ast2600_get_hclk(scu); 209 210 return (rate / apb_div); 211 } 212 213 static u32 ast2600_get_uxclk_rate(struct ast2600_scu *scu) 214 { 215 u32 clk_in = 0; 216 u32 uxclk_sel = readl(&scu->clk_sel4); 217 218 uxclk_sel &= 0x3; 219 switch(uxclk_sel) { 220 case 0: 221 clk_in = ast2600_get_apll_rate(scu) / 4; 222 break; 223 case 1: 224 clk_in = ast2600_get_apll_rate(scu) / 2; 225 break; 226 case 2: 227 clk_in = ast2600_get_apll_rate(scu); 228 break; 229 case 3: 230 clk_in = ast2600_get_hclk(scu); 231 break; 232 } 233 234 return clk_in; 235 } 236 237 static u32 ast2600_get_huxclk_rate(struct ast2600_scu *scu) 238 { 239 u32 clk_in = 0; 240 u32 huclk_sel = readl(&scu->clk_sel4); 241 242 huclk_sel = ((huclk_sel >> 3) & 0x3); 243 switch(huclk_sel) { 244 case 0: 245 clk_in = ast2600_get_apll_rate(scu) / 4; 246 break; 247 case 1: 248 clk_in = ast2600_get_apll_rate(scu) / 2; 249 break; 250 case 2: 251 clk_in = ast2600_get_apll_rate(scu); 252 break; 253 case 3: 254 clk_in = ast2600_get_hclk(scu); 255 break; 256 } 257 258 return clk_in; 259 } 260 261 static u32 ast2600_get_uart_from_uxclk_rate(struct ast2600_scu *scu) 262 { 263 u32 clk_in = ast2600_get_uxclk_rate(scu); 264 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 265 unsigned int mult, div; 266 267 u32 n = (div_reg >> 8) & 0x3ff; 268 u32 r = div_reg & 0xff; 269 270 mult = r; 271 div = (n * 4); 272 return (clk_in * mult)/div; 273 } 274 275 static u32 ast2600_get_uart_from_huxclk_rate(struct ast2600_scu *scu) 276 { 277 u32 clk_in = ast2600_get_huxclk_rate(scu); 278 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 279 280 unsigned int mult, div; 281 282 u32 n = (div_reg >> 8) & 0x3ff; 283 u32 r = div_reg & 0xff; 284 285 mult = r; 286 div = (n * 4); 287 return (clk_in * mult)/div; 288 } 289 290 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 291 { 292 u32 clkin = 0; 293 u32 clk_sel = readl(&scu->clk_sel4); 294 u32 div = (clk_sel >> 28) & 0x7; 295 296 if(clk_sel & BIT(8)) { 297 clkin = ast2600_get_apll_rate(scu); 298 } else { 299 clkin = ast2600_get_hclk(scu); 300 } 301 div = (div + 1) << 1; 302 303 return (clkin / div); 304 } 305 306 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 307 { 308 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 309 u32 clk_sel = readl(&scu->clk_sel1); 310 u32 div = (clk_sel >> 12) & 0x7; 311 312 div = (div + 1) << 2; 313 314 return (clkin / div); 315 } 316 317 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 318 { 319 u32 uart_sel = readl(&scu->clk_sel4); 320 u32 uart_sel5 = readl(&scu->clk_sel5); 321 ulong uart_clk = 0; 322 323 switch(uart_idx) { 324 case 1: 325 case 2: 326 case 3: 327 case 4: 328 case 6: 329 if(uart_sel & BIT(uart_idx - 1)) 330 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 331 else 332 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 333 break; 334 case 5: //24mhz is come form usb phy 48Mhz 335 { 336 u8 uart5_clk_sel = 0; 337 //high bit 338 if (readl(&scu->misc_ctrl1) & BIT(12)) 339 uart5_clk_sel = 0x2; 340 else 341 uart5_clk_sel = 0x0; 342 343 if (readl(&scu->clk_sel2) & BIT(14)) 344 uart5_clk_sel |= 0x1; 345 346 switch(uart5_clk_sel) { 347 case 0: 348 uart_clk = 24000000; 349 break; 350 case 1: 351 uart_clk = 0; 352 break; 353 case 2: 354 uart_clk = 24000000/13; 355 break; 356 case 3: 357 uart_clk = 192000000/13; 358 break; 359 } 360 } 361 break; 362 case 7: 363 case 8: 364 case 9: 365 case 10: 366 case 11: 367 case 12: 368 case 13: 369 if(uart_sel5 & BIT(uart_idx - 1)) 370 uart_clk = ast2600_get_uart_from_uxclk_rate(scu)/13 ; 371 else 372 uart_clk = ast2600_get_uart_from_huxclk_rate(scu)/13 ; 373 break; 374 } 375 376 return uart_clk; 377 } 378 379 static ulong ast2600_clk_get_rate(struct clk *clk) 380 { 381 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 382 ulong rate = 0; 383 384 switch (clk->id) { 385 case ASPEED_CLK_HPLL: 386 case ASPEED_CLK_EPLL: 387 case ASPEED_CLK_DPLL: 388 case ASPEED_CLK_MPLL: 389 rate = ast2600_get_pll_rate(priv->scu, clk->id); 390 break; 391 case ASPEED_CLK_AHB: 392 rate = ast2600_get_hclk(priv->scu); 393 break; 394 case ASPEED_CLK_APB1: 395 rate = ast2600_get_pclk1(priv->scu); 396 break; 397 case ASPEED_CLK_APB2: 398 rate = ast2600_get_pclk2(priv->scu); 399 break; 400 case ASPEED_CLK_APLL: 401 rate = ast2600_get_apll_rate(priv->scu); 402 break; 403 case ASPEED_CLK_GATE_UART1CLK: 404 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 405 break; 406 case ASPEED_CLK_GATE_UART2CLK: 407 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 408 break; 409 case ASPEED_CLK_GATE_UART3CLK: 410 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 411 break; 412 case ASPEED_CLK_GATE_UART4CLK: 413 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 414 break; 415 case ASPEED_CLK_GATE_UART5CLK: 416 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 417 break; 418 case ASPEED_CLK_SDIO: 419 rate = ast2600_get_sdio_clk_rate(priv->scu); 420 break; 421 case ASPEED_CLK_EMMC: 422 rate = ast2600_get_emmc_clk_rate(priv->scu); 423 break; 424 default: 425 pr_debug("can't get clk rate \n"); 426 return -ENOENT; 427 break; 428 } 429 430 return rate; 431 } 432 433 /** 434 * @brief lookup PLL divider config by input/output rate 435 * @param[in] *pll - PLL descriptor 436 * @return true - if PLL divider config is found, false - else 437 * 438 * The function caller shall fill "pll->in" and "pll->out", then this function 439 * will search the lookup table to find a valid PLL divider configuration. 440 */ 441 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 442 { 443 u32 i; 444 bool is_found = false; 445 446 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 447 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 448 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 449 is_found = true; 450 pll->cfg.reg.w = def_cfg->cfg.reg.w; 451 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 452 break; 453 } 454 } 455 return is_found; 456 } 457 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 458 struct ast2600_pll_cfg *p_cfg, int pll_idx) 459 { 460 u32 addr, addr_ext; 461 u32 reg; 462 463 switch (pll_idx) { 464 case ASPEED_CLK_HPLL: 465 addr = (u32)(&scu->h_pll_param); 466 addr_ext = (u32)(&scu->h_pll_ext_param); 467 break; 468 case ASPEED_CLK_MPLL: 469 addr = (u32)(&scu->m_pll_param); 470 addr_ext = (u32)(&scu->m_pll_ext_param); 471 break; 472 case ASPEED_CLK_DPLL: 473 addr = (u32)(&scu->d_pll_param); 474 addr_ext = (u32)(&scu->d_pll_ext_param); 475 break; 476 case ASPEED_CLK_EPLL: 477 addr = (u32)(&scu->e_pll_param); 478 addr_ext = (u32)(&scu->e_pll_ext_param); 479 break; 480 default: 481 debug("unknown PLL index\n"); 482 return 1; 483 } 484 485 p_cfg->reg.b.bypass = 0; 486 p_cfg->reg.b.off = 1; 487 p_cfg->reg.b.reset = 1; 488 489 reg = readl(addr); 490 reg &= ~GENMASK(25, 0); 491 reg |= p_cfg->reg.w; 492 writel(reg, addr); 493 494 /* write extend parameter */ 495 writel(p_cfg->ext_reg, addr_ext); 496 udelay(100); 497 p_cfg->reg.b.off = 0; 498 p_cfg->reg.b.reset = 0; 499 reg &= ~GENMASK(25, 0); 500 reg |= p_cfg->reg.w; 501 writel(reg, addr); 502 503 /* polling PLL lock status */ 504 while(0 == (readl(addr_ext) & BIT(31))); 505 506 return 0; 507 } 508 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 509 { 510 struct ast2600_pll_desc mpll; 511 512 mpll.in = AST2600_CLK_IN; 513 mpll.out = rate; 514 if (false == ast2600_search_clock_config(&mpll)) { 515 printf("error!! unable to find valid DDR clock setting\n"); 516 return 0; 517 } 518 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 519 520 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 521 } 522 523 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 524 { 525 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 526 527 ulong new_rate; 528 switch (clk->id) { 529 case ASPEED_CLK_MPLL: 530 new_rate = ast2600_configure_ddr(priv->scu, rate); 531 break; 532 default: 533 return -ENOENT; 534 } 535 536 return new_rate; 537 } 538 539 #define SCU_CLKSTOP_MAC1 (20) 540 #define SCU_CLKSTOP_MAC2 (21) 541 #define SCU_CLKSTOP_MAC3 (20) 542 #define SCU_CLKSTOP_MAC4 (21) 543 544 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 545 { 546 #if 0 547 struct ast2600_pll_desc epll; 548 549 epll.in = AST2600_CLK_IN; 550 epll.out = 1000000000; 551 if (false == ast2600_search_clock_config(&epll)) { 552 printf( 553 "error!! unable to find valid ETHNET MAC clock setting\n"); 554 debug("%s: epll cfg = 0x%08x 0x%08x\n", __func__, 555 epll.cfg.reg.w, epll.cfg.ext_reg); 556 debug("%s: epll cfg = %02x %02x %02x\n", __func__, 557 epll.cfg.reg.b.m, epll.cfg.reg.b.n, epll.cfg.reg.b.p); 558 return 0; 559 } 560 ast2600_configure_pll(scu, &(epll.cfg), ASPEED_CLK_EPLL); 561 562 /* select MAC#1 and MAC#2 clock source = EPLL / 8 */ 563 clksel = readl(&scu->clk_sel2); 564 clksel &= ~BIT(23); 565 clksel |= 0x7 << 20; 566 writel(clksel, &scu->clk_sel2); 567 #endif 568 /* scu340[25:0]: 1G default delay */ 569 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 570 MAC_DEF_DELAY_1G); 571 572 /* set 100M/10M default delay */ 573 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 574 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 575 576 /* MAC AHB = HPLL / 6 */ 577 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 578 579 return 0; 580 } 581 582 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 583 { 584 ast2600_configure_mac12_clk(scu); 585 586 /* 587 * scu350[31] RGMII 125M source: 0 = from IO pin 588 * scu350[25:0] MAC 1G delay 589 */ 590 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 591 MAC34_DEF_DELAY_1G); 592 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 593 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 594 595 /* 596 * clock source seletion and divider 597 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 598 * scu310[18:16] : RMII 50M = HCLK_200M / 4 599 */ 600 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 601 ((0x0 << 24) | (0x3 << 16))); 602 603 /* 604 * set driving strength 605 * scu458[3:2] : MAC4 driving strength 606 * scu458[1:0] : MAC3 driving strength 607 */ 608 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 609 (0x2 << 2) | (0x2 << 0)); 610 611 return 0; 612 } 613 614 /** 615 * ast2600 RGMII clock source tree 616 * 617 * 125M from external PAD -------->|\ 618 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 619 * | |---->| divider |---->|/ + 620 * EPLL -->|/ | 621 * | 622 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 623 * | 624 * +--------------------------->|\ 625 * | |----> RGMII 125M for MAC#3 & MAC#4 626 * HCLK 200M ---->|divider|---->|/ 627 * 628 * To simplify the control flow: 629 * 1. RGMII 1/2 always use EPLL as the internal clock source 630 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 631 * 632 * 125M from external PAD -------->|\ 633 * | |---->RGMII 125M for MAC#1 & MAC#2 634 * EPLL---->| divider |--->|/ + 635 * | 636 * +<--------------------|RGMIICK PAD output enable|<-------------+ 637 * | 638 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 639 */ 640 #define RGMIICK_SRC_PAD 0 641 #define RGMIICK_SRC_EPLL 1 /* recommended */ 642 #define RGMIICK_SRC_HPLL 2 643 644 #define RGMIICK_DIV2 1 645 #define RGMIICK_DIV3 2 646 #define RGMIICK_DIV4 3 647 #define RGMIICK_DIV5 4 648 #define RGMIICK_DIV6 5 649 #define RGMIICK_DIV7 6 650 #define RGMIICK_DIV8 7 /* recommended */ 651 652 #define RMIICK_DIV4 0 653 #define RMIICK_DIV8 1 654 #define RMIICK_DIV12 2 655 #define RMIICK_DIV16 3 656 #define RMIICK_DIV20 4 /* recommended */ 657 #define RMIICK_DIV24 5 658 #define RMIICK_DIV28 6 659 #define RMIICK_DIV32 7 660 661 struct ast2600_mac_clk_div { 662 u32 src; /* 0=external PAD, 1=internal PLL */ 663 u32 fin; /* divider input speed */ 664 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 665 u32 fout; /* fout = fin / n */ 666 }; 667 668 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 669 .src = ASPEED_CLK_EPLL, 670 .fin = 1000000000, 671 .n = RGMIICK_DIV8, 672 .fout = 125000000, 673 }; 674 675 struct ast2600_mac_clk_div rmii_clk_defconfig = { 676 .src = ASPEED_CLK_EPLL, 677 .fin = 1000000000, 678 .n = RMIICK_DIV20, 679 .fout = 50000000, 680 }; 681 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 682 struct ast2600_mac_clk_div *p_cfg) 683 { 684 struct ast2600_pll_desc pll; 685 686 pll.in = AST2600_CLK_IN; 687 pll.out = p_cfg->fin; 688 if (false == ast2600_search_clock_config(&pll)) { 689 printf("error!! unable to find valid ETHNET MAC clock " 690 "setting\n"); 691 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 692 pll.cfg.ext_reg); 693 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 694 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 695 return; 696 } 697 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 698 } 699 700 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 701 struct ast2600_mac_clk_div *p_cfg) 702 { 703 u32 reg_304 = readl(&p_scu->clk_sel2); 704 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 705 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 706 707 reg_340 &= ~GENMASK(31, 29); 708 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 709 reg_340 |= BIT(28); 710 if ((p_cfg->src == ASPEED_CLK_EPLL) || 711 (p_cfg->src == ASPEED_CLK_HPLL)) { 712 /* 713 * re-init PLL if the current PLL output frequency doesn't match 714 * the divider setting 715 */ 716 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 717 ast2600_init_mac_pll(p_scu, p_cfg); 718 } 719 /* scu340[31]: select RGMII 125M from internal source */ 720 reg_340 |= BIT(31); 721 } 722 723 reg_304 &= ~GENMASK(23, 20); 724 725 /* set clock divider */ 726 reg_304 |= (p_cfg->n & 0x7) << 20; 727 728 /* select internal clock source */ 729 if (ASPEED_CLK_HPLL == p_cfg->src) { 730 reg_304 |= BIT(23); 731 } 732 733 /* RGMII 3/4 clock source select */ 734 reg_350 &= ~BIT(31); 735 #if 0 736 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 737 reg_350 |= BIT(31); 738 } 739 740 /* set clock divider */ 741 reg_310 &= ~GENMASK(22, 20); 742 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 743 #endif 744 745 writel(reg_304, &p_scu->clk_sel2); 746 writel(reg_340, &p_scu->mac12_clk_delay); 747 writel(reg_350, &p_scu->mac34_clk_delay); 748 } 749 750 /** 751 * ast2600 RMII/NCSI clock source tree 752 * 753 * HPLL -->|\ 754 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 755 * EPLL -->|/ 756 * 757 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 758 */ 759 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 760 struct ast2600_mac_clk_div *p_cfg) 761 { 762 u32 reg_304; 763 u32 reg_310; 764 765 if ((p_cfg->src == ASPEED_CLK_EPLL) || 766 (p_cfg->src == ASPEED_CLK_HPLL)) { 767 /* 768 * re-init PLL if the current PLL output frequency doesn't match 769 * the divider setting 770 */ 771 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 772 ast2600_init_mac_pll(p_scu, p_cfg); 773 } 774 } 775 776 reg_304 = readl(&p_scu->clk_sel2); 777 reg_310 = readl(&p_scu->clk_sel4); 778 779 reg_304 &= ~GENMASK(19, 16); 780 781 /* set RMII 1/2 clock divider */ 782 reg_304 |= (p_cfg->n & 0x7) << 16; 783 784 /* RMII clock source selection */ 785 if (ASPEED_CLK_HPLL == p_cfg->src) { 786 reg_304 |= BIT(19); 787 } 788 789 /* set RMII 3/4 clock divider */ 790 reg_310 &= ~GENMASK(18, 16); 791 reg_310 |= (0x3 << 16); 792 793 writel(reg_304, &p_scu->clk_sel2); 794 writel(reg_310, &p_scu->clk_sel4); 795 } 796 797 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 798 { 799 u32 reset_bit; 800 u32 clkstop_bit; 801 802 /* check board level setup */ 803 u32 mac_1_2_cfg = readl(&scu->hwstrap1) & GENMASK(7, 6); 804 u32 mac_3_4_cfg = readl(&scu->hwstrap2) & GENMASK(1, 0); 805 806 if ((mac_1_2_cfg == 0) && (mac_3_4_cfg != 0)) { 807 /** 808 * HW limitation: 809 * impossible to set MAC 3/4 = RGMII when MAC 1/2 = RMII 810 */ 811 printf("%s: unsupported configuration\n", __func__); 812 return -EINVAL; 813 } else if (mac_1_2_cfg | mac_3_4_cfg) { 814 /* setup RGMII clock */ 815 ast2600_init_rgmii_clk(scu, &rgmii_clk_defconfig); 816 } else { 817 /* setup RMII clock */ 818 ast2600_init_rmii_clk(scu, &rmii_clk_defconfig); 819 } 820 821 if (index < 3) 822 ast2600_configure_mac12_clk(scu); 823 else 824 ast2600_configure_mac34_clk(scu); 825 826 switch (index) { 827 case 1: 828 reset_bit = BIT(ASPEED_RESET_MAC1); 829 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 830 writel(reset_bit, &scu->sysreset_ctrl1); 831 udelay(100); 832 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 833 mdelay(10); 834 writel(reset_bit, &scu->sysreset_clr_ctrl1); 835 836 break; 837 case 2: 838 reset_bit = BIT(ASPEED_RESET_MAC2); 839 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 840 writel(reset_bit, &scu->sysreset_ctrl1); 841 udelay(100); 842 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 843 mdelay(10); 844 writel(reset_bit, &scu->sysreset_clr_ctrl1); 845 break; 846 case 3: 847 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 848 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 849 writel(reset_bit, &scu->sysreset_ctrl2); 850 udelay(100); 851 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 852 mdelay(10); 853 writel(reset_bit, &scu->sysreset_clr_ctrl2); 854 break; 855 case 4: 856 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 857 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 858 writel(reset_bit, &scu->sysreset_ctrl2); 859 udelay(100); 860 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 861 mdelay(10); 862 writel(reset_bit, &scu->sysreset_clr_ctrl2); 863 break; 864 default: 865 return -EINVAL; 866 } 867 868 return 0; 869 } 870 871 #define SCU_CLKSTOP_SDIO 4 872 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 873 { 874 u32 reset_bit; 875 u32 clkstop_bit; 876 877 reset_bit = BIT(ASPEED_RESET_SD - 32); 878 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 879 880 writel(reset_bit, &scu->sysreset_clr_ctrl2); 881 udelay(100); 882 //enable clk 883 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 884 mdelay(10); 885 writel(reset_bit, &scu->sysreset_ctrl2); 886 887 return 0; 888 } 889 890 #define SCU_CLKSTOP_EXTSD 31 891 #define SCU_CLK_SD_MASK (0x7 << 28) 892 #define SCU_CLK_SD_DIV(x) (x << 28) 893 894 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 895 { 896 u32 clk_sel = readl(&scu->clk_sel4); 897 u32 enableclk_bit; 898 899 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 900 901 //default use apll for clock source 800/2 = 400 902 clk_sel &= ~SCU_CLK_SD_MASK; 903 clk_sel |= SCU_CLK_SD_DIV(0) | BIT(8); 904 writel(clk_sel, &scu->clk_sel4); 905 906 //enable clk 907 setbits_le32(&scu->clk_sel4, enableclk_bit); 908 909 return 0; 910 } 911 912 #define SCU_CLKSTOP_EMMC 27 913 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 914 { 915 u32 reset_bit; 916 u32 clkstop_bit; 917 918 reset_bit = BIT(ASPEED_RESET_EMMC); 919 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 920 921 writel(reset_bit, &scu->sysreset_clr_ctrl1); 922 udelay(100); 923 //enable clk 924 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 925 mdelay(10); 926 writel(reset_bit, &scu->sysreset_ctrl2); 927 928 return 0; 929 } 930 931 #define SCU_CLKSTOP_EXTEMMC 15 932 #define SCU_CLK_EMMC_MASK (0x7 << 12) 933 #define SCU_CLK_EMMC_DIV(x) (x << 12) 934 935 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 936 { 937 u32 clk_sel = readl(&scu->clk_sel1); 938 u32 enableclk_bit; 939 940 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 941 942 clk_sel &= ~SCU_CLK_SD_MASK; 943 clk_sel |= SCU_CLK_SD_DIV(1); 944 writel(clk_sel, &scu->clk_sel1); 945 946 //enable clk 947 setbits_le32(&scu->clk_sel1, enableclk_bit); 948 949 return 0; 950 } 951 952 static int ast2600_clk_enable(struct clk *clk) 953 { 954 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 955 956 switch (clk->id) { 957 case ASPEED_CLK_GATE_MAC1CLK: 958 ast2600_configure_mac(priv->scu, 1); 959 break; 960 case ASPEED_CLK_GATE_MAC2CLK: 961 ast2600_configure_mac(priv->scu, 2); 962 break; 963 case ASPEED_CLK_GATE_MAC3CLK: 964 ast2600_configure_mac(priv->scu, 3); 965 break; 966 case ASPEED_CLK_GATE_MAC4CLK: 967 ast2600_configure_mac(priv->scu, 4); 968 break; 969 case ASPEED_CLK_GATE_SDCLK: 970 ast2600_enable_sdclk(priv->scu); 971 break; 972 case ASPEED_CLK_GATE_SDEXTCLK: 973 ast2600_enable_extsdclk(priv->scu); 974 break; 975 case ASPEED_CLK_GATE_EMMCCLK: 976 ast2600_enable_emmcclk(priv->scu); 977 break; 978 case ASPEED_CLK_GATE_EMMCEXTCLK: 979 ast2600_enable_extemmcclk(priv->scu); 980 break; 981 default: 982 pr_debug("can't enable clk \n"); 983 return -ENOENT; 984 break; 985 } 986 987 return 0; 988 } 989 990 struct clk_ops ast2600_clk_ops = { 991 .get_rate = ast2600_clk_get_rate, 992 .set_rate = ast2600_clk_set_rate, 993 .enable = ast2600_clk_enable, 994 }; 995 996 static int ast2600_clk_probe(struct udevice *dev) 997 { 998 struct ast2600_clk_priv *priv = dev_get_priv(dev); 999 1000 priv->scu = devfdt_get_addr_ptr(dev); 1001 if (IS_ERR(priv->scu)) 1002 return PTR_ERR(priv->scu); 1003 1004 return 0; 1005 } 1006 1007 static int ast2600_clk_bind(struct udevice *dev) 1008 { 1009 int ret; 1010 1011 /* The reset driver does not have a device node, so bind it here */ 1012 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1013 if (ret) 1014 debug("Warning: No reset driver: ret=%d\n", ret); 1015 1016 return 0; 1017 } 1018 1019 #if CONFIG_IS_ENABLED(CMD_CLK) 1020 struct aspeed_clks { 1021 ulong id; 1022 const char *name; 1023 }; 1024 1025 static struct aspeed_clks aspeed_clk_names[] = { 1026 { ASPEED_CLK_HPLL, "hpll" }, 1027 { ASPEED_CLK_MPLL, "mpll" }, 1028 { ASPEED_CLK_APLL, "apll" }, 1029 { ASPEED_CLK_EPLL, "epll" }, 1030 { ASPEED_CLK_DPLL, "dpll" }, 1031 { ASPEED_CLK_AHB, "hclk" }, 1032 { ASPEED_CLK_APB1, "pclk1" }, 1033 { ASPEED_CLK_APB2, "pclk2" }, 1034 }; 1035 1036 int soc_clk_dump(void) 1037 { 1038 struct udevice *dev; 1039 struct clk clk; 1040 unsigned long rate; 1041 int i, ret; 1042 1043 ret = uclass_get_device_by_driver(UCLASS_CLK, 1044 DM_GET_DRIVER(aspeed_scu), &dev); 1045 if (ret) 1046 return ret; 1047 1048 printf("Clk\t\tHz\n"); 1049 1050 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1051 clk.id = aspeed_clk_names[i].id; 1052 ret = clk_request(dev, &clk); 1053 if (ret < 0) { 1054 debug("%s clk_request() failed: %d\n", __func__, ret); 1055 continue; 1056 } 1057 1058 ret = clk_get_rate(&clk); 1059 rate = ret; 1060 1061 clk_free(&clk); 1062 1063 if (ret == -ENOTSUPP) { 1064 printf("clk ID %lu not supported yet\n", 1065 aspeed_clk_names[i].id); 1066 continue; 1067 } 1068 if (ret < 0) { 1069 printf("%s %lu: get_rate err: %d\n", 1070 __func__, aspeed_clk_names[i].id, ret); 1071 continue; 1072 } 1073 1074 printf("%s(%3lu):\t%lu\n", 1075 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1076 } 1077 1078 return 0; 1079 } 1080 #endif 1081 1082 static const struct udevice_id ast2600_clk_ids[] = { 1083 { .compatible = "aspeed,ast2600-scu", }, 1084 { } 1085 }; 1086 1087 U_BOOT_DRIVER(aspeed_scu) = { 1088 .name = "aspeed_scu", 1089 .id = UCLASS_CLK, 1090 .of_match = ast2600_clk_ids, 1091 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1092 .ops = &ast2600_clk_ops, 1093 .bind = ast2600_clk_bind, 1094 .probe = ast2600_clk_probe, 1095 }; 1096