1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 u32 w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 u32 ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 union mac_delay_1g { 115 u32 w; 116 struct { 117 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 118 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 119 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 120 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 121 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 122 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 123 unsigned int rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 124 unsigned int rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 125 unsigned int rgmiick_pad_dir : 1; /* bit[28] */ 126 unsigned int rmii_50m_oe_1 : 1; /* bit[29] */ 127 unsigned int rmii_50m_oe_2 : 1; /* bit[30] */ 128 unsigned int rgmii_125m_o_sel : 1; /* bit[31] */ 129 } b; 130 }; 131 132 union mac_delay_100_10 { 133 u32 w; 134 struct { 135 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 136 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 137 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 138 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 139 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 140 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 141 unsigned int reserved_0 : 6; /* bit[31:26] */ 142 } b; 143 }; 144 145 struct mac_delay_config { 146 u32 tx_delay_1000; 147 u32 rx_delay_1000; 148 u32 tx_delay_100; 149 u32 rx_delay_100; 150 u32 tx_delay_10; 151 u32 rx_delay_10; 152 }; 153 154 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 155 { 156 u32 clkin = AST2600_CLK_IN; 157 u32 pll_reg = 0; 158 unsigned int mult, div = 1; 159 160 switch (pll_idx) { 161 case ASPEED_CLK_HPLL: 162 pll_reg = readl(&scu->h_pll_param); 163 break; 164 case ASPEED_CLK_MPLL: 165 pll_reg = readl(&scu->m_pll_param); 166 break; 167 case ASPEED_CLK_DPLL: 168 pll_reg = readl(&scu->d_pll_param); 169 break; 170 case ASPEED_CLK_EPLL: 171 pll_reg = readl(&scu->e_pll_param); 172 break; 173 } 174 if (pll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 union ast2600_pll_reg reg; 180 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 181 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 182 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 183 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 184 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 185 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 186 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 187 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 188 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 189 */ 190 reg.w = pll_reg; 191 if (pll_idx == ASPEED_CLK_HPLL) { 192 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 193 194 if (hwstrap1 & BIT(10)) { 195 reg.b.m = 0x5F; 196 } else { 197 if (hwstrap1 & BIT(8)) 198 reg.b.m = 0xBF; 199 /* Otherwise keep default 0x8F */ 200 } 201 } 202 mult = (reg.b.m + 1) / (reg.b.n + 1); 203 div = (reg.b.p + 1); 204 } 205 206 return ((clkin * mult) / div); 207 } 208 209 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 210 { 211 u32 hw_rev = readl(&scu->chip_id1); 212 u32 clkin = AST2600_CLK_IN; 213 u32 apll_reg = readl(&scu->a_pll_param); 214 unsigned int mult, div = 1; 215 216 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 217 //after A2 version 218 if (apll_reg & BIT(24)) { 219 /* Pass through mode */ 220 mult = 1; 221 div = 1; 222 } else { 223 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 224 u32 m = apll_reg & 0x1fff; 225 u32 n = (apll_reg >> 13) & 0x3f; 226 u32 p = (apll_reg >> 19) & 0xf; 227 228 mult = (m + 1); 229 div = (n + 1) * (p + 1); 230 } 231 232 } else { 233 if (apll_reg & BIT(20)) { 234 /* Pass through mode */ 235 mult = 1; 236 div = 1; 237 } else { 238 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 239 u32 m = (apll_reg >> 5) & 0x3f; 240 u32 od = (apll_reg >> 4) & 0x1; 241 u32 n = apll_reg & 0xf; 242 243 mult = (2 - od) * (m + 2); 244 div = n + 1; 245 } 246 } 247 248 return ((clkin * mult) / div); 249 } 250 251 static u32 ast2600_a0_axi_ahb_div_table[] = { 252 2, 253 2, 254 3, 255 4, 256 }; 257 258 static u32 ast2600_a1_axi_ahb_div0_table[] = { 259 3, 260 2, 261 3, 262 4, 263 }; 264 265 static u32 ast2600_a1_axi_ahb_div1_table[] = { 266 3, 267 4, 268 6, 269 8, 270 }; 271 272 static u32 ast2600_a1_axi_ahb_default_table[] = { 273 3, 4, 3, 4, 2, 2, 2, 2, 274 }; 275 276 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 277 { 278 u32 hw_rev = readl(&scu->chip_id1); 279 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 280 u32 axi_div = 1; 281 u32 ahb_div = 0; 282 u32 rate = 0; 283 284 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 285 //After A0 286 if (hwstrap1 & BIT(16)) { 287 ast2600_a1_axi_ahb_div1_table[0] = 288 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 289 0x3]; 290 axi_div = 1; 291 ahb_div = 292 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 293 0x3]; 294 } else { 295 ast2600_a1_axi_ahb_div0_table[0] = 296 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 297 0x3]; 298 axi_div = 2; 299 ahb_div = 300 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 301 0x3]; 302 } 303 } else { 304 //A0 : fix axi = hpll / 2 305 axi_div = 2; 306 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 307 } 308 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 309 310 return (rate / axi_div / ahb_div); 311 } 312 313 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 314 { 315 u32 rate; 316 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 317 318 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 319 320 return (rate / ((bclk_sel + 1) * 4)); 321 } 322 323 static u32 ast2600_hpll_pclk1_div_table[] = { 324 4, 8, 12, 16, 20, 24, 28, 32, 325 }; 326 327 static u32 ast2600_hpll_pclk2_div_table[] = { 328 2, 4, 6, 8, 10, 12, 14, 16, 329 }; 330 331 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 332 { 333 u32 clk_sel1 = readl(&scu->clk_sel1); 334 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 335 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 336 337 return (rate / apb_div); 338 } 339 340 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 341 { 342 u32 clk_sel4 = readl(&scu->clk_sel4); 343 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 344 u32 rate = ast2600_get_hclk(scu); 345 346 return (rate / apb_div); 347 } 348 349 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 350 { 351 u32 clk_in = 0; 352 u32 uxclk_sel = readl(&scu->clk_sel5); 353 354 uxclk_sel &= 0x3; 355 switch (uxclk_sel) { 356 case 0: 357 clk_in = ast2600_get_apll_rate(scu) / 4; 358 break; 359 case 1: 360 clk_in = ast2600_get_apll_rate(scu) / 2; 361 break; 362 case 2: 363 clk_in = ast2600_get_apll_rate(scu); 364 break; 365 case 3: 366 clk_in = ast2600_get_hclk(scu); 367 break; 368 } 369 370 return clk_in; 371 } 372 373 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 374 { 375 u32 clk_in = 0; 376 u32 huclk_sel = readl(&scu->clk_sel5); 377 378 huclk_sel = ((huclk_sel >> 3) & 0x3); 379 switch (huclk_sel) { 380 case 0: 381 clk_in = ast2600_get_apll_rate(scu) / 4; 382 break; 383 case 1: 384 clk_in = ast2600_get_apll_rate(scu) / 2; 385 break; 386 case 2: 387 clk_in = ast2600_get_apll_rate(scu); 388 break; 389 case 3: 390 clk_in = ast2600_get_hclk(scu); 391 break; 392 } 393 394 return clk_in; 395 } 396 397 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 398 { 399 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 400 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 401 unsigned int mult, div; 402 403 u32 n = (div_reg >> 8) & 0x3ff; 404 u32 r = div_reg & 0xff; 405 406 mult = r; 407 div = (n * 2); 408 return (clk_in * mult) / div; 409 } 410 411 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 412 { 413 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 414 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 415 416 unsigned int mult, div; 417 418 u32 n = (div_reg >> 8) & 0x3ff; 419 u32 r = div_reg & 0xff; 420 421 mult = r; 422 div = (n * 2); 423 return (clk_in * mult) / div; 424 } 425 426 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 427 { 428 u32 clkin = 0; 429 u32 clk_sel = readl(&scu->clk_sel4); 430 u32 div = (clk_sel >> 28) & 0x7; 431 432 if (clk_sel & BIT(8)) 433 clkin = ast2600_get_apll_rate(scu); 434 else 435 clkin = ast2600_get_hclk(scu); 436 437 div = (div + 1) << 1; 438 439 return (clkin / div); 440 } 441 442 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 443 { 444 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 445 u32 clk_sel = readl(&scu->clk_sel1); 446 u32 div = (clk_sel >> 12) & 0x7; 447 448 div = (div + 1) << 2; 449 450 return (clkin / div); 451 } 452 453 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 454 { 455 u32 uart_sel = readl(&scu->clk_sel4); 456 u32 uart_sel5 = readl(&scu->clk_sel5); 457 ulong uart_clk = 0; 458 459 switch (uart_idx) { 460 case 1: 461 case 2: 462 case 3: 463 case 4: 464 case 6: 465 if (uart_sel & BIT(uart_idx - 1)) 466 uart_clk = ast2600_get_uart_huxclk_rate(scu); 467 else 468 uart_clk = ast2600_get_uart_uxclk_rate(scu); 469 break; 470 case 5: //24mhz is come form usb phy 48Mhz 471 { 472 u8 uart5_clk_sel = 0; 473 //high bit 474 if (readl(&scu->misc_ctrl1) & BIT(12)) 475 uart5_clk_sel = 0x2; 476 else 477 uart5_clk_sel = 0x0; 478 479 if (readl(&scu->clk_sel2) & BIT(14)) 480 uart5_clk_sel |= 0x1; 481 482 switch (uart5_clk_sel) { 483 case 0: 484 uart_clk = 24000000; 485 break; 486 case 1: 487 uart_clk = 192000000; 488 break; 489 case 2: 490 uart_clk = 24000000 / 13; 491 break; 492 case 3: 493 uart_clk = 192000000 / 13; 494 break; 495 } 496 } break; 497 case 7: 498 case 8: 499 case 9: 500 case 10: 501 case 11: 502 case 12: 503 case 13: 504 if (uart_sel5 & BIT(uart_idx - 1)) 505 uart_clk = ast2600_get_uart_huxclk_rate(scu); 506 else 507 uart_clk = ast2600_get_uart_uxclk_rate(scu); 508 break; 509 } 510 511 return uart_clk; 512 } 513 514 static ulong ast2600_clk_get_rate(struct clk *clk) 515 { 516 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 517 ulong rate = 0; 518 519 switch (clk->id) { 520 case ASPEED_CLK_HPLL: 521 case ASPEED_CLK_EPLL: 522 case ASPEED_CLK_DPLL: 523 case ASPEED_CLK_MPLL: 524 rate = ast2600_get_pll_rate(priv->scu, clk->id); 525 break; 526 case ASPEED_CLK_AHB: 527 rate = ast2600_get_hclk(priv->scu); 528 break; 529 case ASPEED_CLK_APB1: 530 rate = ast2600_get_pclk1(priv->scu); 531 break; 532 case ASPEED_CLK_APB2: 533 rate = ast2600_get_pclk2(priv->scu); 534 break; 535 case ASPEED_CLK_APLL: 536 rate = ast2600_get_apll_rate(priv->scu); 537 break; 538 case ASPEED_CLK_GATE_UART1CLK: 539 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 540 break; 541 case ASPEED_CLK_GATE_UART2CLK: 542 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 543 break; 544 case ASPEED_CLK_GATE_UART3CLK: 545 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 546 break; 547 case ASPEED_CLK_GATE_UART4CLK: 548 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 549 break; 550 case ASPEED_CLK_GATE_UART5CLK: 551 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 552 break; 553 case ASPEED_CLK_BCLK: 554 rate = ast2600_get_bclk_rate(priv->scu); 555 break; 556 case ASPEED_CLK_SDIO: 557 rate = ast2600_get_sdio_clk_rate(priv->scu); 558 break; 559 case ASPEED_CLK_EMMC: 560 rate = ast2600_get_emmc_clk_rate(priv->scu); 561 break; 562 case ASPEED_CLK_UARTX: 563 rate = ast2600_get_uart_uxclk_rate(priv->scu); 564 break; 565 case ASPEED_CLK_HUARTX: 566 rate = ast2600_get_uart_huxclk_rate(priv->scu); 567 break; 568 default: 569 pr_debug("can't get clk rate\n"); 570 return -ENOENT; 571 } 572 573 return rate; 574 } 575 576 /** 577 * @brief lookup PLL divider config by input/output rate 578 * @param[in] *pll - PLL descriptor 579 * @return true - if PLL divider config is found, false - else 580 * The function caller shall fill "pll->in" and "pll->out", 581 * then this function will search the lookup table 582 * to find a valid PLL divider configuration. 583 */ 584 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 585 { 586 u32 i; 587 bool is_found = false; 588 589 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 590 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 591 592 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 593 is_found = true; 594 pll->cfg.reg.w = def_cfg->cfg.reg.w; 595 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 596 break; 597 } 598 } 599 return is_found; 600 } 601 602 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 603 struct ast2600_pll_cfg *p_cfg, int pll_idx) 604 { 605 u32 addr, addr_ext; 606 u32 reg; 607 608 switch (pll_idx) { 609 case ASPEED_CLK_HPLL: 610 addr = (u32)(&scu->h_pll_param); 611 addr_ext = (u32)(&scu->h_pll_ext_param); 612 break; 613 case ASPEED_CLK_MPLL: 614 addr = (u32)(&scu->m_pll_param); 615 addr_ext = (u32)(&scu->m_pll_ext_param); 616 break; 617 case ASPEED_CLK_DPLL: 618 addr = (u32)(&scu->d_pll_param); 619 addr_ext = (u32)(&scu->d_pll_ext_param); 620 break; 621 case ASPEED_CLK_EPLL: 622 addr = (u32)(&scu->e_pll_param); 623 addr_ext = (u32)(&scu->e_pll_ext_param); 624 break; 625 default: 626 debug("unknown PLL index\n"); 627 return 1; 628 } 629 630 p_cfg->reg.b.bypass = 0; 631 p_cfg->reg.b.off = 1; 632 p_cfg->reg.b.reset = 1; 633 634 reg = readl(addr); 635 reg &= ~GENMASK(25, 0); 636 reg |= p_cfg->reg.w; 637 writel(reg, addr); 638 639 /* write extend parameter */ 640 writel(p_cfg->ext_reg, addr_ext); 641 udelay(100); 642 p_cfg->reg.b.off = 0; 643 p_cfg->reg.b.reset = 0; 644 reg &= ~GENMASK(25, 0); 645 reg |= p_cfg->reg.w; 646 writel(reg, addr); 647 while (!(readl(addr_ext) & BIT(31))) 648 ; 649 650 return 0; 651 } 652 653 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 654 { 655 struct ast2600_pll_desc mpll; 656 657 mpll.in = AST2600_CLK_IN; 658 mpll.out = rate; 659 if (ast2600_search_clock_config(&mpll) == false) { 660 printf("error!! unable to find valid DDR clock setting\n"); 661 return 0; 662 } 663 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 664 665 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 666 } 667 668 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 669 { 670 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 671 ulong new_rate; 672 673 switch (clk->id) { 674 case ASPEED_CLK_MPLL: 675 new_rate = ast2600_configure_ddr(priv->scu, rate); 676 break; 677 default: 678 return -ENOENT; 679 } 680 681 return new_rate; 682 } 683 684 #define SCU_CLKSTOP_MAC1 (20) 685 #define SCU_CLKSTOP_MAC2 (21) 686 #define SCU_CLKSTOP_MAC3 (20) 687 #define SCU_CLKSTOP_MAC4 (21) 688 689 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu, struct udevice *dev) 690 { 691 union mac_delay_1g reg_1g; 692 union mac_delay_100_10 reg_100, reg_10; 693 struct mac_delay_config mac1_cfg, mac2_cfg; 694 int ret; 695 696 reg_1g.w = (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)) | 697 MAC_DEF_DELAY_1G; 698 reg_100.w = MAC_DEF_DELAY_100M; 699 reg_10.w = MAC_DEF_DELAY_10M; 700 701 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, sizeof(mac1_cfg) / sizeof(u32)); 702 if (!ret) { 703 reg_1g.b.tx_delay_1 = mac1_cfg.tx_delay_1000; 704 reg_1g.b.rx_delay_1 = mac1_cfg.rx_delay_1000; 705 reg_100.b.tx_delay_1 = mac1_cfg.tx_delay_100; 706 reg_100.b.rx_delay_1 = mac1_cfg.rx_delay_100; 707 reg_10.b.tx_delay_1 = mac1_cfg.tx_delay_10; 708 reg_10.b.rx_delay_1 = mac1_cfg.rx_delay_10; 709 } 710 711 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, sizeof(mac2_cfg) / sizeof(u32)); 712 if (!ret) { 713 reg_1g.b.tx_delay_2 = mac2_cfg.tx_delay_1000; 714 reg_1g.b.rx_delay_2 = mac2_cfg.rx_delay_1000; 715 reg_100.b.tx_delay_2 = mac2_cfg.tx_delay_100; 716 reg_100.b.rx_delay_2 = mac2_cfg.rx_delay_100; 717 reg_10.b.tx_delay_2 = mac2_cfg.tx_delay_10; 718 reg_10.b.rx_delay_2 = mac2_cfg.rx_delay_10; 719 } 720 721 writel(reg_1g.w, &scu->mac12_clk_delay); 722 writel(reg_100.w, &scu->mac12_clk_delay_100M); 723 writel(reg_10.w, &scu->mac12_clk_delay_10M); 724 725 /* MAC AHB = HPLL / 6 */ 726 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 727 728 return 0; 729 } 730 731 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu, struct udevice *dev) 732 { 733 union mac_delay_1g reg_1g; 734 union mac_delay_100_10 reg_100, reg_10; 735 struct mac_delay_config mac3_cfg, mac4_cfg; 736 int ret; 737 738 /* 739 * scu350[31] RGMII 125M source: 0 = from IO pin 740 * scu350[25:0] MAC 1G delay 741 */ 742 reg_1g.w = (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)) | 743 MAC34_DEF_DELAY_1G; 744 reg_1g.b.rgmii_125m_o_sel = 0; 745 reg_100.w = MAC34_DEF_DELAY_100M; 746 reg_10.w = MAC34_DEF_DELAY_10M; 747 748 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 749 if (!ret) { 750 reg_1g.b.tx_delay_1 = mac3_cfg.tx_delay_1000; 751 reg_1g.b.rx_delay_1 = mac3_cfg.rx_delay_1000; 752 reg_100.b.tx_delay_1 = mac3_cfg.tx_delay_100; 753 reg_100.b.rx_delay_1 = mac3_cfg.rx_delay_100; 754 reg_10.b.tx_delay_1 = mac3_cfg.tx_delay_10; 755 reg_10.b.rx_delay_1 = mac3_cfg.rx_delay_10; 756 } 757 758 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 759 if (!ret) { 760 reg_1g.b.tx_delay_2 = mac4_cfg.tx_delay_1000; 761 reg_1g.b.rx_delay_2 = mac4_cfg.rx_delay_1000; 762 reg_100.b.tx_delay_2 = mac4_cfg.tx_delay_100; 763 reg_100.b.rx_delay_2 = mac4_cfg.rx_delay_100; 764 reg_10.b.tx_delay_2 = mac4_cfg.tx_delay_10; 765 reg_10.b.rx_delay_2 = mac4_cfg.rx_delay_10; 766 } 767 768 writel(reg_1g.w, &scu->mac34_clk_delay); 769 writel(reg_100.w, &scu->mac34_clk_delay_100M); 770 writel(reg_10.w, &scu->mac34_clk_delay_10M); 771 772 /* 773 * clock source seletion and divider 774 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 775 * scu310[18:16] : RMII 50M = HCLK_200M / 4 776 */ 777 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 778 ((0x0 << 24) | (0x3 << 16))); 779 780 /* 781 * set driving strength 782 * scu458[3:2] : MAC4 driving strength 783 * scu458[1:0] : MAC3 driving strength 784 */ 785 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 786 (0x3 << 2) | (0x3 << 0)); 787 788 return 0; 789 } 790 791 /** 792 * ast2600 RGMII clock source tree 793 * 125M from external PAD -------->|\ 794 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 795 * | |---->| divider |---->|/ + 796 * EPLL -->|/ | 797 * | 798 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 799 * | 800 * +--------------------------->|\ 801 * | |----> RGMII 125M for MAC#3 & MAC#4 802 * HCLK 200M ---->|divider|---->|/ 803 * To simplify the control flow: 804 * 1. RGMII 1/2 always use EPLL as the internal clock source 805 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 806 * 125M from external PAD -------->|\ 807 * | |---->RGMII 125M for MAC#1 & MAC#2 808 * EPLL---->| divider |--->|/ + 809 * | 810 * +<--------------------|RGMIICK PAD output enable|<-------------+ 811 * | 812 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 813 */ 814 #define RGMIICK_SRC_PAD 0 815 #define RGMIICK_SRC_EPLL 1 /* recommended */ 816 #define RGMIICK_SRC_HPLL 2 817 818 #define RGMIICK_DIV2 1 819 #define RGMIICK_DIV3 2 820 #define RGMIICK_DIV4 3 821 #define RGMIICK_DIV5 4 822 #define RGMIICK_DIV6 5 823 #define RGMIICK_DIV7 6 824 #define RGMIICK_DIV8 7 /* recommended */ 825 826 #define RMIICK_DIV4 0 827 #define RMIICK_DIV8 1 828 #define RMIICK_DIV12 2 829 #define RMIICK_DIV16 3 830 #define RMIICK_DIV20 4 /* recommended */ 831 #define RMIICK_DIV24 5 832 #define RMIICK_DIV28 6 833 #define RMIICK_DIV32 7 834 835 struct ast2600_mac_clk_div { 836 u32 src; /* 0=external PAD, 1=internal PLL */ 837 u32 fin; /* divider input speed */ 838 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 839 u32 fout; /* fout = fin / n */ 840 }; 841 842 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 843 .src = ASPEED_CLK_EPLL, 844 .fin = 1000000000, 845 .n = RGMIICK_DIV8, 846 .fout = 125000000, 847 }; 848 849 struct ast2600_mac_clk_div rmii_clk_defconfig = { 850 .src = ASPEED_CLK_EPLL, 851 .fin = 1000000000, 852 .n = RMIICK_DIV20, 853 .fout = 50000000, 854 }; 855 856 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 857 struct ast2600_mac_clk_div *p_cfg) 858 { 859 struct ast2600_pll_desc pll; 860 861 pll.in = AST2600_CLK_IN; 862 pll.out = p_cfg->fin; 863 if (ast2600_search_clock_config(&pll) == false) { 864 pr_err("unable to find valid ETHNET MAC clock setting\n"); 865 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 866 pll.cfg.ext_reg); 867 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 868 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 869 return; 870 } 871 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 872 } 873 874 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 875 struct ast2600_mac_clk_div *p_cfg) 876 { 877 u32 reg_304 = readl(&p_scu->clk_sel2); 878 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 879 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 880 881 reg_340 &= ~GENMASK(31, 29); 882 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 883 reg_340 |= BIT(28); 884 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 885 /* 886 * re-init PLL if the current PLL output frequency doesn't match 887 * the divider setting 888 */ 889 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 890 ast2600_init_mac_pll(p_scu, p_cfg); 891 /* scu340[31]: select RGMII 125M from internal source */ 892 reg_340 |= BIT(31); 893 } 894 895 reg_304 &= ~GENMASK(23, 20); 896 897 /* set clock divider */ 898 reg_304 |= (p_cfg->n & 0x7) << 20; 899 900 /* select internal clock source */ 901 if (p_cfg->src == ASPEED_CLK_HPLL) 902 reg_304 |= BIT(23); 903 904 /* RGMII 3/4 clock source select */ 905 reg_350 &= ~BIT(31); 906 907 writel(reg_304, &p_scu->clk_sel2); 908 writel(reg_340, &p_scu->mac12_clk_delay); 909 writel(reg_350, &p_scu->mac34_clk_delay); 910 } 911 912 /** 913 * ast2600 RMII/NCSI clock source tree 914 * HPLL -->|\ 915 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 916 * EPLL -->|/ 917 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 918 */ 919 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 920 struct ast2600_mac_clk_div *p_cfg) 921 { 922 u32 reg_304; 923 u32 reg_310; 924 925 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 926 /* 927 * re-init PLL if the current PLL output frequency doesn't match 928 * the divider setting 929 */ 930 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 931 ast2600_init_mac_pll(p_scu, p_cfg); 932 } 933 934 reg_304 = readl(&p_scu->clk_sel2); 935 reg_310 = readl(&p_scu->clk_sel4); 936 937 reg_304 &= ~GENMASK(19, 16); 938 939 /* set RMII 1/2 clock divider */ 940 reg_304 |= (p_cfg->n & 0x7) << 16; 941 942 /* RMII clock source selection */ 943 if (p_cfg->src == ASPEED_CLK_HPLL) 944 reg_304 |= BIT(19); 945 946 /* set RMII 3/4 clock divider */ 947 reg_310 &= ~GENMASK(18, 16); 948 reg_310 |= (0x3 << 16); 949 950 writel(reg_304, &p_scu->clk_sel2); 951 writel(reg_310, &p_scu->clk_sel4); 952 } 953 954 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 955 { 956 u32 reset_bit; 957 u32 clkstop_bit; 958 959 switch (index) { 960 case 1: 961 reset_bit = BIT(ASPEED_RESET_MAC1); 962 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 963 writel(reset_bit, &scu->sysreset_ctrl1); 964 udelay(100); 965 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 966 mdelay(10); 967 writel(reset_bit, &scu->sysreset_clr_ctrl1); 968 break; 969 case 2: 970 reset_bit = BIT(ASPEED_RESET_MAC2); 971 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 972 writel(reset_bit, &scu->sysreset_ctrl1); 973 udelay(100); 974 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 975 mdelay(10); 976 writel(reset_bit, &scu->sysreset_clr_ctrl1); 977 break; 978 case 3: 979 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 980 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 981 writel(reset_bit, &scu->sysreset_ctrl2); 982 udelay(100); 983 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 984 mdelay(10); 985 writel(reset_bit, &scu->sysreset_clr_ctrl2); 986 break; 987 case 4: 988 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 989 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 990 writel(reset_bit, &scu->sysreset_ctrl2); 991 udelay(100); 992 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 993 mdelay(10); 994 writel(reset_bit, &scu->sysreset_clr_ctrl2); 995 break; 996 default: 997 return -EINVAL; 998 } 999 1000 return 0; 1001 } 1002 1003 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1004 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1005 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1006 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1007 { 1008 u32 clk_sel = readl(&scu->clk_sel1); 1009 1010 /* Configure RSA clock = HPLL/3 */ 1011 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1012 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1013 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 1014 1015 writel(clk_sel, &scu->clk_sel1); 1016 } 1017 1018 #define SCU_CLKSTOP_SDIO 4 1019 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1020 { 1021 u32 reset_bit; 1022 u32 clkstop_bit; 1023 1024 reset_bit = BIT(ASPEED_RESET_SD - 32); 1025 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1026 1027 writel(reset_bit, &scu->sysreset_ctrl2); 1028 1029 udelay(100); 1030 //enable clk 1031 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1032 mdelay(10); 1033 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1034 1035 return 0; 1036 } 1037 1038 #define SCU_CLKSTOP_EXTSD 31 1039 #define SCU_CLK_SD_MASK (0x7 << 28) 1040 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1041 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1042 1043 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1044 { 1045 u32 clk_sel = readl(&scu->clk_sel4); 1046 u32 enableclk_bit; 1047 u32 rate = 0; 1048 u32 div = 0; 1049 int i = 0; 1050 1051 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1052 1053 /* ast2600 sd controller max clk is 200Mhz : 1054 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1055 */ 1056 rate = ast2600_get_apll_rate(scu); 1057 for (i = 0; i < 8; i++) { 1058 div = (i + 1) * 2; 1059 if ((rate / div) <= 200000000) 1060 break; 1061 } 1062 clk_sel &= ~SCU_CLK_SD_MASK; 1063 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1064 writel(clk_sel, &scu->clk_sel4); 1065 1066 //enable clk 1067 setbits_le32(&scu->clk_sel4, enableclk_bit); 1068 1069 return 0; 1070 } 1071 1072 #define SCU_CLKSTOP_EMMC 27 1073 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1074 { 1075 u32 reset_bit; 1076 u32 clkstop_bit; 1077 1078 reset_bit = BIT(ASPEED_RESET_EMMC); 1079 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1080 1081 writel(reset_bit, &scu->sysreset_ctrl1); 1082 udelay(100); 1083 //enable clk 1084 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1085 mdelay(10); 1086 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1087 1088 return 0; 1089 } 1090 1091 #define SCU_CLKSTOP_EXTEMMC 15 1092 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1093 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1094 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1095 1096 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1097 { 1098 u32 revision_id = readl(&scu->chip_id1); 1099 u32 clk_sel = readl(&scu->clk_sel1); 1100 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1101 u32 rate = 0; 1102 u32 div = 0; 1103 int i = 0; 1104 1105 /* 1106 * ast2600 eMMC controller max clk is 200Mhz 1107 * HPll->1/2->|\ 1108 * |->SCU300[11]->SCU300[14:12][1/N] + 1109 * MPLL------>|/ | 1110 * +----------------------------------------------+ 1111 * | 1112 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1113 */ 1114 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1115 //AST2600A1 : use mpll to be clk source 1116 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1117 for (i = 0; i < 8; i++) { 1118 div = (i + 1) * 2; 1119 if ((rate / div) <= 200000000) 1120 break; 1121 } 1122 1123 clk_sel &= ~SCU_CLK_EMMC_MASK; 1124 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1125 writel(clk_sel, &scu->clk_sel1); 1126 1127 } else { 1128 //AST2600A0 : use hpll to be clk source 1129 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1130 1131 for (i = 0; i < 8; i++) { 1132 div = (i + 1) * 4; 1133 if ((rate / div) <= 200000000) 1134 break; 1135 } 1136 1137 clk_sel &= ~SCU_CLK_EMMC_MASK; 1138 clk_sel |= SCU_CLK_EMMC_DIV(i); 1139 writel(clk_sel, &scu->clk_sel1); 1140 } 1141 setbits_le32(&scu->clk_sel1, enableclk_bit); 1142 1143 return 0; 1144 } 1145 1146 #define SCU_CLKSTOP_FSICLK 30 1147 1148 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1149 { 1150 u32 reset_bit; 1151 u32 clkstop_bit; 1152 1153 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1154 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1155 1156 /* The FSI clock is shared between masters. If it's already on 1157 * don't touch it, as that will reset the existing master. 1158 */ 1159 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1160 debug("%s: already running, not touching it\n", __func__); 1161 return 0; 1162 } 1163 1164 writel(reset_bit, &scu->sysreset_ctrl2); 1165 udelay(100); 1166 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1167 mdelay(10); 1168 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1169 1170 return 0; 1171 } 1172 1173 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1174 { 1175 u32 reset_bit; 1176 u32 clkstop_bit; 1177 1178 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1179 clkstop_bit = BIT(14); 1180 1181 writel(reset_bit, &scu->sysreset_ctrl1); 1182 udelay(100); 1183 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1184 mdelay(20); 1185 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1186 1187 return 0; 1188 } 1189 1190 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1191 { 1192 u32 reset_bit; 1193 u32 clkstop_bit; 1194 1195 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1196 clkstop_bit = BIT(7); 1197 1198 writel(reset_bit, &scu->sysreset_ctrl1); 1199 udelay(100); 1200 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1201 mdelay(20); 1202 1203 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1204 1205 return 0; 1206 } 1207 1208 static int ast2600_clk_enable(struct clk *clk) 1209 { 1210 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1211 1212 switch (clk->id) { 1213 case ASPEED_CLK_GATE_MAC1CLK: 1214 ast2600_configure_mac(priv->scu, 1); 1215 break; 1216 case ASPEED_CLK_GATE_MAC2CLK: 1217 ast2600_configure_mac(priv->scu, 2); 1218 break; 1219 case ASPEED_CLK_GATE_MAC3CLK: 1220 ast2600_configure_mac(priv->scu, 3); 1221 break; 1222 case ASPEED_CLK_GATE_MAC4CLK: 1223 ast2600_configure_mac(priv->scu, 4); 1224 break; 1225 case ASPEED_CLK_GATE_SDCLK: 1226 ast2600_enable_sdclk(priv->scu); 1227 break; 1228 case ASPEED_CLK_GATE_SDEXTCLK: 1229 ast2600_enable_extsdclk(priv->scu); 1230 break; 1231 case ASPEED_CLK_GATE_EMMCCLK: 1232 ast2600_enable_emmcclk(priv->scu); 1233 break; 1234 case ASPEED_CLK_GATE_EMMCEXTCLK: 1235 ast2600_enable_extemmcclk(priv->scu); 1236 break; 1237 case ASPEED_CLK_GATE_FSICLK: 1238 ast2600_enable_fsiclk(priv->scu); 1239 break; 1240 case ASPEED_CLK_GATE_USBPORT1CLK: 1241 ast2600_enable_usbahclk(priv->scu); 1242 break; 1243 case ASPEED_CLK_GATE_USBPORT2CLK: 1244 ast2600_enable_usbbhclk(priv->scu); 1245 break; 1246 default: 1247 pr_err("can't enable clk\n"); 1248 return -ENOENT; 1249 } 1250 1251 return 0; 1252 } 1253 1254 struct clk_ops ast2600_clk_ops = { 1255 .get_rate = ast2600_clk_get_rate, 1256 .set_rate = ast2600_clk_set_rate, 1257 .enable = ast2600_clk_enable, 1258 }; 1259 1260 static int ast2600_clk_probe(struct udevice *dev) 1261 { 1262 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1263 u32 uart_clk_source; 1264 1265 priv->scu = devfdt_get_addr_ptr(dev); 1266 if (IS_ERR(priv->scu)) 1267 return PTR_ERR(priv->scu); 1268 1269 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1270 1271 if (uart_clk_source) { 1272 if (uart_clk_source & GENMASK(5, 0)) 1273 setbits_le32(&priv->scu->clk_sel4, 1274 uart_clk_source & GENMASK(5, 0)); 1275 if (uart_clk_source & GENMASK(12, 6)) 1276 setbits_le32(&priv->scu->clk_sel5, 1277 uart_clk_source & GENMASK(12, 6)); 1278 } 1279 1280 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1281 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1282 ast2600_configure_mac12_clk(priv->scu, dev); 1283 ast2600_configure_mac34_clk(priv->scu, dev); 1284 ast2600_configure_rsa_ecc_clk(priv->scu); 1285 1286 return 0; 1287 } 1288 1289 static int ast2600_clk_bind(struct udevice *dev) 1290 { 1291 int ret; 1292 1293 /* The reset driver does not have a device node, so bind it here */ 1294 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1295 if (ret) 1296 debug("Warning: No reset driver: ret=%d\n", ret); 1297 1298 return 0; 1299 } 1300 1301 struct aspeed_clks { 1302 ulong id; 1303 const char *name; 1304 }; 1305 1306 static struct aspeed_clks aspeed_clk_names[] = { 1307 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1308 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1309 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1310 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1311 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1312 { ASPEED_CLK_HUARTX, "huxclk" }, 1313 }; 1314 1315 int soc_clk_dump(void) 1316 { 1317 struct udevice *dev; 1318 struct clk clk; 1319 unsigned long rate; 1320 int i, ret; 1321 1322 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1323 &dev); 1324 if (ret) 1325 return ret; 1326 1327 printf("Clk\t\tHz\n"); 1328 1329 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1330 clk.id = aspeed_clk_names[i].id; 1331 ret = clk_request(dev, &clk); 1332 if (ret < 0) { 1333 debug("%s clk_request() failed: %d\n", __func__, ret); 1334 continue; 1335 } 1336 1337 ret = clk_get_rate(&clk); 1338 rate = ret; 1339 1340 clk_free(&clk); 1341 1342 if (ret == -ENOTSUPP) { 1343 printf("clk ID %lu not supported yet\n", 1344 aspeed_clk_names[i].id); 1345 continue; 1346 } 1347 if (ret < 0) { 1348 printf("%s %lu: get_rate err: %d\n", __func__, 1349 aspeed_clk_names[i].id, ret); 1350 continue; 1351 } 1352 1353 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1354 aspeed_clk_names[i].id, rate); 1355 } 1356 1357 return 0; 1358 } 1359 1360 static const struct udevice_id ast2600_clk_ids[] = { 1361 { 1362 .compatible = "aspeed,ast2600-scu", 1363 }, 1364 {} 1365 }; 1366 1367 U_BOOT_DRIVER(aspeed_scu) = { 1368 .name = "aspeed_scu", 1369 .id = UCLASS_CLK, 1370 .of_match = ast2600_clk_ids, 1371 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1372 .ops = &ast2600_clk_ops, 1373 .bind = ast2600_clk_bind, 1374 .probe = ast2600_clk_probe, 1375 }; 1376