1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 3 * 4 * Author: Felipe Balbi <balbi@ti.com> 5 * 6 * Based on board/ti/dra7xx/evm.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <palmas.h> 13 #include <sata.h> 14 #include <usb.h> 15 #include <asm/omap_common.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/emif.h> 18 #include <asm/gpio.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/dra7xx_iodelay.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sata.h> 25 #include <asm/arch/gpio.h> 26 #include <asm/arch/omap.h> 27 #include <environment.h> 28 #include <usb.h> 29 #include <linux/usb/gadget.h> 30 #include <dwc3-uboot.h> 31 #include <dwc3-omap-uboot.h> 32 #include <ti-usb-phy-uboot.h> 33 34 #include "../common/board_detect.h" 35 #include "mux_data.h" 36 37 #define board_is_x15() board_ti_is("BBRDX15_") 38 #define board_is_am572x_evm() board_ti_is("AM572PM_") 39 #define board_is_am572x_idk() board_ti_is("AM572IDK") 40 41 #ifdef CONFIG_DRIVER_TI_CPSW 42 #include <cpsw.h> 43 #endif 44 45 DECLARE_GLOBAL_DATA_PTR; 46 47 /* GPIO 7_11 */ 48 #define GPIO_DDR_VTT_EN 203 49 50 #define SYSINFO_BOARD_NAME_MAX_LEN 45 51 52 const struct omap_sysinfo sysinfo = { 53 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 54 }; 55 56 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 57 .dmm_lisa_map_3 = 0x80740300, 58 .is_ma_present = 0x1 59 }; 60 61 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 62 { 63 *dmm_lisa_regs = &beagle_x15_lisa_regs; 64 } 65 66 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 67 .sdram_config_init = 0x61851b32, 68 .sdram_config = 0x61851b32, 69 .sdram_config2 = 0x08000000, 70 .ref_ctrl = 0x000040F1, 71 .ref_ctrl_final = 0x00001035, 72 .sdram_tim1 = 0xcccf36ab, 73 .sdram_tim2 = 0x308f7fda, 74 .sdram_tim3 = 0x409f88a8, 75 .read_idle_ctrl = 0x00050000, 76 .zq_config = 0x5007190b, 77 .temp_alert_config = 0x00000000, 78 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 79 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 80 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 81 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 82 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 83 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 84 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 85 .emif_rd_wr_lvl_rmp_win = 0x00000000, 86 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 87 .emif_rd_wr_lvl_ctl = 0x00000000, 88 .emif_rd_wr_exec_thresh = 0x00000305 89 }; 90 91 /* Ext phy ctrl regs 1-35 */ 92 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 93 0x10040100, 94 0x00910091, 95 0x00950095, 96 0x009B009B, 97 0x009E009E, 98 0x00980098, 99 0x00340034, 100 0x00350035, 101 0x00340034, 102 0x00310031, 103 0x00340034, 104 0x007F007F, 105 0x007F007F, 106 0x007F007F, 107 0x007F007F, 108 0x007F007F, 109 0x00480048, 110 0x004A004A, 111 0x00520052, 112 0x00550055, 113 0x00500050, 114 0x00000000, 115 0x00600020, 116 0x40011080, 117 0x08102040, 118 0x0, 119 0x0, 120 0x0, 121 0x0, 122 0x0, 123 0x0, 124 0x0, 125 0x0, 126 0x0, 127 0x0 128 }; 129 130 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 131 .sdram_config_init = 0x61851b32, 132 .sdram_config = 0x61851b32, 133 .sdram_config2 = 0x08000000, 134 .ref_ctrl = 0x000040F1, 135 .ref_ctrl_final = 0x00001035, 136 .sdram_tim1 = 0xcccf36b3, 137 .sdram_tim2 = 0x308f7fda, 138 .sdram_tim3 = 0x407f88a8, 139 .read_idle_ctrl = 0x00050000, 140 .zq_config = 0x5007190b, 141 .temp_alert_config = 0x00000000, 142 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 143 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 144 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 145 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 146 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 147 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 148 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 149 .emif_rd_wr_lvl_rmp_win = 0x00000000, 150 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 151 .emif_rd_wr_lvl_ctl = 0x00000000, 152 .emif_rd_wr_exec_thresh = 0x00000305 153 }; 154 155 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 156 0x10040100, 157 0x00910091, 158 0x00950095, 159 0x009B009B, 160 0x009E009E, 161 0x00980098, 162 0x00340034, 163 0x00350035, 164 0x00340034, 165 0x00310031, 166 0x00340034, 167 0x007F007F, 168 0x007F007F, 169 0x007F007F, 170 0x007F007F, 171 0x007F007F, 172 0x00480048, 173 0x004A004A, 174 0x00520052, 175 0x00550055, 176 0x00500050, 177 0x00000000, 178 0x00600020, 179 0x40011080, 180 0x08102040, 181 0x0, 182 0x0, 183 0x0, 184 0x0, 185 0x0, 186 0x0, 187 0x0, 188 0x0, 189 0x0, 190 0x0 191 }; 192 193 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 194 { 195 switch (emif_nr) { 196 case 1: 197 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 198 break; 199 case 2: 200 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 201 break; 202 } 203 } 204 205 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 206 { 207 switch (emif_nr) { 208 case 1: 209 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 210 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 211 break; 212 case 2: 213 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 214 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 215 break; 216 } 217 } 218 219 struct vcores_data beagle_x15_volts = { 220 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 221 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 222 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 223 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 224 .mpu.pmic = &tps659038, 225 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 226 227 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 228 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 229 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 230 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 231 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 232 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 233 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 234 .eve.addr = TPS659038_REG_ADDR_SMPS45, 235 .eve.pmic = &tps659038, 236 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 237 238 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 239 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 240 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 241 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 242 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 243 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 244 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 245 .gpu.addr = TPS659038_REG_ADDR_SMPS45, 246 .gpu.pmic = &tps659038, 247 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 248 249 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 250 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 251 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 252 .core.addr = TPS659038_REG_ADDR_SMPS6, 253 .core.pmic = &tps659038, 254 255 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 256 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 257 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 258 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 259 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 260 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 261 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 262 .iva.addr = TPS659038_REG_ADDR_SMPS45, 263 .iva.pmic = &tps659038, 264 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 265 }; 266 267 struct vcores_data am572x_idk_volts = { 268 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 269 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 270 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 271 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 272 .mpu.pmic = &tps659038, 273 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 274 275 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 276 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 277 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 278 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 279 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 280 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 281 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 282 .eve.addr = TPS659038_REG_ADDR_SMPS45, 283 .eve.pmic = &tps659038, 284 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 285 286 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 287 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 288 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 289 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 290 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 291 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 292 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 293 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 294 .gpu.pmic = &tps659038, 295 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 296 297 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 298 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 299 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 300 .core.addr = TPS659038_REG_ADDR_SMPS7, 301 .core.pmic = &tps659038, 302 303 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 304 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 305 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 306 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 307 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 308 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 309 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 310 .iva.addr = TPS659038_REG_ADDR_SMPS8, 311 .iva.pmic = &tps659038, 312 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 313 }; 314 315 int get_voltrail_opp(int rail_offset) 316 { 317 int opp; 318 319 switch (rail_offset) { 320 case VOLT_MPU: 321 opp = DRA7_MPU_OPP; 322 break; 323 case VOLT_CORE: 324 opp = DRA7_CORE_OPP; 325 break; 326 case VOLT_GPU: 327 opp = DRA7_GPU_OPP; 328 break; 329 case VOLT_EVE: 330 opp = DRA7_DSPEVE_OPP; 331 break; 332 case VOLT_IVA: 333 opp = DRA7_IVA_OPP; 334 break; 335 default: 336 opp = OPP_NOM; 337 } 338 339 return opp; 340 } 341 342 343 #ifdef CONFIG_SPL_BUILD 344 /* No env to setup for SPL */ 345 static inline void setup_board_eeprom_env(void) { } 346 347 /* Override function to read eeprom information */ 348 void do_board_detect(void) 349 { 350 int rc; 351 352 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 353 CONFIG_EEPROM_CHIP_ADDRESS); 354 if (rc) 355 printf("ti_i2c_eeprom_init failed %d\n", rc); 356 } 357 358 #else /* CONFIG_SPL_BUILD */ 359 360 /* Override function to read eeprom information: actual i2c read done by SPL*/ 361 void do_board_detect(void) 362 { 363 char *bname = NULL; 364 int rc; 365 366 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 367 CONFIG_EEPROM_CHIP_ADDRESS); 368 if (rc) 369 printf("ti_i2c_eeprom_init failed %d\n", rc); 370 371 if (board_is_x15()) 372 bname = "BeagleBoard X15"; 373 else if (board_is_am572x_evm()) 374 bname = "AM572x EVM"; 375 else if (board_is_am572x_idk()) 376 bname = "AM572x IDK"; 377 378 if (bname) 379 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 380 "Board: %s REV %s\n", bname, board_ti_get_rev()); 381 } 382 383 static void setup_board_eeprom_env(void) 384 { 385 char *name = "beagle_x15"; 386 int rc; 387 388 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 389 CONFIG_EEPROM_CHIP_ADDRESS); 390 if (rc) 391 goto invalid_eeprom; 392 393 if (board_is_x15()) 394 name = "beagle_x15"; 395 else if (board_is_am572x_evm()) 396 name = "am57xx_evm"; 397 else if (board_is_am572x_idk()) 398 name = "am572x_idk"; 399 else 400 printf("Unidentified board claims %s in eeprom header\n", 401 board_ti_get_name()); 402 403 invalid_eeprom: 404 set_board_info_env(name); 405 } 406 407 #endif /* CONFIG_SPL_BUILD */ 408 409 void vcores_init(void) 410 { 411 if (board_is_am572x_idk()) 412 *omap_vcores = &am572x_idk_volts; 413 else 414 *omap_vcores = &beagle_x15_volts; 415 } 416 417 void hw_data_init(void) 418 { 419 *prcm = &dra7xx_prcm; 420 *dplls_data = &dra7xx_dplls; 421 *ctrl = &dra7xx_ctrl; 422 } 423 424 int board_init(void) 425 { 426 gpmc_init(); 427 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 428 429 return 0; 430 } 431 432 int board_late_init(void) 433 { 434 setup_board_eeprom_env(); 435 436 /* 437 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 438 * This is the POWERHOLD-in-Low behavior. 439 */ 440 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 441 442 /* 443 * Default FIT boot on HS devices. Non FIT images are not allowed 444 * on HS devices. 445 */ 446 if (get_device_type() == HS_DEVICE) 447 setenv("boot_fit", "1"); 448 449 return 0; 450 } 451 452 void set_muxconf_regs(void) 453 { 454 do_set_mux32((*ctrl)->control_padconf_core_base, 455 early_padconf, ARRAY_SIZE(early_padconf)); 456 } 457 458 #ifdef CONFIG_IODELAY_RECALIBRATION 459 void recalibrate_iodelay(void) 460 { 461 const struct pad_conf_entry *pconf; 462 const struct iodelay_cfg_entry *iod; 463 int pconf_sz, iod_sz; 464 465 if (board_is_am572x_idk()) { 466 pconf = core_padconf_array_essential_am572x_idk; 467 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); 468 iod = iodelay_cfg_array_am572x_idk; 469 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); 470 } else { 471 /* Common for X15/GPEVM */ 472 pconf = core_padconf_array_essential_x15; 473 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); 474 iod = iodelay_cfg_array_x15; 475 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15); 476 } 477 478 __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz); 479 } 480 #endif 481 482 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 483 int board_mmc_init(bd_t *bis) 484 { 485 omap_mmc_init(0, 0, 0, -1, -1); 486 omap_mmc_init(1, 0, 0, -1, -1); 487 return 0; 488 } 489 #endif 490 491 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 492 int spl_start_uboot(void) 493 { 494 /* break into full u-boot on 'c' */ 495 if (serial_tstc() && serial_getc() == 'c') 496 return 1; 497 498 #ifdef CONFIG_SPL_ENV_SUPPORT 499 env_init(); 500 env_relocate_spec(); 501 if (getenv_yesno("boot_os") != 1) 502 return 1; 503 #endif 504 505 return 0; 506 } 507 #endif 508 509 #ifdef CONFIG_USB_DWC3 510 static struct dwc3_device usb_otg_ss2 = { 511 .maximum_speed = USB_SPEED_HIGH, 512 .base = DRA7_USB_OTG_SS2_BASE, 513 .tx_fifo_resize = false, 514 .index = 1, 515 }; 516 517 static struct dwc3_omap_device usb_otg_ss2_glue = { 518 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 519 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 520 .index = 1, 521 }; 522 523 static struct ti_usb_phy_device usb_phy2_device = { 524 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 525 .index = 1, 526 }; 527 528 int usb_gadget_handle_interrupts(int index) 529 { 530 u32 status; 531 532 status = dwc3_omap_uboot_interrupt_status(index); 533 if (status) 534 dwc3_uboot_handle_interrupt(index); 535 536 return 0; 537 } 538 #endif /* CONFIG_USB_DWC3 */ 539 540 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 541 int board_usb_init(int index, enum usb_init_type init) 542 { 543 enable_usb_clocks(index); 544 switch (index) { 545 case 0: 546 if (init == USB_INIT_DEVICE) { 547 printf("port %d can't be used as device\n", index); 548 disable_usb_clocks(index); 549 return -EINVAL; 550 } 551 break; 552 case 1: 553 if (init == USB_INIT_DEVICE) { 554 #ifdef CONFIG_USB_DWC3 555 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 556 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 557 ti_usb_phy_uboot_init(&usb_phy2_device); 558 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 559 dwc3_uboot_init(&usb_otg_ss2); 560 #endif 561 } else { 562 printf("port %d can't be used as host\n", index); 563 disable_usb_clocks(index); 564 return -EINVAL; 565 } 566 567 break; 568 default: 569 printf("Invalid Controller Index\n"); 570 } 571 572 return 0; 573 } 574 575 int board_usb_cleanup(int index, enum usb_init_type init) 576 { 577 #ifdef CONFIG_USB_DWC3 578 switch (index) { 579 case 0: 580 case 1: 581 if (init == USB_INIT_DEVICE) { 582 ti_usb_phy_uboot_exit(index); 583 dwc3_uboot_exit(index); 584 dwc3_omap_uboot_exit(index); 585 } 586 break; 587 default: 588 printf("Invalid Controller Index\n"); 589 } 590 #endif 591 disable_usb_clocks(index); 592 return 0; 593 } 594 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 595 596 #ifdef CONFIG_DRIVER_TI_CPSW 597 598 /* Delay value to add to calibrated value */ 599 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 600 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 601 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 602 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 603 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 604 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 605 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 606 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 607 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 608 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 609 610 static void cpsw_control(int enabled) 611 { 612 /* VTP can be added here */ 613 } 614 615 static struct cpsw_slave_data cpsw_slaves[] = { 616 { 617 .slave_reg_ofs = 0x208, 618 .sliver_reg_ofs = 0xd80, 619 .phy_addr = 1, 620 }, 621 { 622 .slave_reg_ofs = 0x308, 623 .sliver_reg_ofs = 0xdc0, 624 .phy_addr = 2, 625 }, 626 }; 627 628 static struct cpsw_platform_data cpsw_data = { 629 .mdio_base = CPSW_MDIO_BASE, 630 .cpsw_base = CPSW_BASE, 631 .mdio_div = 0xff, 632 .channels = 8, 633 .cpdma_reg_ofs = 0x800, 634 .slaves = 1, 635 .slave_data = cpsw_slaves, 636 .ale_reg_ofs = 0xd00, 637 .ale_entries = 1024, 638 .host_port_reg_ofs = 0x108, 639 .hw_stats_reg_ofs = 0x900, 640 .bd_ram_ofs = 0x2000, 641 .mac_control = (1 << 5), 642 .control = cpsw_control, 643 .host_port_num = 0, 644 .version = CPSW_CTRL_VERSION_2, 645 }; 646 647 static u64 mac_to_u64(u8 mac[6]) 648 { 649 int i; 650 u64 addr = 0; 651 652 for (i = 0; i < 6; i++) { 653 addr <<= 8; 654 addr |= mac[i]; 655 } 656 657 return addr; 658 } 659 660 static void u64_to_mac(u64 addr, u8 mac[6]) 661 { 662 mac[5] = addr; 663 mac[4] = addr >> 8; 664 mac[3] = addr >> 16; 665 mac[2] = addr >> 24; 666 mac[1] = addr >> 32; 667 mac[0] = addr >> 40; 668 } 669 670 int board_eth_init(bd_t *bis) 671 { 672 int ret; 673 uint8_t mac_addr[6]; 674 uint32_t mac_hi, mac_lo; 675 uint32_t ctrl_val; 676 int i; 677 u64 mac1, mac2; 678 u8 mac_addr1[6], mac_addr2[6]; 679 int num_macs; 680 681 /* try reading mac address from efuse */ 682 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 683 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 684 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 685 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 686 mac_addr[2] = mac_hi & 0xFF; 687 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 688 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 689 mac_addr[5] = mac_lo & 0xFF; 690 691 if (!getenv("ethaddr")) { 692 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 693 694 if (is_valid_ethaddr(mac_addr)) 695 eth_setenv_enetaddr("ethaddr", mac_addr); 696 } 697 698 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 699 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 700 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 701 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 702 mac_addr[2] = mac_hi & 0xFF; 703 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 704 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 705 mac_addr[5] = mac_lo & 0xFF; 706 707 if (!getenv("eth1addr")) { 708 if (is_valid_ethaddr(mac_addr)) 709 eth_setenv_enetaddr("eth1addr", mac_addr); 710 } 711 712 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 713 ctrl_val |= 0x22; 714 writel(ctrl_val, (*ctrl)->control_core_control_io1); 715 716 /* The phy address for the AM572x IDK are different than x15 */ 717 if (board_is_am572x_idk()) { 718 cpsw_data.slave_data[0].phy_addr = 0; 719 cpsw_data.slave_data[1].phy_addr = 1; 720 } 721 722 ret = cpsw_register(&cpsw_data); 723 if (ret < 0) 724 printf("Error %d registering CPSW switch\n", ret); 725 726 /* 727 * Export any Ethernet MAC addresses from EEPROM. 728 * On AM57xx the 2 MAC addresses define the address range 729 */ 730 board_ti_get_eth_mac_addr(0, mac_addr1); 731 board_ti_get_eth_mac_addr(1, mac_addr2); 732 733 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 734 mac1 = mac_to_u64(mac_addr1); 735 mac2 = mac_to_u64(mac_addr2); 736 737 /* must contain an address range */ 738 num_macs = mac2 - mac1 + 1; 739 /* <= 50 to protect against user programming error */ 740 if (num_macs > 0 && num_macs <= 50) { 741 for (i = 0; i < num_macs; i++) { 742 u64_to_mac(mac1 + i, mac_addr); 743 if (is_valid_ethaddr(mac_addr)) { 744 eth_setenv_enetaddr_by_index("eth", 745 i + 2, 746 mac_addr); 747 } 748 } 749 } 750 } 751 752 return ret; 753 } 754 #endif 755 756 #ifdef CONFIG_BOARD_EARLY_INIT_F 757 /* VTT regulator enable */ 758 static inline void vtt_regulator_enable(void) 759 { 760 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 761 return; 762 763 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 764 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 765 } 766 767 int board_early_init_f(void) 768 { 769 vtt_regulator_enable(); 770 return 0; 771 } 772 #endif 773 774 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 775 int ft_board_setup(void *blob, bd_t *bd) 776 { 777 ft_cpu_setup(blob, bd); 778 779 return 0; 780 } 781 #endif 782 783 #ifdef CONFIG_SPL_LOAD_FIT 784 int board_fit_config_name_match(const char *name) 785 { 786 if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15")) 787 return 0; 788 else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15")) 789 return 0; 790 else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) 791 return 0; 792 else 793 return -1; 794 } 795 #endif 796 797 #ifdef CONFIG_TI_SECURE_DEVICE 798 void board_fit_image_post_process(void **p_image, size_t *p_size) 799 { 800 secure_boot_verify_image(p_image, p_size); 801 } 802 803 void board_tee_image_process(ulong tee_image, size_t tee_size) 804 { 805 secure_tee_install((u32)tee_image); 806 } 807 808 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 809 #endif 810