1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <asm/mmu.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/fsl_law.h>
13 #include <asm/mpc85xx_gpio.h>
14 #include "ddr.h"
15
16 DECLARE_GLOBAL_DATA_PTR;
17
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)18 void fsl_ddr_board_options(memctl_options_t *popts,
19 dimm_params_t *pdimm,
20 unsigned int ctrl_num)
21 {
22 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 ulong ddr_freq;
24
25 if (ctrl_num > 1) {
26 printf("Not supported controller number %d\n", ctrl_num);
27 return;
28 }
29 if (!pdimm->n_ranks)
30 return;
31
32 pbsp = udimms[0];
33
34 /* Get clk_adjust according to the board ddr
35 * freqency and n_banks specified in board_specific_parameters table.
36 */
37 ddr_freq = get_ddr_freq(0) / 1000000;
38 while (pbsp->datarate_mhz_high) {
39 if (pbsp->n_ranks == pdimm->n_ranks &&
40 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
41 if (ddr_freq <= pbsp->datarate_mhz_high) {
42 popts->clk_adjust = pbsp->clk_adjust;
43 popts->wrlvl_start = pbsp->wrlvl_start;
44 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
45 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
46 goto found;
47 }
48 pbsp_highest = pbsp;
49 }
50 pbsp++;
51 }
52
53 if (pbsp_highest) {
54 printf("Error: board specific timing not found\n");
55 printf("for data rate %lu MT/s\n", ddr_freq);
56 printf("Trying to use the highest speed (%u) parameters\n",
57 pbsp_highest->datarate_mhz_high);
58 popts->clk_adjust = pbsp_highest->clk_adjust;
59 popts->wrlvl_start = pbsp_highest->wrlvl_start;
60 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
61 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
62 } else {
63 panic("DIMM is not supported by this board");
64 }
65 found:
66 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
67 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
68 "wrlvl_ctrl_3 0x%x\n",
69 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
70 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
71 pbsp->wrlvl_ctl_3);
72
73 /*
74 * Factors to consider for half-strength driver enable:
75 * - number of DIMMs installed
76 */
77 #ifdef CONFIG_SYS_FSL_DDR4
78 popts->half_strength_driver_enable = 1;
79 /* optimize cpo for erratum A-009942 */
80 popts->cpo_sample = 0x59;
81 #else
82 popts->half_strength_driver_enable = 0;
83 #endif
84 /*
85 * Write leveling override
86 */
87 popts->wrlvl_override = 1;
88 popts->wrlvl_sample = 0xf;
89
90 /*
91 * rtt and rtt_wr override
92 */
93 popts->rtt_override = 0;
94
95 /* Enable ZQ calibration */
96 popts->zq_en = 1;
97
98 /* DHC_EN =1, ODT = 75 Ohm */
99 #ifdef CONFIG_SYS_FSL_DDR4
100 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
101 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
102 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
103 #else
104 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
105 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
106 #endif
107 }
108
109 #if defined(CONFIG_DEEP_SLEEP)
board_mem_sleep_setup(void)110 void board_mem_sleep_setup(void)
111 {
112 void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
113
114 /* does not provide HW signals for power management */
115 clrbits_8(cpld_base + 0x17, 0x40);
116 /* Disable MCKE isolation */
117 gpio_set_value(2, 0);
118 udelay(1);
119 }
120 #endif
121
dram_init(void)122 int dram_init(void)
123 {
124 phys_size_t dram_size;
125
126 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
127 puts("Initializing....using SPD\n");
128 dram_size = fsl_ddr_sdram();
129 #else
130 dram_size = fsl_ddr_sdram_size();
131 #endif
132 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
133 dram_size *= 0x100000;
134
135 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
136 fsl_dp_resume();
137 #endif
138
139 gd->ram_size = dram_size;
140
141 return 0;
142 }
143