1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SPL specific code for Compulab CM-T335 board
4 *
5 * Board functions for Compulab CM-T335 board
6 *
7 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
8 *
9 * Author: Ilya Ledvich <ilya@compulab.co.il>
10 */
11
12 #include <common.h>
13 #include <errno.h>
14
15 #include <asm/arch/ddr_defs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/clocks_am33xx.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/hardware_am33xx.h>
20 #include <linux/sizes.h>
21
22 const struct ctrl_ioregs ioregs = {
23 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
24 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
25 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
26 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
27 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
28 };
29
30 static const struct ddr_data ddr3_data = {
31 .datardsratio0 = MT41J128MJT125_RD_DQS,
32 .datawdsratio0 = MT41J128MJT125_WR_DQS,
33 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
34 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
35 };
36
37 static const struct cmd_control ddr3_cmd_ctrl_data = {
38 .cmd0csratio = MT41J128MJT125_RATIO,
39 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
40
41 .cmd1csratio = MT41J128MJT125_RATIO,
42 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
43
44 .cmd2csratio = MT41J128MJT125_RATIO,
45 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
46 };
47
48 static struct emif_regs ddr3_emif_reg_data = {
49 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
50 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
51 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
52 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
53 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
54 .zq_config = MT41J128MJT125_ZQ_CFG,
55 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
56 PHY_EN_DYN_PWRDN,
57 };
58
59 const struct dpll_params dpll_ddr = {
60 /* M N M2 M3 M4 M5 M6 */
61 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
62
am33xx_spl_board_init(void)63 void am33xx_spl_board_init(void)
64 {
65 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
66
67 /* Get the frequency */
68 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
69
70 /* Set CORE Frequencies to OPP100 */
71 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
72
73 /* Set MPU Frequency to what we detected now that voltages are set */
74 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
75 }
76
get_dpll_ddr_params(void)77 const struct dpll_params *get_dpll_ddr_params(void)
78 {
79 return &dpll_ddr;
80 }
81
probe_sdram_size(long size)82 static void probe_sdram_size(long size)
83 {
84 switch (size) {
85 case SZ_512M:
86 ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
87 break;
88 case SZ_256M:
89 ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
90 break;
91 case SZ_128M:
92 ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
93 break;
94 default:
95 puts("Failed configuring DRAM, resetting...\n\n");
96 reset_cpu(0);
97 }
98 debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
99 config_ddr(303, &ioregs, &ddr3_data,
100 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
101 }
102
sdram_init(void)103 void sdram_init(void)
104 {
105 long size = SZ_1G;
106
107 do {
108 size = size / 2;
109 probe_sdram_size(size);
110 } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
111
112 return;
113 }
114