1b2e02d28SBin Meng /* 2b2e02d28SBin Meng * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3b2e02d28SBin Meng * 4b2e02d28SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5b2e02d28SBin Meng */ 6b2e02d28SBin Meng 7b2e02d28SBin Meng #include <common.h> 8b2e02d28SBin Meng #include <asm/io.h> 99c7dea60SBin Meng #include <asm/irq.h> 10adfe3b24SBin Meng #include <asm/pci.h> 11b2e02d28SBin Meng #include <asm/post.h> 12afbf1404SBin Meng #include <asm/arch/device.h> 139c7dea60SBin Meng #include <asm/arch/tnc.h> 141021af4dSSimon Glass #include <asm/fsp/fsp_support.h> 15b2e02d28SBin Meng #include <asm/processor.h> 16b2e02d28SBin Meng 17*9e36c53dSBin Meng static int __maybe_unused disable_igd(void) 181f124ebaSBin Meng { 19e5ffa4bbSBin Meng /* 20e5ffa4bbSBin Meng * According to Atom E6xx datasheet, setting VGA Disable (bit17) 21e5ffa4bbSBin Meng * of Graphics Controller register (offset 0x50) prevents IGD 22e5ffa4bbSBin Meng * (D2:F0) from reporting itself as a VGA display controller 23e5ffa4bbSBin Meng * class in the PCI configuration space, and should also prevent 24e5ffa4bbSBin Meng * it from responding to VGA legacy memory range and I/O addresses. 25e5ffa4bbSBin Meng * 26e5ffa4bbSBin Meng * However test result shows that with just VGA Disable bit set and 27e5ffa4bbSBin Meng * a PCIe graphics card connected to one of the PCIe controllers on 28e5ffa4bbSBin Meng * the E6xx, accessing the VGA legacy space still causes system hang. 29e5ffa4bbSBin Meng * After a number of attempts, it turns out besides VGA Disable bit, 30e5ffa4bbSBin Meng * the SDVO (D3:F0) device should be disabled to make it work. 31e5ffa4bbSBin Meng * 32e5ffa4bbSBin Meng * To simplify, use the Function Disable register (offset 0xc4) 33e5ffa4bbSBin Meng * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these 34e5ffa4bbSBin Meng * two devices will be completely disabled (invisible in the PCI 35e5ffa4bbSBin Meng * configuration space) unless a system reset is performed. 36e5ffa4bbSBin Meng */ 37e5ffa4bbSBin Meng x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); 38e5ffa4bbSBin Meng x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); 39*9e36c53dSBin Meng 40*9e36c53dSBin Meng return 0; 411f124ebaSBin Meng } 421f124ebaSBin Meng 43b2e02d28SBin Meng int arch_cpu_init(void) 44b2e02d28SBin Meng { 45adfe3b24SBin Meng int ret; 46adfe3b24SBin Meng 47b2e02d28SBin Meng post_code(POST_CPU_INIT); 48b2e02d28SBin Meng 49adfe3b24SBin Meng ret = x86_cpu_init_f(); 50adfe3b24SBin Meng if (ret) 51adfe3b24SBin Meng return ret; 52adfe3b24SBin Meng 53adfe3b24SBin Meng return 0; 54b2e02d28SBin Meng } 55afbf1404SBin Meng 561f124ebaSBin Meng int arch_early_init_r(void) 571f124ebaSBin Meng { 58*9e36c53dSBin Meng int ret = 0; 59*9e36c53dSBin Meng 601f124ebaSBin Meng #ifdef CONFIG_DISABLE_IGD 61*9e36c53dSBin Meng ret = disable_igd(); 621f124ebaSBin Meng #endif 631f124ebaSBin Meng 64*9e36c53dSBin Meng return ret; 651f124ebaSBin Meng } 66