1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #include <common.h> 8 9 void flush_dcache_range(unsigned long start, unsigned long end) 10 { 11 } 12 13 void invalidate_icache_range(unsigned long start, unsigned long end) 14 { 15 /* 16 * RISC-V does not have an instruction for invalidating parts of the 17 * instruction cache. Invalidate all of it instead. 18 */ 19 invalidate_icache_all(); 20 } 21 22 void invalidate_icache_all(void) 23 { 24 asm volatile ("fence.i" ::: "memory"); 25 } 26 27 void invalidate_dcache_range(unsigned long start, unsigned long end) 28 { 29 } 30 31 void flush_cache(unsigned long addr, unsigned long size) 32 { 33 } 34 35 void icache_enable(void) 36 { 37 } 38 39 void icache_disable(void) 40 { 41 } 42 43 int icache_status(void) 44 { 45 return 0; 46 } 47 48 void dcache_enable(void) 49 { 50 } 51 52 void dcache_disable(void) 53 { 54 } 55 56 int dcache_status(void) 57 { 58 return 0; 59 } 60