1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7 #include <common.h>
8
invalidate_icache_all(void)9 void invalidate_icache_all(void)
10 {
11 asm volatile ("fence.i" ::: "memory");
12 }
13
flush_dcache_all(void)14 __weak void flush_dcache_all(void)
15 {
16 }
17
flush_dcache_range(unsigned long start,unsigned long end)18 __weak void flush_dcache_range(unsigned long start, unsigned long end)
19 {
20 }
21
invalidate_icache_range(unsigned long start,unsigned long end)22 void invalidate_icache_range(unsigned long start, unsigned long end)
23 {
24 /*
25 * RISC-V does not have an instruction for invalidating parts of the
26 * instruction cache. Invalidate all of it instead.
27 */
28 invalidate_icache_all();
29 }
30
invalidate_dcache_range(unsigned long start,unsigned long end)31 __weak void invalidate_dcache_range(unsigned long start, unsigned long end)
32 {
33 }
34
cache_flush(void)35 void cache_flush(void)
36 {
37 invalidate_icache_all();
38 flush_dcache_all();
39 }
40
flush_cache(unsigned long addr,unsigned long size)41 void flush_cache(unsigned long addr, unsigned long size)
42 {
43 invalidate_icache_range(addr, addr + size);
44 flush_dcache_range(addr, addr + size);
45 }
46
icache_enable(void)47 __weak void icache_enable(void)
48 {
49 }
50
icache_disable(void)51 __weak void icache_disable(void)
52 {
53 }
54
icache_status(void)55 __weak int icache_status(void)
56 {
57 return 0;
58 }
59
dcache_enable(void)60 __weak void dcache_enable(void)
61 {
62 }
63
dcache_disable(void)64 __weak void dcache_disable(void)
65 {
66 }
67
dcache_status(void)68 __weak int dcache_status(void)
69 {
70 return 0;
71 }
72