1/* 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25 * 26 * The processor starts at 0xfffffffc and the code is first executed in the 27 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28 * 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <mpc85xx.h> 34#include <version.h> 35 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#undef MSR_KERNEL 45#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46 47/* 48 * Set up GOT: Global Offset Table 49 * 50 * Use r12 to access the GOT 51 */ 52 START_GOT 53 GOT_ENTRY(_GOT2_TABLE_) 54 GOT_ENTRY(_FIXUP_TABLE_) 55 56#ifndef CONFIG_NAND_SPL 57 GOT_ENTRY(_start) 58 GOT_ENTRY(_start_of_vectors) 59 GOT_ENTRY(_end_of_vectors) 60 GOT_ENTRY(transfer_to_handler) 61#endif 62 63 GOT_ENTRY(__init_end) 64 GOT_ENTRY(__bss_end__) 65 GOT_ENTRY(__bss_start) 66 END_GOT 67 68/* 69 * e500 Startup -- after reset only the last 4KB of the effective 70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71 * section is located at THIS LAST page and basically does three 72 * things: clear some registers, set up exception tables and 73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74 * continue the boot procedure. 75 76 * Once the boot rom is mapped by TLB entries we can proceed 77 * with normal startup. 78 * 79 */ 80 81 .section .bootpg,"ax" 82 .globl _start_e500 83 84_start_e500: 85 86/* clear registers/arrays not reset by hardware */ 87 88 /* L1 */ 89 li r0,2 90 mtspr L1CSR0,r0 /* invalidate d-cache */ 91 mtspr L1CSR1,r0 /* invalidate i-cache */ 92 93 mfspr r1,DBSR 94 mtspr DBSR,r1 /* Clear all valid bits */ 95 96 /* 97 * Enable L1 Caches early 98 * 99 */ 100 101#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 102 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 103 li r2,(32 + 0) 104 mtspr L1CSR2,r2 105#endif 106 107 /* Enable/invalidate the I-Cache */ 108 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 109 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 110 mtspr SPRN_L1CSR1,r2 1111: 112 mfspr r3,SPRN_L1CSR1 113 and. r1,r3,r2 114 bne 1b 115 116 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 117 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 118 mtspr SPRN_L1CSR1,r3 119 isync 1202: 121 mfspr r3,SPRN_L1CSR1 122 andi. r1,r3,L1CSR1_ICE@l 123 beq 2b 124 125 /* Enable/invalidate the D-Cache */ 126 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 127 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 128 mtspr SPRN_L1CSR0,r2 1291: 130 mfspr r3,SPRN_L1CSR0 131 and. r1,r3,r2 132 bne 1b 133 134 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 135 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 136 mtspr SPRN_L1CSR0,r3 137 isync 1382: 139 mfspr r3,SPRN_L1CSR0 140 andi. r1,r3,L1CSR0_DCE@l 141 beq 2b 142 143 /* Setup interrupt vectors */ 144 lis r1,CONFIG_SYS_MONITOR_BASE@h 145 mtspr IVPR,r1 146 147 li r1,0x0100 148 mtspr IVOR0,r1 /* 0: Critical input */ 149 li r1,0x0200 150 mtspr IVOR1,r1 /* 1: Machine check */ 151 li r1,0x0300 152 mtspr IVOR2,r1 /* 2: Data storage */ 153 li r1,0x0400 154 mtspr IVOR3,r1 /* 3: Instruction storage */ 155 li r1,0x0500 156 mtspr IVOR4,r1 /* 4: External interrupt */ 157 li r1,0x0600 158 mtspr IVOR5,r1 /* 5: Alignment */ 159 li r1,0x0700 160 mtspr IVOR6,r1 /* 6: Program check */ 161 li r1,0x0800 162 mtspr IVOR7,r1 /* 7: floating point unavailable */ 163 li r1,0x0900 164 mtspr IVOR8,r1 /* 8: System call */ 165 /* 9: Auxiliary processor unavailable(unsupported) */ 166 li r1,0x0a00 167 mtspr IVOR10,r1 /* 10: Decrementer */ 168 li r1,0x0b00 169 mtspr IVOR11,r1 /* 11: Interval timer */ 170 li r1,0x0c00 171 mtspr IVOR12,r1 /* 12: Watchdog timer */ 172 li r1,0x0d00 173 mtspr IVOR13,r1 /* 13: Data TLB error */ 174 li r1,0x0e00 175 mtspr IVOR14,r1 /* 14: Instruction TLB error */ 176 li r1,0x0f00 177 mtspr IVOR15,r1 /* 15: Debug */ 178 179 /* Clear and set up some registers. */ 180 li r0,0x0000 181 lis r1,0xffff 182 mtspr DEC,r0 /* prevent dec exceptions */ 183 mttbl r0 /* prevent fit & wdt exceptions */ 184 mttbu r0 185 mtspr TSR,r1 /* clear all timer exception status */ 186 mtspr TCR,r0 /* disable all */ 187 mtspr ESR,r0 /* clear exception syndrome register */ 188 mtspr MCSR,r0 /* machine check syndrome register */ 189 mtxer r0 /* clear integer exception register */ 190 191#ifdef CONFIG_SYS_BOOK3E_HV 192 mtspr MAS8,r0 /* make sure MAS8 is clear */ 193#endif 194 195 /* Enable Time Base and Select Time Base Clock */ 196 lis r0,HID0_EMCP@h /* Enable machine check */ 197#if defined(CONFIG_ENABLE_36BIT_PHYS) 198 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 199#endif 200#ifndef CONFIG_E500MC 201 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 202#endif 203 mtspr HID0,r0 204 205#ifndef CONFIG_E500MC 206 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 207 mfspr r3,PVR 208 andi. r3,r3, 0xff 209 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 210 blt 1f 211 /* Set MBDD bit also */ 212 ori r0, r0, HID1_MBDD@l 2131: 214 mtspr HID1,r0 215#endif 216 217 /* Enable Branch Prediction */ 218#if defined(CONFIG_BTB) 219 lis r0,BUCSR_ENABLE@h 220 ori r0,r0,BUCSR_ENABLE@l 221 mtspr SPRN_BUCSR,r0 222#endif 223 224#if defined(CONFIG_SYS_INIT_DBCR) 225 lis r1,0xffff 226 ori r1,r1,0xffff 227 mtspr DBSR,r1 /* Clear all status bits */ 228 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 229 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 230 mtspr DBCR0,r0 231#endif 232 233#ifdef CONFIG_MPC8569 234#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 235#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 236 237 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 238 * use address space which is more than 12bits, and it must be done in 239 * the 4K boot page. So we set this bit here. 240 */ 241 242 /* create a temp mapping TLB0[0] for LBCR */ 243 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 244 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 245 246 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 247 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 248 249 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 250 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 251 252 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 253 (MAS3_SX|MAS3_SW|MAS3_SR))@h 254 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 255 (MAS3_SX|MAS3_SW|MAS3_SR))@l 256 257 mtspr MAS0,r6 258 mtspr MAS1,r7 259 mtspr MAS2,r8 260 mtspr MAS3,r9 261 isync 262 msync 263 tlbwe 264 265 /* Set LBCR register */ 266 lis r4,CONFIG_SYS_LBCR_ADDR@h 267 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 268 269 lis r5,CONFIG_SYS_LBC_LBCR@h 270 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 271 stw r5,0(r4) 272 isync 273 274 /* invalidate this temp TLB */ 275 lis r4,CONFIG_SYS_LBC_ADDR@h 276 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 277 tlbivax 0,r4 278 isync 279 280#endif /* CONFIG_MPC8569 */ 281 282/* 283 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 284 * location is not where we want it. This typically happens on a 36-bit 285 * system, where we want to move CCSR to near the top of 36-bit address space. 286 * 287 * To move CCSR, we create two temporary TLBs, one for the old location, and 288 * another for the new location. On CoreNet systems, we also need to create 289 * a special, temporary LAW. 290 * 291 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 292 * long-term TLBs, so we use TLB0 here. 293 */ 294#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 295 296#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 297#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 298#endif 299 300purge_old_ccsr_tlb: 301 lis r8, CONFIG_SYS_CCSRBAR@h 302 ori r8, r8, CONFIG_SYS_CCSRBAR@l 303 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 304 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 305 306 /* 307 * In a multi-stage boot (e.g. NAND boot), a previous stage may have 308 * created a TLB for CCSR, which will interfere with our relocation 309 * code. Since we're going to create a new TLB for CCSR anyway, 310 * it should be safe to delete this old TLB here. We have to search 311 * for it, though. 312 */ 313 314 li r1, 0 315 mtspr MAS6, r1 /* Search the current address space and PID */ 316 tlbsx 0, r8 317 mfspr r1, MAS1 318 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 319 beq 1f /* Skip if no TLB found */ 320 321 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 322 mtspr MAS1, r1 323 tlbwe 3241: 325 326create_ccsr_new_tlb: 327 /* 328 * Create a TLB for the new location of CCSR. Register R8 is reserved 329 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 330 */ 331 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 332 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 333 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 334 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 335 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 336 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 337 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 338 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 339 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 340 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 341 mtspr MAS0, r0 342 mtspr MAS1, r1 343 mtspr MAS2, r2 344 mtspr MAS3, r3 345 mtspr MAS7, r7 346 isync 347 msync 348 tlbwe 349 350 /* 351 * Create a TLB for the old location of CCSR. Register R9 is reserved 352 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 353 */ 354create_ccsr_old_tlb: 355 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 356 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 357 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 358 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 359 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 360 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 361 li r7, 0 /* The default CCSR address is always a 32-bit number */ 362 mtspr MAS0, r0 363 /* MAS1 is the same as above */ 364 mtspr MAS2, r2 365 mtspr MAS3, r3 366 mtspr MAS7, r7 367 isync 368 msync 369 tlbwe 370 371#ifdef CONFIG_FSL_CORENET 372 373#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 374#define LAW_EN 0x80000000 375#define LAW_SIZE_4K 0xb 376#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 377#define CCSRAR_C 0x80000000 /* Commit */ 378 379create_temp_law: 380 /* 381 * On CoreNet systems, we create the temporary LAW using a special LAW 382 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 383 */ 384 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 385 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 386 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 387 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 388 lis r2, CCSRBAR_LAWAR@h 389 ori r2, r2, CCSRBAR_LAWAR@l 390 391 stw r0, 0xc00(r9) /* LAWBARH0 */ 392 stw r1, 0xc04(r9) /* LAWBARL0 */ 393 sync 394 stw r2, 0xc08(r9) /* LAWAR0 */ 395 396 /* 397 * Read back from LAWAR to ensure the update is complete. e500mc 398 * cores also require an isync. 399 */ 400 lwz r0, 0xc08(r9) /* LAWAR0 */ 401 isync 402 403 /* 404 * Read the current CCSRBARH and CCSRBARL using load word instructions. 405 * Follow this with an isync instruction. This forces any outstanding 406 * accesses to configuration space to completion. 407 */ 408read_old_ccsrbar: 409 lwz r0, 0(r9) /* CCSRBARH */ 410 lwz r0, 4(r9) /* CCSRBARH */ 411 isync 412 413 /* 414 * Write the new values for CCSRBARH and CCSRBARL to their old 415 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 416 * has a new value written it loads a CCSRBARH shadow register. When 417 * the CCSRBARL is written, the CCSRBARH shadow register contents 418 * along with the CCSRBARL value are loaded into the CCSRBARH and 419 * CCSRBARL registers, respectively. Follow this with a sync 420 * instruction. 421 */ 422write_new_ccsrbar: 423 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 424 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 425 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 426 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 427 lis r2, CCSRAR_C@h 428 ori r2, r2, CCSRAR_C@l 429 430 stw r0, 0(r9) /* Write to CCSRBARH */ 431 sync /* Make sure we write to CCSRBARH first */ 432 stw r1, 4(r9) /* Write to CCSRBARL */ 433 sync 434 435 /* 436 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 437 * Follow this with a sync instruction. 438 */ 439 stw r2, 8(r9) 440 sync 441 442 /* Delete the temporary LAW */ 443delete_temp_law: 444 li r1, 0 445 stw r1, 0xc08(r8) 446 sync 447 stw r1, 0xc00(r8) 448 stw r1, 0xc04(r8) 449 sync 450 451#else /* #ifdef CONFIG_FSL_CORENET */ 452 453write_new_ccsrbar: 454 /* 455 * Read the current value of CCSRBAR using a load word instruction 456 * followed by an isync. This forces all accesses to configuration 457 * space to complete. 458 */ 459 sync 460 lwz r0, 0(r9) 461 isync 462 463/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 464#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 465 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 466 467 /* Write the new value to CCSRBAR. */ 468 lis r0, CCSRBAR_PHYS_RS12@h 469 ori r0, r0, CCSRBAR_PHYS_RS12@l 470 stw r0, 0(r9) 471 sync 472 473 /* 474 * The manual says to perform a load of an address that does not 475 * access configuration space or the on-chip SRAM using an existing TLB, 476 * but that doesn't appear to be necessary. We will do the isync, 477 * though. 478 */ 479 isync 480 481 /* 482 * Read the contents of CCSRBAR from its new location, followed by 483 * another isync. 484 */ 485 lwz r0, 0(r8) 486 isync 487 488#endif /* #ifdef CONFIG_FSL_CORENET */ 489 490 /* Delete the temporary TLBs */ 491delete_temp_tlbs: 492 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 493 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 494 li r1, 0 495 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 496 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 497 mtspr MAS0, r0 498 mtspr MAS1, r1 499 mtspr MAS2, r2 500 isync 501 msync 502 tlbwe 503 504 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 505 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 506 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 507 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 508 mtspr MAS0, r0 509 mtspr MAS2, r2 510 isync 511 msync 512 tlbwe 513#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 514 515create_init_ram_area: 516 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 517 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 518 519#ifndef CONFIG_SYS_RAMBOOT 520 /* create a temp mapping in AS=1 to the 4M boot window */ 521 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 522 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 523 524 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 525 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 526 527 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 528 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 529 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 530#else 531 /* 532 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 533 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 534 */ 535 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 536 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 537 538 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 539 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 540 541 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 542 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 543#endif 544 545 mtspr MAS0,r6 546 mtspr MAS1,r7 547 mtspr MAS2,r8 548 mtspr MAS3,r9 549 isync 550 msync 551 tlbwe 552 553 /* create a temp mapping in AS=1 to the stack */ 554 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 555 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 556 557 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 558 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 559 560 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 561 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 562 563#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 564 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 565 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 566 (MAS3_SX|MAS3_SW|MAS3_SR))@h 567 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 568 (MAS3_SX|MAS3_SW|MAS3_SR))@l 569 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 570 mtspr MAS7,r10 571#else 572 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 573 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 574#endif 575 576 mtspr MAS0,r6 577 mtspr MAS1,r7 578 mtspr MAS2,r8 579 mtspr MAS3,r9 580 isync 581 msync 582 tlbwe 583 584 lis r6,MSR_IS|MSR_DS@h 585 ori r6,r6,MSR_IS|MSR_DS@l 586 lis r7,switch_as@h 587 ori r7,r7,switch_as@l 588 589 mtspr SPRN_SRR0,r7 590 mtspr SPRN_SRR1,r6 591 rfi 592 593switch_as: 594/* L1 DCache is used for initial RAM */ 595 596 /* Allocate Initial RAM in data cache. 597 */ 598 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 599 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 600 mfspr r2, L1CFG0 601 andi. r2, r2, 0x1ff 602 /* cache size * 1024 / (2 * L1 line size) */ 603 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 604 mtctr r2 605 li r0,0 6061: 607 dcbz r0,r3 608 dcbtls 0,r0,r3 609 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 610 bdnz 1b 611 612 /* Jump out the last 4K page and continue to 'normal' start */ 613#ifdef CONFIG_SYS_RAMBOOT 614 b _start_cont 615#else 616 /* Calculate absolute address in FLASH and jump there */ 617 /*--------------------------------------------------------------*/ 618 lis r3,CONFIG_SYS_MONITOR_BASE@h 619 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 620 addi r3,r3,_start_cont - _start + _START_OFFSET 621 mtlr r3 622 blr 623#endif 624 625 .text 626 .globl _start 627_start: 628 .long 0x27051956 /* U-BOOT Magic Number */ 629 .globl version_string 630version_string: 631 .ascii U_BOOT_VERSION_STRING, "\0" 632 633 .align 4 634 .globl _start_cont 635_start_cont: 636 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 637 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 638 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 639 640 li r0,0 641 stwu r0,-4(r1) 642 stwu r0,-4(r1) /* Terminate call chain */ 643 644 stwu r1,-8(r1) /* Save back chain and move SP */ 645 lis r0,RESET_VECTOR@h /* Address of reset vector */ 646 ori r0,r0,RESET_VECTOR@l 647 stwu r1,-8(r1) /* Save back chain and move SP */ 648 stw r0,+12(r1) /* Save return addr (underflow vect) */ 649 650 GET_GOT 651 bl cpu_init_early_f 652 653 /* switch back to AS = 0 */ 654 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 655 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 656 mtmsr r3 657 isync 658 659 bl cpu_init_f 660 bl board_init_f 661 isync 662 663 /* NOTREACHED - board_init_f() does not return */ 664 665#ifndef CONFIG_NAND_SPL 666 . = EXC_OFF_SYS_RESET 667 .globl _start_of_vectors 668_start_of_vectors: 669 670/* Critical input. */ 671 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 672 673/* Machine check */ 674 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 675 676/* Data Storage exception. */ 677 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 678 679/* Instruction Storage exception. */ 680 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 681 682/* External Interrupt exception. */ 683 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 684 685/* Alignment exception. */ 686 . = 0x0600 687Alignment: 688 EXCEPTION_PROLOG(SRR0, SRR1) 689 mfspr r4,DAR 690 stw r4,_DAR(r21) 691 mfspr r5,DSISR 692 stw r5,_DSISR(r21) 693 addi r3,r1,STACK_FRAME_OVERHEAD 694 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 695 696/* Program check exception */ 697 . = 0x0700 698ProgramCheck: 699 EXCEPTION_PROLOG(SRR0, SRR1) 700 addi r3,r1,STACK_FRAME_OVERHEAD 701 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 702 MSR_KERNEL, COPY_EE) 703 704 /* No FPU on MPC85xx. This exception is not supposed to happen. 705 */ 706 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 707 708 . = 0x0900 709/* 710 * r0 - SYSCALL number 711 * r3-... arguments 712 */ 713SystemCall: 714 addis r11,r0,0 /* get functions table addr */ 715 ori r11,r11,0 /* Note: this code is patched in trap_init */ 716 addis r12,r0,0 /* get number of functions */ 717 ori r12,r12,0 718 719 cmplw 0,r0,r12 720 bge 1f 721 722 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 723 add r11,r11,r0 724 lwz r11,0(r11) 725 726 li r20,0xd00-4 /* Get stack pointer */ 727 lwz r12,0(r20) 728 subi r12,r12,12 /* Adjust stack pointer */ 729 li r0,0xc00+_end_back-SystemCall 730 cmplw 0,r0,r12 /* Check stack overflow */ 731 bgt 1f 732 stw r12,0(r20) 733 734 mflr r0 735 stw r0,0(r12) 736 mfspr r0,SRR0 737 stw r0,4(r12) 738 mfspr r0,SRR1 739 stw r0,8(r12) 740 741 li r12,0xc00+_back-SystemCall 742 mtlr r12 743 mtspr SRR0,r11 744 7451: SYNC 746 rfi 747_back: 748 749 mfmsr r11 /* Disable interrupts */ 750 li r12,0 751 ori r12,r12,MSR_EE 752 andc r11,r11,r12 753 SYNC /* Some chip revs need this... */ 754 mtmsr r11 755 SYNC 756 757 li r12,0xd00-4 /* restore regs */ 758 lwz r12,0(r12) 759 760 lwz r11,0(r12) 761 mtlr r11 762 lwz r11,4(r12) 763 mtspr SRR0,r11 764 lwz r11,8(r12) 765 mtspr SRR1,r11 766 767 addi r12,r12,12 /* Adjust stack pointer */ 768 li r20,0xd00-4 769 stw r12,0(r20) 770 771 SYNC 772 rfi 773_end_back: 774 775 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 776 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 777 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 778 779 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 780 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 781 782 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 783 784 .globl _end_of_vectors 785_end_of_vectors: 786 787 788 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 789 790/* 791 * This code finishes saving the registers to the exception frame 792 * and jumps to the appropriate handler for the exception. 793 * Register r21 is pointer into trap frame, r1 has new stack pointer. 794 */ 795 .globl transfer_to_handler 796transfer_to_handler: 797 stw r22,_NIP(r21) 798 lis r22,MSR_POW@h 799 andc r23,r23,r22 800 stw r23,_MSR(r21) 801 SAVE_GPR(7, r21) 802 SAVE_4GPRS(8, r21) 803 SAVE_8GPRS(12, r21) 804 SAVE_8GPRS(24, r21) 805 806 mflr r23 807 andi. r24,r23,0x3f00 /* get vector offset */ 808 stw r24,TRAP(r21) 809 li r22,0 810 stw r22,RESULT(r21) 811 mtspr SPRG2,r22 /* r1 is now kernel sp */ 812 813 lwz r24,0(r23) /* virtual address of handler */ 814 lwz r23,4(r23) /* where to go when done */ 815 mtspr SRR0,r24 816 mtspr SRR1,r20 817 mtlr r23 818 SYNC 819 rfi /* jump to handler, enable MMU */ 820 821int_return: 822 mfmsr r28 /* Disable interrupts */ 823 li r4,0 824 ori r4,r4,MSR_EE 825 andc r28,r28,r4 826 SYNC /* Some chip revs need this... */ 827 mtmsr r28 828 SYNC 829 lwz r2,_CTR(r1) 830 lwz r0,_LINK(r1) 831 mtctr r2 832 mtlr r0 833 lwz r2,_XER(r1) 834 lwz r0,_CCR(r1) 835 mtspr XER,r2 836 mtcrf 0xFF,r0 837 REST_10GPRS(3, r1) 838 REST_10GPRS(13, r1) 839 REST_8GPRS(23, r1) 840 REST_GPR(31, r1) 841 lwz r2,_NIP(r1) /* Restore environment */ 842 lwz r0,_MSR(r1) 843 mtspr SRR0,r2 844 mtspr SRR1,r0 845 lwz r0,GPR0(r1) 846 lwz r2,GPR2(r1) 847 lwz r1,GPR1(r1) 848 SYNC 849 rfi 850 851crit_return: 852 mfmsr r28 /* Disable interrupts */ 853 li r4,0 854 ori r4,r4,MSR_EE 855 andc r28,r28,r4 856 SYNC /* Some chip revs need this... */ 857 mtmsr r28 858 SYNC 859 lwz r2,_CTR(r1) 860 lwz r0,_LINK(r1) 861 mtctr r2 862 mtlr r0 863 lwz r2,_XER(r1) 864 lwz r0,_CCR(r1) 865 mtspr XER,r2 866 mtcrf 0xFF,r0 867 REST_10GPRS(3, r1) 868 REST_10GPRS(13, r1) 869 REST_8GPRS(23, r1) 870 REST_GPR(31, r1) 871 lwz r2,_NIP(r1) /* Restore environment */ 872 lwz r0,_MSR(r1) 873 mtspr SPRN_CSRR0,r2 874 mtspr SPRN_CSRR1,r0 875 lwz r0,GPR0(r1) 876 lwz r2,GPR2(r1) 877 lwz r1,GPR1(r1) 878 SYNC 879 rfci 880 881mck_return: 882 mfmsr r28 /* Disable interrupts */ 883 li r4,0 884 ori r4,r4,MSR_EE 885 andc r28,r28,r4 886 SYNC /* Some chip revs need this... */ 887 mtmsr r28 888 SYNC 889 lwz r2,_CTR(r1) 890 lwz r0,_LINK(r1) 891 mtctr r2 892 mtlr r0 893 lwz r2,_XER(r1) 894 lwz r0,_CCR(r1) 895 mtspr XER,r2 896 mtcrf 0xFF,r0 897 REST_10GPRS(3, r1) 898 REST_10GPRS(13, r1) 899 REST_8GPRS(23, r1) 900 REST_GPR(31, r1) 901 lwz r2,_NIP(r1) /* Restore environment */ 902 lwz r0,_MSR(r1) 903 mtspr SPRN_MCSRR0,r2 904 mtspr SPRN_MCSRR1,r0 905 lwz r0,GPR0(r1) 906 lwz r2,GPR2(r1) 907 lwz r1,GPR1(r1) 908 SYNC 909 rfmci 910 911/* Cache functions. 912*/ 913.globl flush_icache 914flush_icache: 915.globl invalidate_icache 916invalidate_icache: 917 mfspr r0,L1CSR1 918 ori r0,r0,L1CSR1_ICFI 919 msync 920 isync 921 mtspr L1CSR1,r0 922 isync 923 blr /* entire I cache */ 924 925.globl invalidate_dcache 926invalidate_dcache: 927 mfspr r0,L1CSR0 928 ori r0,r0,L1CSR0_DCFI 929 msync 930 isync 931 mtspr L1CSR0,r0 932 isync 933 blr 934 935 .globl icache_enable 936icache_enable: 937 mflr r8 938 bl invalidate_icache 939 mtlr r8 940 isync 941 mfspr r4,L1CSR1 942 ori r4,r4,0x0001 943 oris r4,r4,0x0001 944 mtspr L1CSR1,r4 945 isync 946 blr 947 948 .globl icache_disable 949icache_disable: 950 mfspr r0,L1CSR1 951 lis r3,0 952 ori r3,r3,L1CSR1_ICE 953 andc r0,r0,r3 954 mtspr L1CSR1,r0 955 isync 956 blr 957 958 .globl icache_status 959icache_status: 960 mfspr r3,L1CSR1 961 andi. r3,r3,L1CSR1_ICE 962 blr 963 964 .globl dcache_enable 965dcache_enable: 966 mflr r8 967 bl invalidate_dcache 968 mtlr r8 969 isync 970 mfspr r0,L1CSR0 971 ori r0,r0,0x0001 972 oris r0,r0,0x0001 973 msync 974 isync 975 mtspr L1CSR0,r0 976 isync 977 blr 978 979 .globl dcache_disable 980dcache_disable: 981 mfspr r3,L1CSR0 982 lis r4,0 983 ori r4,r4,L1CSR0_DCE 984 andc r3,r3,r4 985 mtspr L1CSR0,r3 986 isync 987 blr 988 989 .globl dcache_status 990dcache_status: 991 mfspr r3,L1CSR0 992 andi. r3,r3,L1CSR0_DCE 993 blr 994 995 .globl get_pir 996get_pir: 997 mfspr r3,PIR 998 blr 999 1000 .globl get_pvr 1001get_pvr: 1002 mfspr r3,PVR 1003 blr 1004 1005 .globl get_svr 1006get_svr: 1007 mfspr r3,SVR 1008 blr 1009 1010 .globl wr_tcr 1011wr_tcr: 1012 mtspr TCR,r3 1013 blr 1014 1015/*------------------------------------------------------------------------------- */ 1016/* Function: in8 */ 1017/* Description: Input 8 bits */ 1018/*------------------------------------------------------------------------------- */ 1019 .globl in8 1020in8: 1021 lbz r3,0x0000(r3) 1022 blr 1023 1024/*------------------------------------------------------------------------------- */ 1025/* Function: out8 */ 1026/* Description: Output 8 bits */ 1027/*------------------------------------------------------------------------------- */ 1028 .globl out8 1029out8: 1030 stb r4,0x0000(r3) 1031 sync 1032 blr 1033 1034/*------------------------------------------------------------------------------- */ 1035/* Function: out16 */ 1036/* Description: Output 16 bits */ 1037/*------------------------------------------------------------------------------- */ 1038 .globl out16 1039out16: 1040 sth r4,0x0000(r3) 1041 sync 1042 blr 1043 1044/*------------------------------------------------------------------------------- */ 1045/* Function: out16r */ 1046/* Description: Byte reverse and output 16 bits */ 1047/*------------------------------------------------------------------------------- */ 1048 .globl out16r 1049out16r: 1050 sthbrx r4,r0,r3 1051 sync 1052 blr 1053 1054/*------------------------------------------------------------------------------- */ 1055/* Function: out32 */ 1056/* Description: Output 32 bits */ 1057/*------------------------------------------------------------------------------- */ 1058 .globl out32 1059out32: 1060 stw r4,0x0000(r3) 1061 sync 1062 blr 1063 1064/*------------------------------------------------------------------------------- */ 1065/* Function: out32r */ 1066/* Description: Byte reverse and output 32 bits */ 1067/*------------------------------------------------------------------------------- */ 1068 .globl out32r 1069out32r: 1070 stwbrx r4,r0,r3 1071 sync 1072 blr 1073 1074/*------------------------------------------------------------------------------- */ 1075/* Function: in16 */ 1076/* Description: Input 16 bits */ 1077/*------------------------------------------------------------------------------- */ 1078 .globl in16 1079in16: 1080 lhz r3,0x0000(r3) 1081 blr 1082 1083/*------------------------------------------------------------------------------- */ 1084/* Function: in16r */ 1085/* Description: Input 16 bits and byte reverse */ 1086/*------------------------------------------------------------------------------- */ 1087 .globl in16r 1088in16r: 1089 lhbrx r3,r0,r3 1090 blr 1091 1092/*------------------------------------------------------------------------------- */ 1093/* Function: in32 */ 1094/* Description: Input 32 bits */ 1095/*------------------------------------------------------------------------------- */ 1096 .globl in32 1097in32: 1098 lwz 3,0x0000(3) 1099 blr 1100 1101/*------------------------------------------------------------------------------- */ 1102/* Function: in32r */ 1103/* Description: Input 32 bits and byte reverse */ 1104/*------------------------------------------------------------------------------- */ 1105 .globl in32r 1106in32r: 1107 lwbrx r3,r0,r3 1108 blr 1109#endif /* !CONFIG_NAND_SPL */ 1110 1111/*------------------------------------------------------------------------------*/ 1112 1113/* 1114 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1115 */ 1116 .globl write_tlb 1117write_tlb: 1118 mtspr MAS0,r3 1119 mtspr MAS1,r4 1120 mtspr MAS2,r5 1121 mtspr MAS3,r6 1122#ifdef CONFIG_ENABLE_36BIT_PHYS 1123 mtspr MAS7,r7 1124#endif 1125 li r3,0 1126#ifdef CONFIG_SYS_BOOK3E_HV 1127 mtspr MAS8,r3 1128#endif 1129 isync 1130 tlbwe 1131 msync 1132 isync 1133 blr 1134 1135/* 1136 * void relocate_code (addr_sp, gd, addr_moni) 1137 * 1138 * This "function" does not return, instead it continues in RAM 1139 * after relocating the monitor code. 1140 * 1141 * r3 = dest 1142 * r4 = src 1143 * r5 = length in bytes 1144 * r6 = cachelinesize 1145 */ 1146 .globl relocate_code 1147relocate_code: 1148 mr r1,r3 /* Set new stack pointer */ 1149 mr r9,r4 /* Save copy of Init Data pointer */ 1150 mr r10,r5 /* Save copy of Destination Address */ 1151 1152 GET_GOT 1153 mr r3,r5 /* Destination Address */ 1154 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1155 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1156 lwz r5,GOT(__init_end) 1157 sub r5,r5,r4 1158 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1159 1160 /* 1161 * Fix GOT pointer: 1162 * 1163 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1164 * 1165 * Offset: 1166 */ 1167 sub r15,r10,r4 1168 1169 /* First our own GOT */ 1170 add r12,r12,r15 1171 /* the the one used by the C code */ 1172 add r30,r30,r15 1173 1174 /* 1175 * Now relocate code 1176 */ 1177 1178 cmplw cr1,r3,r4 1179 addi r0,r5,3 1180 srwi. r0,r0,2 1181 beq cr1,4f /* In place copy is not necessary */ 1182 beq 7f /* Protect against 0 count */ 1183 mtctr r0 1184 bge cr1,2f 1185 1186 la r8,-4(r4) 1187 la r7,-4(r3) 11881: lwzu r0,4(r8) 1189 stwu r0,4(r7) 1190 bdnz 1b 1191 b 4f 1192 11932: slwi r0,r0,2 1194 add r8,r4,r0 1195 add r7,r3,r0 11963: lwzu r0,-4(r8) 1197 stwu r0,-4(r7) 1198 bdnz 3b 1199 1200/* 1201 * Now flush the cache: note that we must start from a cache aligned 1202 * address. Otherwise we might miss one cache line. 1203 */ 12044: cmpwi r6,0 1205 add r5,r3,r5 1206 beq 7f /* Always flush prefetch queue in any case */ 1207 subi r0,r6,1 1208 andc r3,r3,r0 1209 mr r4,r3 12105: dcbst 0,r4 1211 add r4,r4,r6 1212 cmplw r4,r5 1213 blt 5b 1214 sync /* Wait for all dcbst to complete on bus */ 1215 mr r4,r3 12166: icbi 0,r4 1217 add r4,r4,r6 1218 cmplw r4,r5 1219 blt 6b 12207: sync /* Wait for all icbi to complete on bus */ 1221 isync 1222 1223 /* 1224 * Re-point the IVPR at RAM 1225 */ 1226 mtspr IVPR,r10 1227 1228/* 1229 * We are done. Do not return, instead branch to second part of board 1230 * initialization, now running from RAM. 1231 */ 1232 1233 addi r0,r10,in_ram - _start + _START_OFFSET 1234 mtlr r0 1235 blr /* NEVER RETURNS! */ 1236 .globl in_ram 1237in_ram: 1238 1239 /* 1240 * Relocation Function, r12 point to got2+0x8000 1241 * 1242 * Adjust got2 pointers, no need to check for 0, this code 1243 * already puts a few entries in the table. 1244 */ 1245 li r0,__got2_entries@sectoff@l 1246 la r3,GOT(_GOT2_TABLE_) 1247 lwz r11,GOT(_GOT2_TABLE_) 1248 mtctr r0 1249 sub r11,r3,r11 1250 addi r3,r3,-4 12511: lwzu r0,4(r3) 1252 cmpwi r0,0 1253 beq- 2f 1254 add r0,r0,r11 1255 stw r0,0(r3) 12562: bdnz 1b 1257 1258 /* 1259 * Now adjust the fixups and the pointers to the fixups 1260 * in case we need to move ourselves again. 1261 */ 1262 li r0,__fixup_entries@sectoff@l 1263 lwz r3,GOT(_FIXUP_TABLE_) 1264 cmpwi r0,0 1265 mtctr r0 1266 addi r3,r3,-4 1267 beq 4f 12683: lwzu r4,4(r3) 1269 lwzux r0,r4,r11 1270 cmpwi r0,0 1271 add r0,r0,r11 1272 stw r4,0(r3) 1273 beq- 5f 1274 stw r0,0(r4) 12755: bdnz 3b 12764: 1277clear_bss: 1278 /* 1279 * Now clear BSS segment 1280 */ 1281 lwz r3,GOT(__bss_start) 1282 lwz r4,GOT(__bss_end__) 1283 1284 cmplw 0,r3,r4 1285 beq 6f 1286 1287 li r0,0 12885: 1289 stw r0,0(r3) 1290 addi r3,r3,4 1291 cmplw 0,r3,r4 1292 bne 5b 12936: 1294 1295 mr r3,r9 /* Init Data pointer */ 1296 mr r4,r10 /* Destination Address */ 1297 bl board_init_r 1298 1299#ifndef CONFIG_NAND_SPL 1300 /* 1301 * Copy exception vector code to low memory 1302 * 1303 * r3: dest_addr 1304 * r7: source address, r8: end address, r9: target address 1305 */ 1306 .globl trap_init 1307trap_init: 1308 mflr r4 /* save link register */ 1309 GET_GOT 1310 lwz r7,GOT(_start_of_vectors) 1311 lwz r8,GOT(_end_of_vectors) 1312 1313 li r9,0x100 /* reset vector always at 0x100 */ 1314 1315 cmplw 0,r7,r8 1316 bgelr /* return if r7>=r8 - just in case */ 13171: 1318 lwz r0,0(r7) 1319 stw r0,0(r9) 1320 addi r7,r7,4 1321 addi r9,r9,4 1322 cmplw 0,r7,r8 1323 bne 1b 1324 1325 /* 1326 * relocate `hdlr' and `int_return' entries 1327 */ 1328 li r7,.L_CriticalInput - _start + _START_OFFSET 1329 bl trap_reloc 1330 li r7,.L_MachineCheck - _start + _START_OFFSET 1331 bl trap_reloc 1332 li r7,.L_DataStorage - _start + _START_OFFSET 1333 bl trap_reloc 1334 li r7,.L_InstStorage - _start + _START_OFFSET 1335 bl trap_reloc 1336 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1337 bl trap_reloc 1338 li r7,.L_Alignment - _start + _START_OFFSET 1339 bl trap_reloc 1340 li r7,.L_ProgramCheck - _start + _START_OFFSET 1341 bl trap_reloc 1342 li r7,.L_FPUnavailable - _start + _START_OFFSET 1343 bl trap_reloc 1344 li r7,.L_Decrementer - _start + _START_OFFSET 1345 bl trap_reloc 1346 li r7,.L_IntervalTimer - _start + _START_OFFSET 1347 li r8,_end_of_vectors - _start + _START_OFFSET 13482: 1349 bl trap_reloc 1350 addi r7,r7,0x100 /* next exception vector */ 1351 cmplw 0,r7,r8 1352 blt 2b 1353 1354 lis r7,0x0 1355 mtspr IVPR,r7 1356 1357 mtlr r4 /* restore link register */ 1358 blr 1359 1360.globl unlock_ram_in_cache 1361unlock_ram_in_cache: 1362 /* invalidate the INIT_RAM section */ 1363 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1364 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1365 mfspr r4,L1CFG0 1366 andi. r4,r4,0x1ff 1367 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1368 mtctr r4 13691: dcbi r0,r3 1370 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1371 bdnz 1b 1372 sync 1373 1374 /* Invalidate the TLB entries for the cache */ 1375 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1376 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1377 tlbivax 0,r3 1378 addi r3,r3,0x1000 1379 tlbivax 0,r3 1380 addi r3,r3,0x1000 1381 tlbivax 0,r3 1382 addi r3,r3,0x1000 1383 tlbivax 0,r3 1384 isync 1385 blr 1386 1387.globl flush_dcache 1388flush_dcache: 1389 mfspr r3,SPRN_L1CFG0 1390 1391 rlwinm r5,r3,9,3 /* Extract cache block size */ 1392 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1393 * are currently defined. 1394 */ 1395 li r4,32 1396 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1397 * log2(number of ways) 1398 */ 1399 slw r5,r4,r5 /* r5 = cache block size */ 1400 1401 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1402 mulli r7,r7,13 /* An 8-way cache will require 13 1403 * loads per set. 1404 */ 1405 slw r7,r7,r6 1406 1407 /* save off HID0 and set DCFA */ 1408 mfspr r8,SPRN_HID0 1409 ori r9,r8,HID0_DCFA@l 1410 mtspr SPRN_HID0,r9 1411 isync 1412 1413 lis r4,0 1414 mtctr r7 1415 14161: lwz r3,0(r4) /* Load... */ 1417 add r4,r4,r5 1418 bdnz 1b 1419 1420 msync 1421 lis r4,0 1422 mtctr r7 1423 14241: dcbf 0,r4 /* ...and flush. */ 1425 add r4,r4,r5 1426 bdnz 1b 1427 1428 /* restore HID0 */ 1429 mtspr SPRN_HID0,r8 1430 isync 1431 1432 blr 1433 1434.globl setup_ivors 1435setup_ivors: 1436 1437#include "fixed_ivor.S" 1438 blr 1439#endif /* !CONFIG_NAND_SPL */ 1440