Merge tag 'mpc85xx-for-v2019.04-rc1' of git://git.denx.de/u-boot-mpc85xx

mpc85xx config.mk: Add support for -msingle-pic-base

mpc85xx: Add support for -msingle-pic-base

-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4-5 KB.
While at it, add -fno-jump-tables too to sa

mpc85xx: Add support for -msingle-pic-base

-msingle-pic-base is a new gcc(from 4.6) option for ppc and
it reduces the size of my u-boot with about 4-5 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

e5500 core:
size u-boot.bef
text data bss dec hex filename
473043 23772 307104 803919 c444f u-boot.bef
size u-boot.aft
text data bss dec hex filename
453195 23772 307104 784071 bf6c7 u-boot.aft

e500 core:
size u-boot.bef
text data bss dec hex filename
292998 17868 24968 335834 51fda u-boot.bef
size u-boot.aft
text data bss dec hex filename
288002 17868 24968 330838 50c56 u-boot.aft

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool befo

powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot

Some platforms have very limited SRAM to run SPL code, so there may
not be the same amount space for a malloc pool before relocation in
the SPL stage as the normal U-Boot stage.

Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN,
so the size of pre-relocation malloc pool can be configured memory
space independently.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixed up commit-message:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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powerpc: move get_pvr() and get_svr() into C

Avoid unnecessary assembly functions when they can easily be written
in C.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-fsl-qoriq

powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L

powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram

For E6500 cores, L2 cache has been used as init_ram. L1 cache is a
write through cache on E6500.If lines are not locked in both L1 and
L2 caches, crashes are observed during secure boot. This patch locks/
unlocks both L1 and L2 cache to prevent the crash.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-mpc85xx

powerpc: mpc85xx: Use symbolic names for cache control bits

We should use the symbolic names for the cache control bits.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas

powerpc: mpc85xx: Use symbolic names for cache control bits

We should use the symbolic names for the cache control bits.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-mpc85xx

powerpc: QEMU_E500: Remove macro CONFIG_QEMU_E500

Replace CONFIG_QEMU_E500 with ARCH_QEMU_E500 in Kconfig and
clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>

powerpc: MPC8569: Remove macro CONFIG_MPC8569

Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>

Merge git://git.denx.de/u-boot-mpc85xx

powerpc/mpc85xx: T104x: Add nand secure boot target

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configure

powerpc/mpc85xx: T104x: Add nand secure boot target

For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache

While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.

powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache

While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx

To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-

powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx

To enable DM on MPC85xx, we need pre-relocation malloc, which is
implemented in this patch.

We also make sure that the IVORs are always 4-aligned on e500 to prevent
alignment exceptions caused by code changes in start.S.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Cc: York Sun <york.sun@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram

MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data

powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram

MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure

powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge git://git.denx.de/u-boot-mpc85xx