1/* 2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. 3 * Copyright (C) 2003 Motorola,Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25 * 26 * The processor starts at 0xfffffffc and the code is first executed in the 27 * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28 * 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <mpc85xx.h> 34#include <version.h> 35 36#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37 38#include <ppc_asm.tmpl> 39#include <ppc_defs.h> 40 41#include <asm/cache.h> 42#include <asm/mmu.h> 43 44#undef MSR_KERNEL 45#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46 47/* 48 * Set up GOT: Global Offset Table 49 * 50 * Use r12 to access the GOT 51 */ 52 START_GOT 53 GOT_ENTRY(_GOT2_TABLE_) 54 GOT_ENTRY(_FIXUP_TABLE_) 55 56#ifndef CONFIG_NAND_SPL 57 GOT_ENTRY(_start) 58 GOT_ENTRY(_start_of_vectors) 59 GOT_ENTRY(_end_of_vectors) 60 GOT_ENTRY(transfer_to_handler) 61#endif 62 63 GOT_ENTRY(__init_end) 64 GOT_ENTRY(__bss_end__) 65 GOT_ENTRY(__bss_start) 66 END_GOT 67 68/* 69 * e500 Startup -- after reset only the last 4KB of the effective 70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71 * section is located at THIS LAST page and basically does three 72 * things: clear some registers, set up exception tables and 73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74 * continue the boot procedure. 75 76 * Once the boot rom is mapped by TLB entries we can proceed 77 * with normal startup. 78 * 79 */ 80 81 .section .bootpg,"ax" 82 .globl _start_e500 83 84_start_e500: 85/* Enable debug exception */ 86 li r1,MSR_DE 87 mtmsr r1 88 89#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 90 /* ISBC uses L2 as stack. 91 * Disable L2 cache here so that u-boot can enable it later 92 * as part of it's normal flow 93 */ 94 95 /* Check if L2 is enabled */ 96 mfspr r3, SPRN_L2CSR0 97 lis r2, L2CSR0_L2E@h 98 ori r2, r2, L2CSR0_L2E@l 99 and. r4, r3, r2 100 beq l2_disabled 101 102 mfspr r3, SPRN_L2CSR0 103 /* Flush L2 cache */ 104 lis r2,(L2CSR0_L2FL)@h 105 ori r2, r2, (L2CSR0_L2FL)@l 106 or r3, r2, r3 107 sync 108 isync 109 mtspr SPRN_L2CSR0,r3 110 isync 1111: 112 mfspr r3, SPRN_L2CSR0 113 and. r1, r3, r2 114 bne 1b 115 116 mfspr r3, SPRN_L2CSR0 117 lis r2, L2CSR0_L2E@h 118 ori r2, r2, L2CSR0_L2E@l 119 andc r4, r3, r2 120 sync 121 isync 122 mtspr SPRN_L2CSR0,r4 123 isync 124 125l2_disabled: 126#endif 127 128/* clear registers/arrays not reset by hardware */ 129 130 /* L1 */ 131 li r0,2 132 mtspr L1CSR0,r0 /* invalidate d-cache */ 133 mtspr L1CSR1,r0 /* invalidate i-cache */ 134 135 mfspr r1,DBSR 136 mtspr DBSR,r1 /* Clear all valid bits */ 137 138 /* 139 * Enable L1 Caches early 140 * 141 */ 142 143#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 144 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 145 li r2,(32 + 0) 146 mtspr L1CSR2,r2 147#endif 148 149 /* Enable/invalidate the I-Cache */ 150 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 151 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 152 mtspr SPRN_L1CSR1,r2 1531: 154 mfspr r3,SPRN_L1CSR1 155 and. r1,r3,r2 156 bne 1b 157 158 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 159 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 160 mtspr SPRN_L1CSR1,r3 161 isync 1622: 163 mfspr r3,SPRN_L1CSR1 164 andi. r1,r3,L1CSR1_ICE@l 165 beq 2b 166 167 /* Enable/invalidate the D-Cache */ 168 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 169 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 170 mtspr SPRN_L1CSR0,r2 1711: 172 mfspr r3,SPRN_L1CSR0 173 and. r1,r3,r2 174 bne 1b 175 176 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 177 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 178 mtspr SPRN_L1CSR0,r3 179 isync 1802: 181 mfspr r3,SPRN_L1CSR0 182 andi. r1,r3,L1CSR0_DCE@l 183 beq 2b 184 185#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) 186/* 187 * TLB entry for debuggging in AS1 188 * Create temporary TLB entry in AS0 to handle debug exception 189 * As on debug exception MSR is cleared i.e. Address space is changed 190 * to 0. A TLB entry (in AS0) is required to handle debug exception generated 191 * in AS1. 192 */ 193 194 lis r6,FSL_BOOKE_MAS0(1, 195 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h 196 ori r6,r6,FSL_BOOKE_MAS0(1, 197 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l 198 199#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 200/* 201 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 202 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. 203 * and this window is outside of 4K boot window. 204 */ 205 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h 206 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l 207 208 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 209 (MAS2_I|MAS2_G))@h 210 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, 211 (MAS2_I|MAS2_G))@l 212 213 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 214 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 215 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 216#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 217 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h 218 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l 219 220 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h 221 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l 222 223 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 224 (MAS3_SX|MAS3_SW|MAS3_SR))@h 225 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 226 (MAS3_SX|MAS3_SW|MAS3_SR))@l 227#else 228/* 229 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address 230 * because "nexti" will resize TLB to 4K 231 */ 232 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h 233 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l 234 235 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h 236 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, 237 (MAS2_I))@l 238 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 239 (MAS3_SX|MAS3_SW|MAS3_SR))@h 240 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, 241 (MAS3_SX|MAS3_SW|MAS3_SR))@l 242#endif 243 mtspr MAS0,r6 244 mtspr MAS1,r7 245 mtspr MAS2,r8 246 mtspr MAS3,r9 247 tlbwe 248 isync 249#endif 250 251/* 252 * Ne need to setup interrupt vector for NAND SPL 253 * because NAND SPL never compiles it. 254 */ 255#if !defined(CONFIG_NAND_SPL) 256 /* Setup interrupt vectors */ 257 lis r1,CONFIG_SYS_MONITOR_BASE@h 258 mtspr IVPR,r1 259 260 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h 261 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l 262 263 addi r4,r3,CriticalInput - _start + _START_OFFSET 264 mtspr IVOR0,r4 /* 0: Critical input */ 265 addi r4,r3,MachineCheck - _start + _START_OFFSET 266 mtspr IVOR1,r4 /* 1: Machine check */ 267 addi r4,r3,DataStorage - _start + _START_OFFSET 268 mtspr IVOR2,r4 /* 2: Data storage */ 269 addi r4,r3,InstStorage - _start + _START_OFFSET 270 mtspr IVOR3,r4 /* 3: Instruction storage */ 271 addi r4,r3,ExtInterrupt - _start + _START_OFFSET 272 mtspr IVOR4,r4 /* 4: External interrupt */ 273 addi r4,r3,Alignment - _start + _START_OFFSET 274 mtspr IVOR5,r4 /* 5: Alignment */ 275 addi r4,r3,ProgramCheck - _start + _START_OFFSET 276 mtspr IVOR6,r4 /* 6: Program check */ 277 addi r4,r3,FPUnavailable - _start + _START_OFFSET 278 mtspr IVOR7,r4 /* 7: floating point unavailable */ 279 addi r4,r3,SystemCall - _start + _START_OFFSET 280 mtspr IVOR8,r4 /* 8: System call */ 281 /* 9: Auxiliary processor unavailable(unsupported) */ 282 addi r4,r3,Decrementer - _start + _START_OFFSET 283 mtspr IVOR10,r4 /* 10: Decrementer */ 284 addi r4,r3,IntervalTimer - _start + _START_OFFSET 285 mtspr IVOR11,r4 /* 11: Interval timer */ 286 addi r4,r3,WatchdogTimer - _start + _START_OFFSET 287 mtspr IVOR12,r4 /* 12: Watchdog timer */ 288 addi r4,r3,DataTLBError - _start + _START_OFFSET 289 mtspr IVOR13,r4 /* 13: Data TLB error */ 290 addi r4,r3,InstructionTLBError - _start + _START_OFFSET 291 mtspr IVOR14,r4 /* 14: Instruction TLB error */ 292 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET 293 mtspr IVOR15,r4 /* 15: Debug */ 294#endif 295 296 /* Clear and set up some registers. */ 297 li r0,0x0000 298 lis r1,0xffff 299 mtspr DEC,r0 /* prevent dec exceptions */ 300 mttbl r0 /* prevent fit & wdt exceptions */ 301 mttbu r0 302 mtspr TSR,r1 /* clear all timer exception status */ 303 mtspr TCR,r0 /* disable all */ 304 mtspr ESR,r0 /* clear exception syndrome register */ 305 mtspr MCSR,r0 /* machine check syndrome register */ 306 mtxer r0 /* clear integer exception register */ 307 308#ifdef CONFIG_SYS_BOOK3E_HV 309 mtspr MAS8,r0 /* make sure MAS8 is clear */ 310#endif 311 312 /* Enable Time Base and Select Time Base Clock */ 313 lis r0,HID0_EMCP@h /* Enable machine check */ 314#if defined(CONFIG_ENABLE_36BIT_PHYS) 315 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 316#endif 317#ifndef CONFIG_E500MC 318 ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 319#endif 320 mtspr HID0,r0 321 322#ifndef CONFIG_E500MC 323 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 324 mfspr r3,PVR 325 andi. r3,r3, 0xff 326 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 327 blt 1f 328 /* Set MBDD bit also */ 329 ori r0, r0, HID1_MBDD@l 3301: 331 mtspr HID1,r0 332#endif 333 334#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 335 mfspr r3,977 336 oris r3,r3,0x0100 337 mtspr 977,r3 338#endif 339 340 /* Enable Branch Prediction */ 341#if defined(CONFIG_BTB) 342 lis r0,BUCSR_ENABLE@h 343 ori r0,r0,BUCSR_ENABLE@l 344 mtspr SPRN_BUCSR,r0 345#endif 346 347#if defined(CONFIG_SYS_INIT_DBCR) 348 lis r1,0xffff 349 ori r1,r1,0xffff 350 mtspr DBSR,r1 /* Clear all status bits */ 351 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 352 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 353 mtspr DBCR0,r0 354#endif 355 356#ifdef CONFIG_MPC8569 357#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 358#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 359 360 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 361 * use address space which is more than 12bits, and it must be done in 362 * the 4K boot page. So we set this bit here. 363 */ 364 365 /* create a temp mapping TLB0[0] for LBCR */ 366 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 367 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 368 369 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 370 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 371 372 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 373 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 374 375 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 376 (MAS3_SX|MAS3_SW|MAS3_SR))@h 377 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 378 (MAS3_SX|MAS3_SW|MAS3_SR))@l 379 380 mtspr MAS0,r6 381 mtspr MAS1,r7 382 mtspr MAS2,r8 383 mtspr MAS3,r9 384 isync 385 msync 386 tlbwe 387 388 /* Set LBCR register */ 389 lis r4,CONFIG_SYS_LBCR_ADDR@h 390 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 391 392 lis r5,CONFIG_SYS_LBC_LBCR@h 393 ori r5,r5,CONFIG_SYS_LBC_LBCR@l 394 stw r5,0(r4) 395 isync 396 397 /* invalidate this temp TLB */ 398 lis r4,CONFIG_SYS_LBC_ADDR@h 399 ori r4,r4,CONFIG_SYS_LBC_ADDR@l 400 tlbivax 0,r4 401 isync 402 403#endif /* CONFIG_MPC8569 */ 404 405/* 406 * Search for the TLB that covers the code we're executing, and shrink it 407 * so that it covers only this 4K page. That will ensure that any other 408 * TLB we create won't interfere with it. We assume that the TLB exists, 409 * which is why we don't check the Valid bit of MAS1. 410 * 411 * This is necessary, for example, when booting from the on-chip ROM, 412 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 413 * If we don't shrink this TLB now, then we'll accidentally delete it 414 * in "purge_old_ccsr_tlb" below. 415 */ 416 bl nexti /* Find our address */ 417nexti: mflr r1 /* R1 = our PC */ 418 li r2, 0 419 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 420 isync 421 msync 422 tlbsx 0, r1 /* This must succeed */ 423 424 /* Set the size of the TLB to 4KB */ 425 mfspr r3, MAS1 426 li r2, 0xF00 427 andc r3, r3, r2 /* Clear the TSIZE bits */ 428 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 429 mtspr MAS1, r3 430 431 /* 432 * Set the base address of the TLB to our PC. We assume that 433 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 434 */ 435 lis r3, MAS2_EPN@h 436 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 437 438 and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 439 440 mfspr r2, MAS2 441 andc r2, r2, r3 442 or r2, r2, r1 443 mtspr MAS2, r2 /* Set the EPN to our PC base address */ 444 445 mfspr r2, MAS3 446 andc r2, r2, r3 447 or r2, r2, r1 448 mtspr MAS3, r2 /* Set the RPN to our PC base address */ 449 450 isync 451 msync 452 tlbwe 453 454/* 455 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 456 * location is not where we want it. This typically happens on a 36-bit 457 * system, where we want to move CCSR to near the top of 36-bit address space. 458 * 459 * To move CCSR, we create two temporary TLBs, one for the old location, and 460 * another for the new location. On CoreNet systems, we also need to create 461 * a special, temporary LAW. 462 * 463 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 464 * long-term TLBs, so we use TLB0 here. 465 */ 466#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 467 468#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 469#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 470#endif 471 472purge_old_ccsr_tlb: 473 lis r8, CONFIG_SYS_CCSRBAR@h 474 ori r8, r8, CONFIG_SYS_CCSRBAR@l 475 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 476 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 477 478 /* 479 * In a multi-stage boot (e.g. NAND boot), a previous stage may have 480 * created a TLB for CCSR, which will interfere with our relocation 481 * code. Since we're going to create a new TLB for CCSR anyway, 482 * it should be safe to delete this old TLB here. We have to search 483 * for it, though. 484 */ 485 486 li r1, 0 487 mtspr MAS6, r1 /* Search the current address space and PID */ 488 isync 489 msync 490 tlbsx 0, r8 491 mfspr r1, MAS1 492 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 493 beq 1f /* Skip if no TLB found */ 494 495 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 496 mtspr MAS1, r1 497 isync 498 msync 499 tlbwe 5001: 501 502create_ccsr_new_tlb: 503 /* 504 * Create a TLB for the new location of CCSR. Register R8 is reserved 505 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 506 */ 507 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 508 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 509 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 510 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 511 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 512 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 513 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 514 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 515#ifdef CONFIG_ENABLE_36BIT_PHYS 516 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 517 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 518 mtspr MAS7, r7 519#endif 520 mtspr MAS0, r0 521 mtspr MAS1, r1 522 mtspr MAS2, r2 523 mtspr MAS3, r3 524 isync 525 msync 526 tlbwe 527 528 /* 529 * Create a TLB for the current location of CCSR. Register R9 is reserved 530 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 531 */ 532create_ccsr_old_tlb: 533 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 534 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 535 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 536 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 537 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 538 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 539#ifdef CONFIG_ENABLE_36BIT_PHYS 540 li r7, 0 /* The default CCSR address is always a 32-bit number */ 541 mtspr MAS7, r7 542#endif 543 mtspr MAS0, r0 544 /* MAS1 is the same as above */ 545 mtspr MAS2, r2 546 mtspr MAS3, r3 547 isync 548 msync 549 tlbwe 550 551 /* 552 * We have a TLB for what we think is the current (old) CCSR. Let's 553 * verify that, otherwise we won't be able to move it. 554 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 555 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 556 */ 557verify_old_ccsr: 558 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 559 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 560#ifdef CONFIG_FSL_CORENET 561 lwz r1, 4(r9) /* CCSRBARL */ 562#else 563 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 564 slwi r1, r1, 12 565#endif 566 567 cmpl 0, r0, r1 568 569 /* 570 * If the value we read from CCSRBARL is not what we expect, then 571 * enter an infinite loop. This will at least allow a debugger to 572 * halt execution and examine TLBs, etc. There's no point in going 573 * on. 574 */ 575infinite_debug_loop: 576 bne infinite_debug_loop 577 578#ifdef CONFIG_FSL_CORENET 579 580#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 581#define LAW_EN 0x80000000 582#define LAW_SIZE_4K 0xb 583#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 584#define CCSRAR_C 0x80000000 /* Commit */ 585 586create_temp_law: 587 /* 588 * On CoreNet systems, we create the temporary LAW using a special LAW 589 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 590 */ 591 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 592 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 593 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 594 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 595 lis r2, CCSRBAR_LAWAR@h 596 ori r2, r2, CCSRBAR_LAWAR@l 597 598 stw r0, 0xc00(r9) /* LAWBARH0 */ 599 stw r1, 0xc04(r9) /* LAWBARL0 */ 600 sync 601 stw r2, 0xc08(r9) /* LAWAR0 */ 602 603 /* 604 * Read back from LAWAR to ensure the update is complete. e500mc 605 * cores also require an isync. 606 */ 607 lwz r0, 0xc08(r9) /* LAWAR0 */ 608 isync 609 610 /* 611 * Read the current CCSRBARH and CCSRBARL using load word instructions. 612 * Follow this with an isync instruction. This forces any outstanding 613 * accesses to configuration space to completion. 614 */ 615read_old_ccsrbar: 616 lwz r0, 0(r9) /* CCSRBARH */ 617 lwz r0, 4(r9) /* CCSRBARL */ 618 isync 619 620 /* 621 * Write the new values for CCSRBARH and CCSRBARL to their old 622 * locations. The CCSRBARH has a shadow register. When the CCSRBARH 623 * has a new value written it loads a CCSRBARH shadow register. When 624 * the CCSRBARL is written, the CCSRBARH shadow register contents 625 * along with the CCSRBARL value are loaded into the CCSRBARH and 626 * CCSRBARL registers, respectively. Follow this with a sync 627 * instruction. 628 */ 629write_new_ccsrbar: 630 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 631 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 632 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 633 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 634 lis r2, CCSRAR_C@h 635 ori r2, r2, CCSRAR_C@l 636 637 stw r0, 0(r9) /* Write to CCSRBARH */ 638 sync /* Make sure we write to CCSRBARH first */ 639 stw r1, 4(r9) /* Write to CCSRBARL */ 640 sync 641 642 /* 643 * Write a 1 to the commit bit (C) of CCSRAR at the old location. 644 * Follow this with a sync instruction. 645 */ 646 stw r2, 8(r9) 647 sync 648 649 /* Delete the temporary LAW */ 650delete_temp_law: 651 li r1, 0 652 stw r1, 0xc08(r8) 653 sync 654 stw r1, 0xc00(r8) 655 stw r1, 0xc04(r8) 656 sync 657 658#else /* #ifdef CONFIG_FSL_CORENET */ 659 660write_new_ccsrbar: 661 /* 662 * Read the current value of CCSRBAR using a load word instruction 663 * followed by an isync. This forces all accesses to configuration 664 * space to complete. 665 */ 666 sync 667 lwz r0, 0(r9) 668 isync 669 670/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 671#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 672 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 673 674 /* Write the new value to CCSRBAR. */ 675 lis r0, CCSRBAR_PHYS_RS12@h 676 ori r0, r0, CCSRBAR_PHYS_RS12@l 677 stw r0, 0(r9) 678 sync 679 680 /* 681 * The manual says to perform a load of an address that does not 682 * access configuration space or the on-chip SRAM using an existing TLB, 683 * but that doesn't appear to be necessary. We will do the isync, 684 * though. 685 */ 686 isync 687 688 /* 689 * Read the contents of CCSRBAR from its new location, followed by 690 * another isync. 691 */ 692 lwz r0, 0(r8) 693 isync 694 695#endif /* #ifdef CONFIG_FSL_CORENET */ 696 697 /* Delete the temporary TLBs */ 698delete_temp_tlbs: 699 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 700 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 701 li r1, 0 702 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 703 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 704 mtspr MAS0, r0 705 mtspr MAS1, r1 706 mtspr MAS2, r2 707 isync 708 msync 709 tlbwe 710 711 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 712 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 713 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 714 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 715 mtspr MAS0, r0 716 mtspr MAS2, r2 717 isync 718 msync 719 tlbwe 720#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 721 722create_init_ram_area: 723 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 724 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 725 726#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 727 /* create a temp mapping in AS=1 to the 4M boot window */ 728 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 729 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 730 731 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 732 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 733 734 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 735 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 736 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 737#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 738 /* create a temp mapping in AS = 1 for Flash mapping 739 * created by PBL for ISBC code 740 */ 741 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 742 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 743 744 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 745 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 746 747 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 748 (MAS3_SX|MAS3_SW|MAS3_SR))@h 749 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 750 (MAS3_SX|MAS3_SW|MAS3_SR))@l 751#else 752 /* 753 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 754 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 755 */ 756 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 757 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 758 759 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 760 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 761 762 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 763 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 764#endif 765 766 mtspr MAS0,r6 767 mtspr MAS1,r7 768 mtspr MAS2,r8 769 mtspr MAS3,r9 770 isync 771 msync 772 tlbwe 773 774 /* create a temp mapping in AS=1 to the stack */ 775 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 776 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 777 778 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 779 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 780 781 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 782 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 783 784#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 785 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 786 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 787 (MAS3_SX|MAS3_SW|MAS3_SR))@h 788 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 789 (MAS3_SX|MAS3_SW|MAS3_SR))@l 790 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 791 mtspr MAS7,r10 792#else 793 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 794 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 795#endif 796 797 mtspr MAS0,r6 798 mtspr MAS1,r7 799 mtspr MAS2,r8 800 mtspr MAS3,r9 801 isync 802 msync 803 tlbwe 804 805 lis r6,MSR_IS|MSR_DS|MSR_DE@h 806 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l 807 lis r7,switch_as@h 808 ori r7,r7,switch_as@l 809 810 mtspr SPRN_SRR0,r7 811 mtspr SPRN_SRR1,r6 812 rfi 813 814switch_as: 815/* L1 DCache is used for initial RAM */ 816 817 /* Allocate Initial RAM in data cache. 818 */ 819 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 820 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 821 mfspr r2, L1CFG0 822 andi. r2, r2, 0x1ff 823 /* cache size * 1024 / (2 * L1 line size) */ 824 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 825 mtctr r2 826 li r0,0 8271: 828 dcbz r0,r3 829 dcbtls 0,r0,r3 830 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 831 bdnz 1b 832 833 /* Jump out the last 4K page and continue to 'normal' start */ 834#ifdef CONFIG_SYS_RAMBOOT 835 b _start_cont 836#else 837 /* Calculate absolute address in FLASH and jump there */ 838 /*--------------------------------------------------------------*/ 839 lis r3,CONFIG_SYS_MONITOR_BASE@h 840 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 841 addi r3,r3,_start_cont - _start + _START_OFFSET 842 mtlr r3 843 blr 844#endif 845 846 .text 847 .globl _start 848_start: 849 .long 0x27051956 /* U-BOOT Magic Number */ 850 .globl version_string 851version_string: 852 .ascii U_BOOT_VERSION_STRING, "\0" 853 854 .align 4 855 .globl _start_cont 856_start_cont: 857 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 858 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h 859 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ 860 li r0,0 861 stw r0,0(r3) /* Terminate Back Chain */ 862 stw r0,+4(r3) /* NULL return address. */ 863 mr r1,r3 /* Transfer to SP(r1) */ 864 865 GET_GOT 866 bl cpu_init_early_f 867 868 /* switch back to AS = 0 */ 869 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 870 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 871 mtmsr r3 872 isync 873 874 bl cpu_init_f 875 bl board_init_f 876 isync 877 878 /* NOTREACHED - board_init_f() does not return */ 879 880#ifndef CONFIG_NAND_SPL 881 . = EXC_OFF_SYS_RESET 882 .globl _start_of_vectors 883_start_of_vectors: 884 885/* Critical input. */ 886 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 887 888/* Machine check */ 889 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 890 891/* Data Storage exception. */ 892 STD_EXCEPTION(0x0300, DataStorage, UnknownException) 893 894/* Instruction Storage exception. */ 895 STD_EXCEPTION(0x0400, InstStorage, UnknownException) 896 897/* External Interrupt exception. */ 898 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 899 900/* Alignment exception. */ 901 . = 0x0600 902Alignment: 903 EXCEPTION_PROLOG(SRR0, SRR1) 904 mfspr r4,DAR 905 stw r4,_DAR(r21) 906 mfspr r5,DSISR 907 stw r5,_DSISR(r21) 908 addi r3,r1,STACK_FRAME_OVERHEAD 909 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 910 911/* Program check exception */ 912 . = 0x0700 913ProgramCheck: 914 EXCEPTION_PROLOG(SRR0, SRR1) 915 addi r3,r1,STACK_FRAME_OVERHEAD 916 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 917 MSR_KERNEL, COPY_EE) 918 919 /* No FPU on MPC85xx. This exception is not supposed to happen. 920 */ 921 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 922 923 . = 0x0900 924/* 925 * r0 - SYSCALL number 926 * r3-... arguments 927 */ 928SystemCall: 929 addis r11,r0,0 /* get functions table addr */ 930 ori r11,r11,0 /* Note: this code is patched in trap_init */ 931 addis r12,r0,0 /* get number of functions */ 932 ori r12,r12,0 933 934 cmplw 0,r0,r12 935 bge 1f 936 937 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 938 add r11,r11,r0 939 lwz r11,0(r11) 940 941 li r20,0xd00-4 /* Get stack pointer */ 942 lwz r12,0(r20) 943 subi r12,r12,12 /* Adjust stack pointer */ 944 li r0,0xc00+_end_back-SystemCall 945 cmplw 0,r0,r12 /* Check stack overflow */ 946 bgt 1f 947 stw r12,0(r20) 948 949 mflr r0 950 stw r0,0(r12) 951 mfspr r0,SRR0 952 stw r0,4(r12) 953 mfspr r0,SRR1 954 stw r0,8(r12) 955 956 li r12,0xc00+_back-SystemCall 957 mtlr r12 958 mtspr SRR0,r11 959 9601: SYNC 961 rfi 962_back: 963 964 mfmsr r11 /* Disable interrupts */ 965 li r12,0 966 ori r12,r12,MSR_EE 967 andc r11,r11,r12 968 SYNC /* Some chip revs need this... */ 969 mtmsr r11 970 SYNC 971 972 li r12,0xd00-4 /* restore regs */ 973 lwz r12,0(r12) 974 975 lwz r11,0(r12) 976 mtlr r11 977 lwz r11,4(r12) 978 mtspr SRR0,r11 979 lwz r11,8(r12) 980 mtspr SRR1,r11 981 982 addi r12,r12,12 /* Adjust stack pointer */ 983 li r20,0xd00-4 984 stw r12,0(r20) 985 986 SYNC 987 rfi 988_end_back: 989 990 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 991 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 992 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 993 994 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 995 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 996 997 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 998 999 .globl _end_of_vectors 1000_end_of_vectors: 1001 1002 1003 . = . + (0x100 - ( . & 0xff )) /* align for debug */ 1004 1005/* 1006 * This code finishes saving the registers to the exception frame 1007 * and jumps to the appropriate handler for the exception. 1008 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1009 */ 1010 .globl transfer_to_handler 1011transfer_to_handler: 1012 stw r22,_NIP(r21) 1013 lis r22,MSR_POW@h 1014 andc r23,r23,r22 1015 stw r23,_MSR(r21) 1016 SAVE_GPR(7, r21) 1017 SAVE_4GPRS(8, r21) 1018 SAVE_8GPRS(12, r21) 1019 SAVE_8GPRS(24, r21) 1020 1021 mflr r23 1022 andi. r24,r23,0x3f00 /* get vector offset */ 1023 stw r24,TRAP(r21) 1024 li r22,0 1025 stw r22,RESULT(r21) 1026 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1027 1028 lwz r24,0(r23) /* virtual address of handler */ 1029 lwz r23,4(r23) /* where to go when done */ 1030 mtspr SRR0,r24 1031 mtspr SRR1,r20 1032 mtlr r23 1033 SYNC 1034 rfi /* jump to handler, enable MMU */ 1035 1036int_return: 1037 mfmsr r28 /* Disable interrupts */ 1038 li r4,0 1039 ori r4,r4,MSR_EE 1040 andc r28,r28,r4 1041 SYNC /* Some chip revs need this... */ 1042 mtmsr r28 1043 SYNC 1044 lwz r2,_CTR(r1) 1045 lwz r0,_LINK(r1) 1046 mtctr r2 1047 mtlr r0 1048 lwz r2,_XER(r1) 1049 lwz r0,_CCR(r1) 1050 mtspr XER,r2 1051 mtcrf 0xFF,r0 1052 REST_10GPRS(3, r1) 1053 REST_10GPRS(13, r1) 1054 REST_8GPRS(23, r1) 1055 REST_GPR(31, r1) 1056 lwz r2,_NIP(r1) /* Restore environment */ 1057 lwz r0,_MSR(r1) 1058 mtspr SRR0,r2 1059 mtspr SRR1,r0 1060 lwz r0,GPR0(r1) 1061 lwz r2,GPR2(r1) 1062 lwz r1,GPR1(r1) 1063 SYNC 1064 rfi 1065 1066crit_return: 1067 mfmsr r28 /* Disable interrupts */ 1068 li r4,0 1069 ori r4,r4,MSR_EE 1070 andc r28,r28,r4 1071 SYNC /* Some chip revs need this... */ 1072 mtmsr r28 1073 SYNC 1074 lwz r2,_CTR(r1) 1075 lwz r0,_LINK(r1) 1076 mtctr r2 1077 mtlr r0 1078 lwz r2,_XER(r1) 1079 lwz r0,_CCR(r1) 1080 mtspr XER,r2 1081 mtcrf 0xFF,r0 1082 REST_10GPRS(3, r1) 1083 REST_10GPRS(13, r1) 1084 REST_8GPRS(23, r1) 1085 REST_GPR(31, r1) 1086 lwz r2,_NIP(r1) /* Restore environment */ 1087 lwz r0,_MSR(r1) 1088 mtspr SPRN_CSRR0,r2 1089 mtspr SPRN_CSRR1,r0 1090 lwz r0,GPR0(r1) 1091 lwz r2,GPR2(r1) 1092 lwz r1,GPR1(r1) 1093 SYNC 1094 rfci 1095 1096mck_return: 1097 mfmsr r28 /* Disable interrupts */ 1098 li r4,0 1099 ori r4,r4,MSR_EE 1100 andc r28,r28,r4 1101 SYNC /* Some chip revs need this... */ 1102 mtmsr r28 1103 SYNC 1104 lwz r2,_CTR(r1) 1105 lwz r0,_LINK(r1) 1106 mtctr r2 1107 mtlr r0 1108 lwz r2,_XER(r1) 1109 lwz r0,_CCR(r1) 1110 mtspr XER,r2 1111 mtcrf 0xFF,r0 1112 REST_10GPRS(3, r1) 1113 REST_10GPRS(13, r1) 1114 REST_8GPRS(23, r1) 1115 REST_GPR(31, r1) 1116 lwz r2,_NIP(r1) /* Restore environment */ 1117 lwz r0,_MSR(r1) 1118 mtspr SPRN_MCSRR0,r2 1119 mtspr SPRN_MCSRR1,r0 1120 lwz r0,GPR0(r1) 1121 lwz r2,GPR2(r1) 1122 lwz r1,GPR1(r1) 1123 SYNC 1124 rfmci 1125 1126/* Cache functions. 1127*/ 1128.globl flush_icache 1129flush_icache: 1130.globl invalidate_icache 1131invalidate_icache: 1132 mfspr r0,L1CSR1 1133 ori r0,r0,L1CSR1_ICFI 1134 msync 1135 isync 1136 mtspr L1CSR1,r0 1137 isync 1138 blr /* entire I cache */ 1139 1140.globl invalidate_dcache 1141invalidate_dcache: 1142 mfspr r0,L1CSR0 1143 ori r0,r0,L1CSR0_DCFI 1144 msync 1145 isync 1146 mtspr L1CSR0,r0 1147 isync 1148 blr 1149 1150 .globl icache_enable 1151icache_enable: 1152 mflr r8 1153 bl invalidate_icache 1154 mtlr r8 1155 isync 1156 mfspr r4,L1CSR1 1157 ori r4,r4,0x0001 1158 oris r4,r4,0x0001 1159 mtspr L1CSR1,r4 1160 isync 1161 blr 1162 1163 .globl icache_disable 1164icache_disable: 1165 mfspr r0,L1CSR1 1166 lis r3,0 1167 ori r3,r3,L1CSR1_ICE 1168 andc r0,r0,r3 1169 mtspr L1CSR1,r0 1170 isync 1171 blr 1172 1173 .globl icache_status 1174icache_status: 1175 mfspr r3,L1CSR1 1176 andi. r3,r3,L1CSR1_ICE 1177 blr 1178 1179 .globl dcache_enable 1180dcache_enable: 1181 mflr r8 1182 bl invalidate_dcache 1183 mtlr r8 1184 isync 1185 mfspr r0,L1CSR0 1186 ori r0,r0,0x0001 1187 oris r0,r0,0x0001 1188 msync 1189 isync 1190 mtspr L1CSR0,r0 1191 isync 1192 blr 1193 1194 .globl dcache_disable 1195dcache_disable: 1196 mfspr r3,L1CSR0 1197 lis r4,0 1198 ori r4,r4,L1CSR0_DCE 1199 andc r3,r3,r4 1200 mtspr L1CSR0,r3 1201 isync 1202 blr 1203 1204 .globl dcache_status 1205dcache_status: 1206 mfspr r3,L1CSR0 1207 andi. r3,r3,L1CSR0_DCE 1208 blr 1209 1210 .globl get_pir 1211get_pir: 1212 mfspr r3,PIR 1213 blr 1214 1215 .globl get_pvr 1216get_pvr: 1217 mfspr r3,PVR 1218 blr 1219 1220 .globl get_svr 1221get_svr: 1222 mfspr r3,SVR 1223 blr 1224 1225 .globl wr_tcr 1226wr_tcr: 1227 mtspr TCR,r3 1228 blr 1229 1230/*------------------------------------------------------------------------------- */ 1231/* Function: in8 */ 1232/* Description: Input 8 bits */ 1233/*------------------------------------------------------------------------------- */ 1234 .globl in8 1235in8: 1236 lbz r3,0x0000(r3) 1237 blr 1238 1239/*------------------------------------------------------------------------------- */ 1240/* Function: out8 */ 1241/* Description: Output 8 bits */ 1242/*------------------------------------------------------------------------------- */ 1243 .globl out8 1244out8: 1245 stb r4,0x0000(r3) 1246 sync 1247 blr 1248 1249/*------------------------------------------------------------------------------- */ 1250/* Function: out16 */ 1251/* Description: Output 16 bits */ 1252/*------------------------------------------------------------------------------- */ 1253 .globl out16 1254out16: 1255 sth r4,0x0000(r3) 1256 sync 1257 blr 1258 1259/*------------------------------------------------------------------------------- */ 1260/* Function: out16r */ 1261/* Description: Byte reverse and output 16 bits */ 1262/*------------------------------------------------------------------------------- */ 1263 .globl out16r 1264out16r: 1265 sthbrx r4,r0,r3 1266 sync 1267 blr 1268 1269/*------------------------------------------------------------------------------- */ 1270/* Function: out32 */ 1271/* Description: Output 32 bits */ 1272/*------------------------------------------------------------------------------- */ 1273 .globl out32 1274out32: 1275 stw r4,0x0000(r3) 1276 sync 1277 blr 1278 1279/*------------------------------------------------------------------------------- */ 1280/* Function: out32r */ 1281/* Description: Byte reverse and output 32 bits */ 1282/*------------------------------------------------------------------------------- */ 1283 .globl out32r 1284out32r: 1285 stwbrx r4,r0,r3 1286 sync 1287 blr 1288 1289/*------------------------------------------------------------------------------- */ 1290/* Function: in16 */ 1291/* Description: Input 16 bits */ 1292/*------------------------------------------------------------------------------- */ 1293 .globl in16 1294in16: 1295 lhz r3,0x0000(r3) 1296 blr 1297 1298/*------------------------------------------------------------------------------- */ 1299/* Function: in16r */ 1300/* Description: Input 16 bits and byte reverse */ 1301/*------------------------------------------------------------------------------- */ 1302 .globl in16r 1303in16r: 1304 lhbrx r3,r0,r3 1305 blr 1306 1307/*------------------------------------------------------------------------------- */ 1308/* Function: in32 */ 1309/* Description: Input 32 bits */ 1310/*------------------------------------------------------------------------------- */ 1311 .globl in32 1312in32: 1313 lwz 3,0x0000(3) 1314 blr 1315 1316/*------------------------------------------------------------------------------- */ 1317/* Function: in32r */ 1318/* Description: Input 32 bits and byte reverse */ 1319/*------------------------------------------------------------------------------- */ 1320 .globl in32r 1321in32r: 1322 lwbrx r3,r0,r3 1323 blr 1324#endif /* !CONFIG_NAND_SPL */ 1325 1326/*------------------------------------------------------------------------------*/ 1327 1328/* 1329 * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1330 */ 1331 .globl write_tlb 1332write_tlb: 1333 mtspr MAS0,r3 1334 mtspr MAS1,r4 1335 mtspr MAS2,r5 1336 mtspr MAS3,r6 1337#ifdef CONFIG_ENABLE_36BIT_PHYS 1338 mtspr MAS7,r7 1339#endif 1340 li r3,0 1341#ifdef CONFIG_SYS_BOOK3E_HV 1342 mtspr MAS8,r3 1343#endif 1344 isync 1345 tlbwe 1346 msync 1347 isync 1348 blr 1349 1350/* 1351 * void relocate_code (addr_sp, gd, addr_moni) 1352 * 1353 * This "function" does not return, instead it continues in RAM 1354 * after relocating the monitor code. 1355 * 1356 * r3 = dest 1357 * r4 = src 1358 * r5 = length in bytes 1359 * r6 = cachelinesize 1360 */ 1361 .globl relocate_code 1362relocate_code: 1363 mr r1,r3 /* Set new stack pointer */ 1364 mr r9,r4 /* Save copy of Init Data pointer */ 1365 mr r10,r5 /* Save copy of Destination Address */ 1366 1367 GET_GOT 1368 mr r3,r5 /* Destination Address */ 1369 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1370 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1371 lwz r5,GOT(__init_end) 1372 sub r5,r5,r4 1373 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1374 1375 /* 1376 * Fix GOT pointer: 1377 * 1378 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1379 * 1380 * Offset: 1381 */ 1382 sub r15,r10,r4 1383 1384 /* First our own GOT */ 1385 add r12,r12,r15 1386 /* the the one used by the C code */ 1387 add r30,r30,r15 1388 1389 /* 1390 * Now relocate code 1391 */ 1392 1393 cmplw cr1,r3,r4 1394 addi r0,r5,3 1395 srwi. r0,r0,2 1396 beq cr1,4f /* In place copy is not necessary */ 1397 beq 7f /* Protect against 0 count */ 1398 mtctr r0 1399 bge cr1,2f 1400 1401 la r8,-4(r4) 1402 la r7,-4(r3) 14031: lwzu r0,4(r8) 1404 stwu r0,4(r7) 1405 bdnz 1b 1406 b 4f 1407 14082: slwi r0,r0,2 1409 add r8,r4,r0 1410 add r7,r3,r0 14113: lwzu r0,-4(r8) 1412 stwu r0,-4(r7) 1413 bdnz 3b 1414 1415/* 1416 * Now flush the cache: note that we must start from a cache aligned 1417 * address. Otherwise we might miss one cache line. 1418 */ 14194: cmpwi r6,0 1420 add r5,r3,r5 1421 beq 7f /* Always flush prefetch queue in any case */ 1422 subi r0,r6,1 1423 andc r3,r3,r0 1424 mr r4,r3 14255: dcbst 0,r4 1426 add r4,r4,r6 1427 cmplw r4,r5 1428 blt 5b 1429 sync /* Wait for all dcbst to complete on bus */ 1430 mr r4,r3 14316: icbi 0,r4 1432 add r4,r4,r6 1433 cmplw r4,r5 1434 blt 6b 14357: sync /* Wait for all icbi to complete on bus */ 1436 isync 1437 1438/* 1439 * We are done. Do not return, instead branch to second part of board 1440 * initialization, now running from RAM. 1441 */ 1442 1443 addi r0,r10,in_ram - _start + _START_OFFSET 1444 1445 /* 1446 * As IVPR is going to point RAM address, 1447 * Make sure IVOR15 has valid opcode to support debugger 1448 */ 1449 mtspr IVOR15,r0 1450 1451 /* 1452 * Re-point the IVPR at RAM 1453 */ 1454 mtspr IVPR,r10 1455 1456 mtlr r0 1457 blr /* NEVER RETURNS! */ 1458 .globl in_ram 1459in_ram: 1460 1461 /* 1462 * Relocation Function, r12 point to got2+0x8000 1463 * 1464 * Adjust got2 pointers, no need to check for 0, this code 1465 * already puts a few entries in the table. 1466 */ 1467 li r0,__got2_entries@sectoff@l 1468 la r3,GOT(_GOT2_TABLE_) 1469 lwz r11,GOT(_GOT2_TABLE_) 1470 mtctr r0 1471 sub r11,r3,r11 1472 addi r3,r3,-4 14731: lwzu r0,4(r3) 1474 cmpwi r0,0 1475 beq- 2f 1476 add r0,r0,r11 1477 stw r0,0(r3) 14782: bdnz 1b 1479 1480 /* 1481 * Now adjust the fixups and the pointers to the fixups 1482 * in case we need to move ourselves again. 1483 */ 1484 li r0,__fixup_entries@sectoff@l 1485 lwz r3,GOT(_FIXUP_TABLE_) 1486 cmpwi r0,0 1487 mtctr r0 1488 addi r3,r3,-4 1489 beq 4f 14903: lwzu r4,4(r3) 1491 lwzux r0,r4,r11 1492 cmpwi r0,0 1493 add r0,r0,r11 1494 stw r4,0(r3) 1495 beq- 5f 1496 stw r0,0(r4) 14975: bdnz 3b 14984: 1499clear_bss: 1500 /* 1501 * Now clear BSS segment 1502 */ 1503 lwz r3,GOT(__bss_start) 1504 lwz r4,GOT(__bss_end__) 1505 1506 cmplw 0,r3,r4 1507 beq 6f 1508 1509 li r0,0 15105: 1511 stw r0,0(r3) 1512 addi r3,r3,4 1513 cmplw 0,r3,r4 1514 bne 5b 15156: 1516 1517 mr r3,r9 /* Init Data pointer */ 1518 mr r4,r10 /* Destination Address */ 1519 bl board_init_r 1520 1521#ifndef CONFIG_NAND_SPL 1522 /* 1523 * Copy exception vector code to low memory 1524 * 1525 * r3: dest_addr 1526 * r7: source address, r8: end address, r9: target address 1527 */ 1528 .globl trap_init 1529trap_init: 1530 mflr r4 /* save link register */ 1531 GET_GOT 1532 lwz r7,GOT(_start_of_vectors) 1533 lwz r8,GOT(_end_of_vectors) 1534 1535 li r9,0x100 /* reset vector always at 0x100 */ 1536 1537 cmplw 0,r7,r8 1538 bgelr /* return if r7>=r8 - just in case */ 15391: 1540 lwz r0,0(r7) 1541 stw r0,0(r9) 1542 addi r7,r7,4 1543 addi r9,r9,4 1544 cmplw 0,r7,r8 1545 bne 1b 1546 1547 /* 1548 * relocate `hdlr' and `int_return' entries 1549 */ 1550 li r7,.L_CriticalInput - _start + _START_OFFSET 1551 bl trap_reloc 1552 li r7,.L_MachineCheck - _start + _START_OFFSET 1553 bl trap_reloc 1554 li r7,.L_DataStorage - _start + _START_OFFSET 1555 bl trap_reloc 1556 li r7,.L_InstStorage - _start + _START_OFFSET 1557 bl trap_reloc 1558 li r7,.L_ExtInterrupt - _start + _START_OFFSET 1559 bl trap_reloc 1560 li r7,.L_Alignment - _start + _START_OFFSET 1561 bl trap_reloc 1562 li r7,.L_ProgramCheck - _start + _START_OFFSET 1563 bl trap_reloc 1564 li r7,.L_FPUnavailable - _start + _START_OFFSET 1565 bl trap_reloc 1566 li r7,.L_Decrementer - _start + _START_OFFSET 1567 bl trap_reloc 1568 li r7,.L_IntervalTimer - _start + _START_OFFSET 1569 li r8,_end_of_vectors - _start + _START_OFFSET 15702: 1571 bl trap_reloc 1572 addi r7,r7,0x100 /* next exception vector */ 1573 cmplw 0,r7,r8 1574 blt 2b 1575 1576 /* Update IVORs as per relocated vector table address */ 1577 li r7,0x0100 1578 mtspr IVOR0,r7 /* 0: Critical input */ 1579 li r7,0x0200 1580 mtspr IVOR1,r7 /* 1: Machine check */ 1581 li r7,0x0300 1582 mtspr IVOR2,r7 /* 2: Data storage */ 1583 li r7,0x0400 1584 mtspr IVOR3,r7 /* 3: Instruction storage */ 1585 li r7,0x0500 1586 mtspr IVOR4,r7 /* 4: External interrupt */ 1587 li r7,0x0600 1588 mtspr IVOR5,r7 /* 5: Alignment */ 1589 li r7,0x0700 1590 mtspr IVOR6,r7 /* 6: Program check */ 1591 li r7,0x0800 1592 mtspr IVOR7,r7 /* 7: floating point unavailable */ 1593 li r7,0x0900 1594 mtspr IVOR8,r7 /* 8: System call */ 1595 /* 9: Auxiliary processor unavailable(unsupported) */ 1596 li r7,0x0a00 1597 mtspr IVOR10,r7 /* 10: Decrementer */ 1598 li r7,0x0b00 1599 mtspr IVOR11,r7 /* 11: Interval timer */ 1600 li r7,0x0c00 1601 mtspr IVOR12,r7 /* 12: Watchdog timer */ 1602 li r7,0x0d00 1603 mtspr IVOR13,r7 /* 13: Data TLB error */ 1604 li r7,0x0e00 1605 mtspr IVOR14,r7 /* 14: Instruction TLB error */ 1606 li r7,0x0f00 1607 mtspr IVOR15,r7 /* 15: Debug */ 1608 1609 lis r7,0x0 1610 mtspr IVPR,r7 1611 1612 mtlr r4 /* restore link register */ 1613 blr 1614 1615.globl unlock_ram_in_cache 1616unlock_ram_in_cache: 1617 /* invalidate the INIT_RAM section */ 1618 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1619 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1620 mfspr r4,L1CFG0 1621 andi. r4,r4,0x1ff 1622 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1623 mtctr r4 16241: dcbi r0,r3 1625 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1626 bdnz 1b 1627 sync 1628 1629 /* Invalidate the TLB entries for the cache */ 1630 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1631 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1632 tlbivax 0,r3 1633 addi r3,r3,0x1000 1634 tlbivax 0,r3 1635 addi r3,r3,0x1000 1636 tlbivax 0,r3 1637 addi r3,r3,0x1000 1638 tlbivax 0,r3 1639 isync 1640 blr 1641 1642.globl flush_dcache 1643flush_dcache: 1644 mfspr r3,SPRN_L1CFG0 1645 1646 rlwinm r5,r3,9,3 /* Extract cache block size */ 1647 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1648 * are currently defined. 1649 */ 1650 li r4,32 1651 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1652 * log2(number of ways) 1653 */ 1654 slw r5,r4,r5 /* r5 = cache block size */ 1655 1656 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1657 mulli r7,r7,13 /* An 8-way cache will require 13 1658 * loads per set. 1659 */ 1660 slw r7,r7,r6 1661 1662 /* save off HID0 and set DCFA */ 1663 mfspr r8,SPRN_HID0 1664 ori r9,r8,HID0_DCFA@l 1665 mtspr SPRN_HID0,r9 1666 isync 1667 1668 lis r4,0 1669 mtctr r7 1670 16711: lwz r3,0(r4) /* Load... */ 1672 add r4,r4,r5 1673 bdnz 1b 1674 1675 msync 1676 lis r4,0 1677 mtctr r7 1678 16791: dcbf 0,r4 /* ...and flush. */ 1680 add r4,r4,r5 1681 bdnz 1b 1682 1683 /* restore HID0 */ 1684 mtspr SPRN_HID0,r8 1685 isync 1686 1687 blr 1688 1689.globl setup_ivors 1690setup_ivors: 1691 1692#include "fixed_ivor.S" 1693 blr 1694#endif /* !CONFIG_NAND_SPL */ 1695