1a47a12beSStefan Roese/* 2a47a12beSStefan Roese * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * Copyright (C) 2003 Motorola,Inc. 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25a47a12beSStefan Roese * 26a47a12beSStefan Roese * The processor starts at 0xfffffffc and the code is first executed in the 27a47a12beSStefan Roese * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28a47a12beSStefan Roese * 29a47a12beSStefan Roese */ 30a47a12beSStefan Roese 31a47a12beSStefan Roese#include <config.h> 32a47a12beSStefan Roese#include <mpc85xx.h> 33a47a12beSStefan Roese#include <timestamp.h> 34a47a12beSStefan Roese#include <version.h> 35a47a12beSStefan Roese 36a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37a47a12beSStefan Roese 38a47a12beSStefan Roese#include <ppc_asm.tmpl> 39a47a12beSStefan Roese#include <ppc_defs.h> 40a47a12beSStefan Roese 41a47a12beSStefan Roese#include <asm/cache.h> 42a47a12beSStefan Roese#include <asm/mmu.h> 43a47a12beSStefan Roese 44a47a12beSStefan Roese#ifndef CONFIG_IDENT_STRING 45a47a12beSStefan Roese#define CONFIG_IDENT_STRING "" 46a47a12beSStefan Roese#endif 47a47a12beSStefan Roese 48a47a12beSStefan Roese#undef MSR_KERNEL 49a47a12beSStefan Roese#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 50a47a12beSStefan Roese 51a47a12beSStefan Roese/* 52a47a12beSStefan Roese * Set up GOT: Global Offset Table 53a47a12beSStefan Roese * 54a47a12beSStefan Roese * Use r12 to access the GOT 55a47a12beSStefan Roese */ 56a47a12beSStefan Roese START_GOT 57a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 58a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 59a47a12beSStefan Roese 60a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 61a47a12beSStefan Roese GOT_ENTRY(_start) 62a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 63a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 64a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 65a47a12beSStefan Roese#endif 66a47a12beSStefan Roese 67a47a12beSStefan Roese GOT_ENTRY(__init_end) 68a47a12beSStefan Roese GOT_ENTRY(_end) 69a47a12beSStefan Roese GOT_ENTRY(__bss_start) 70a47a12beSStefan Roese END_GOT 71a47a12beSStefan Roese 72a47a12beSStefan Roese/* 73a47a12beSStefan Roese * e500 Startup -- after reset only the last 4KB of the effective 74a47a12beSStefan Roese * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 75a47a12beSStefan Roese * section is located at THIS LAST page and basically does three 76a47a12beSStefan Roese * things: clear some registers, set up exception tables and 77a47a12beSStefan Roese * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 78a47a12beSStefan Roese * continue the boot procedure. 79a47a12beSStefan Roese 80a47a12beSStefan Roese * Once the boot rom is mapped by TLB entries we can proceed 81a47a12beSStefan Roese * with normal startup. 82a47a12beSStefan Roese * 83a47a12beSStefan Roese */ 84a47a12beSStefan Roese 85a47a12beSStefan Roese .section .bootpg,"ax" 86a47a12beSStefan Roese .globl _start_e500 87a47a12beSStefan Roese 88a47a12beSStefan Roese_start_e500: 89a47a12beSStefan Roese 90a47a12beSStefan Roese/* clear registers/arrays not reset by hardware */ 91a47a12beSStefan Roese 92a47a12beSStefan Roese /* L1 */ 93a47a12beSStefan Roese li r0,2 94a47a12beSStefan Roese mtspr L1CSR0,r0 /* invalidate d-cache */ 95a47a12beSStefan Roese mtspr L1CSR1,r0 /* invalidate i-cache */ 96a47a12beSStefan Roese 97a47a12beSStefan Roese mfspr r1,DBSR 98a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all valid bits */ 99a47a12beSStefan Roese 100a47a12beSStefan Roese /* 101a47a12beSStefan Roese * Enable L1 Caches early 102a47a12beSStefan Roese * 103a47a12beSStefan Roese */ 104a47a12beSStefan Roese 105a47a12beSStefan Roese#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 106a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 107a47a12beSStefan Roese li r2,(32 + 0) 108a47a12beSStefan Roese mtspr L1CSR2,r2 109a47a12beSStefan Roese#endif 110a47a12beSStefan Roese 111a47a12beSStefan Roese /* Enable/invalidate the I-Cache */ 112a47a12beSStefan Roese lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 113a47a12beSStefan Roese ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 114a47a12beSStefan Roese mtspr SPRN_L1CSR1,r2 115a47a12beSStefan Roese1: 116a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 117a47a12beSStefan Roese and. r1,r3,r2 118a47a12beSStefan Roese bne 1b 119a47a12beSStefan Roese 120a47a12beSStefan Roese lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 121a47a12beSStefan Roese ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 122a47a12beSStefan Roese mtspr SPRN_L1CSR1,r3 123a47a12beSStefan Roese isync 124a47a12beSStefan Roese2: 125a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 126a47a12beSStefan Roese andi. r1,r3,L1CSR1_ICE@l 127a47a12beSStefan Roese beq 2b 128a47a12beSStefan Roese 129a47a12beSStefan Roese /* Enable/invalidate the D-Cache */ 130a47a12beSStefan Roese lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 131a47a12beSStefan Roese ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 132a47a12beSStefan Roese mtspr SPRN_L1CSR0,r2 133a47a12beSStefan Roese1: 134a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 135a47a12beSStefan Roese and. r1,r3,r2 136a47a12beSStefan Roese bne 1b 137a47a12beSStefan Roese 138a47a12beSStefan Roese lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 139a47a12beSStefan Roese ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 140a47a12beSStefan Roese mtspr SPRN_L1CSR0,r3 141a47a12beSStefan Roese isync 142a47a12beSStefan Roese2: 143a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 144a47a12beSStefan Roese andi. r1,r3,L1CSR0_DCE@l 145a47a12beSStefan Roese beq 2b 146a47a12beSStefan Roese 147a47a12beSStefan Roese /* Setup interrupt vectors */ 14814d0a02aSWolfgang Denk lis r1,CONFIG_SYS_TEXT_BASE@h 149a47a12beSStefan Roese mtspr IVPR,r1 150a47a12beSStefan Roese 151a47a12beSStefan Roese li r1,0x0100 152a47a12beSStefan Roese mtspr IVOR0,r1 /* 0: Critical input */ 153a47a12beSStefan Roese li r1,0x0200 154a47a12beSStefan Roese mtspr IVOR1,r1 /* 1: Machine check */ 155a47a12beSStefan Roese li r1,0x0300 156a47a12beSStefan Roese mtspr IVOR2,r1 /* 2: Data storage */ 157a47a12beSStefan Roese li r1,0x0400 158a47a12beSStefan Roese mtspr IVOR3,r1 /* 3: Instruction storage */ 159a47a12beSStefan Roese li r1,0x0500 160a47a12beSStefan Roese mtspr IVOR4,r1 /* 4: External interrupt */ 161a47a12beSStefan Roese li r1,0x0600 162a47a12beSStefan Roese mtspr IVOR5,r1 /* 5: Alignment */ 163a47a12beSStefan Roese li r1,0x0700 164a47a12beSStefan Roese mtspr IVOR6,r1 /* 6: Program check */ 165a47a12beSStefan Roese li r1,0x0800 166a47a12beSStefan Roese mtspr IVOR7,r1 /* 7: floating point unavailable */ 167a47a12beSStefan Roese li r1,0x0900 168a47a12beSStefan Roese mtspr IVOR8,r1 /* 8: System call */ 169a47a12beSStefan Roese /* 9: Auxiliary processor unavailable(unsupported) */ 170a47a12beSStefan Roese li r1,0x0a00 171a47a12beSStefan Roese mtspr IVOR10,r1 /* 10: Decrementer */ 172a47a12beSStefan Roese li r1,0x0b00 173a47a12beSStefan Roese mtspr IVOR11,r1 /* 11: Interval timer */ 174a47a12beSStefan Roese li r1,0x0c00 175a47a12beSStefan Roese mtspr IVOR12,r1 /* 12: Watchdog timer */ 176a47a12beSStefan Roese li r1,0x0d00 177a47a12beSStefan Roese mtspr IVOR13,r1 /* 13: Data TLB error */ 178a47a12beSStefan Roese li r1,0x0e00 179a47a12beSStefan Roese mtspr IVOR14,r1 /* 14: Instruction TLB error */ 180a47a12beSStefan Roese li r1,0x0f00 181a47a12beSStefan Roese mtspr IVOR15,r1 /* 15: Debug */ 182a47a12beSStefan Roese 183a47a12beSStefan Roese /* Clear and set up some registers. */ 184a47a12beSStefan Roese li r0,0x0000 185a47a12beSStefan Roese lis r1,0xffff 186a47a12beSStefan Roese mtspr DEC,r0 /* prevent dec exceptions */ 187a47a12beSStefan Roese mttbl r0 /* prevent fit & wdt exceptions */ 188a47a12beSStefan Roese mttbu r0 189a47a12beSStefan Roese mtspr TSR,r1 /* clear all timer exception status */ 190a47a12beSStefan Roese mtspr TCR,r0 /* disable all */ 191a47a12beSStefan Roese mtspr ESR,r0 /* clear exception syndrome register */ 192a47a12beSStefan Roese mtspr MCSR,r0 /* machine check syndrome register */ 193a47a12beSStefan Roese mtxer r0 /* clear integer exception register */ 194a47a12beSStefan Roese 195a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 196a47a12beSStefan Roese mtspr MAS8,r0 /* make sure MAS8 is clear */ 197a47a12beSStefan Roese#endif 198a47a12beSStefan Roese 199a47a12beSStefan Roese /* Enable Time Base and Select Time Base Clock */ 200a47a12beSStefan Roese lis r0,HID0_EMCP@h /* Enable machine check */ 201a47a12beSStefan Roese#if defined(CONFIG_ENABLE_36BIT_PHYS) 202a47a12beSStefan Roese ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 203a47a12beSStefan Roese#endif 204a47a12beSStefan Roese#ifndef CONFIG_E500MC 205a47a12beSStefan Roese ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 206a47a12beSStefan Roese#endif 207a47a12beSStefan Roese mtspr HID0,r0 208a47a12beSStefan Roese 209a47a12beSStefan Roese#ifndef CONFIG_E500MC 210a47a12beSStefan Roese li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 211a47a12beSStefan Roese mfspr r3,PVR 212a47a12beSStefan Roese andi. r3,r3, 0xff 213a47a12beSStefan Roese cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 214a47a12beSStefan Roese blt 1f 215a47a12beSStefan Roese /* Set MBDD bit also */ 216a47a12beSStefan Roese ori r0, r0, HID1_MBDD@l 217a47a12beSStefan Roese1: 218a47a12beSStefan Roese mtspr HID1,r0 219a47a12beSStefan Roese#endif 220a47a12beSStefan Roese 221a47a12beSStefan Roese /* Enable Branch Prediction */ 222a47a12beSStefan Roese#if defined(CONFIG_BTB) 223a47a12beSStefan Roese lis r0,BUCSR_ENABLE@h 224a47a12beSStefan Roese ori r0,r0,BUCSR_ENABLE@l 225a47a12beSStefan Roese mtspr SPRN_BUCSR,r0 226a47a12beSStefan Roese#endif 227a47a12beSStefan Roese 228a47a12beSStefan Roese#if defined(CONFIG_SYS_INIT_DBCR) 229a47a12beSStefan Roese lis r1,0xffff 230a47a12beSStefan Roese ori r1,r1,0xffff 231a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all status bits */ 232a47a12beSStefan Roese lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 233a47a12beSStefan Roese ori r0,r0,CONFIG_SYS_INIT_DBCR@l 234a47a12beSStefan Roese mtspr DBCR0,r0 235a47a12beSStefan Roese#endif 236a47a12beSStefan Roese 237a47a12beSStefan Roese#ifdef CONFIG_MPC8569 238a47a12beSStefan Roese#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 239a47a12beSStefan Roese#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 240a47a12beSStefan Roese 241a47a12beSStefan Roese /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 242a47a12beSStefan Roese * use address space which is more than 12bits, and it must be done in 243a47a12beSStefan Roese * the 4K boot page. So we set this bit here. 244a47a12beSStefan Roese */ 245a47a12beSStefan Roese 246a47a12beSStefan Roese /* create a temp mapping TLB0[0] for LBCR */ 247a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 248a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 249a47a12beSStefan Roese 250a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 251a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 252a47a12beSStefan Roese 253a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 254a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 255a47a12beSStefan Roese 256a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 257a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@h 258a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 259a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@l 260a47a12beSStefan Roese 261a47a12beSStefan Roese mtspr MAS0,r6 262a47a12beSStefan Roese mtspr MAS1,r7 263a47a12beSStefan Roese mtspr MAS2,r8 264a47a12beSStefan Roese mtspr MAS3,r9 265a47a12beSStefan Roese isync 266a47a12beSStefan Roese msync 267a47a12beSStefan Roese tlbwe 268a47a12beSStefan Roese 269a47a12beSStefan Roese /* Set LBCR register */ 270a47a12beSStefan Roese lis r4,CONFIG_SYS_LBCR_ADDR@h 271a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 272a47a12beSStefan Roese 273a47a12beSStefan Roese lis r5,CONFIG_SYS_LBC_LBCR@h 274a47a12beSStefan Roese ori r5,r5,CONFIG_SYS_LBC_LBCR@l 275a47a12beSStefan Roese stw r5,0(r4) 276a47a12beSStefan Roese isync 277a47a12beSStefan Roese 278a47a12beSStefan Roese /* invalidate this temp TLB */ 279a47a12beSStefan Roese lis r4,CONFIG_SYS_LBC_ADDR@h 280a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBC_ADDR@l 281a47a12beSStefan Roese tlbivax 0,r4 282a47a12beSStefan Roese isync 283a47a12beSStefan Roese 284a47a12beSStefan Roese#endif /* CONFIG_MPC8569 */ 285a47a12beSStefan Roese 286a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 287a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 288a47a12beSStefan Roese 289a47a12beSStefan Roese#ifndef CONFIG_SYS_RAMBOOT 290a47a12beSStefan Roese /* create a temp mapping in AS=1 to the 4M boot window */ 291a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 292a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 293a47a12beSStefan Roese 29414d0a02aSWolfgang Denk lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 29514d0a02aSWolfgang Denk ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 296a47a12beSStefan Roese 297a47a12beSStefan Roese /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 298a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 299a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 300a47a12beSStefan Roese#else 301a47a12beSStefan Roese /* 30214d0a02aSWolfgang Denk * create a temp mapping in AS=1 to the 1M CONFIG_SYS_TEXT_BASE space, the main 30314d0a02aSWolfgang Denk * image has been relocated to CONFIG_SYS_TEXT_BASE on the second stage. 304a47a12beSStefan Roese */ 305a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 306a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 307a47a12beSStefan Roese 30814d0a02aSWolfgang Denk lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@h 30914d0a02aSWolfgang Denk ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, (MAS2_I|MAS2_G))@l 310a47a12beSStefan Roese 31114d0a02aSWolfgang Denk lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 31214d0a02aSWolfgang Denk ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 313a47a12beSStefan Roese#endif 314a47a12beSStefan Roese 315a47a12beSStefan Roese mtspr MAS0,r6 316a47a12beSStefan Roese mtspr MAS1,r7 317a47a12beSStefan Roese mtspr MAS2,r8 318a47a12beSStefan Roese mtspr MAS3,r9 319a47a12beSStefan Roese isync 320a47a12beSStefan Roese msync 321a47a12beSStefan Roese tlbwe 322a47a12beSStefan Roese 323a47a12beSStefan Roese /* create a temp mapping in AS=1 to the stack */ 324a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 325a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 326a47a12beSStefan Roese 327a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 328a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 329a47a12beSStefan Roese 330a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 331a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 332a47a12beSStefan Roese 333a3f18529Syork#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 334a3f18529Syork defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 335a3f18529Syork lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 336a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@h 337a3f18529Syork ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 338a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@l 339a3f18529Syork li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 340a3f18529Syork mtspr MAS7,r10 341a3f18529Syork#else 342a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 343a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 344a3f18529Syork#endif 345a47a12beSStefan Roese 346a47a12beSStefan Roese mtspr MAS0,r6 347a47a12beSStefan Roese mtspr MAS1,r7 348a47a12beSStefan Roese mtspr MAS2,r8 349a47a12beSStefan Roese mtspr MAS3,r9 350a47a12beSStefan Roese isync 351a47a12beSStefan Roese msync 352a47a12beSStefan Roese tlbwe 353a47a12beSStefan Roese 354a47a12beSStefan Roese lis r6,MSR_IS|MSR_DS@h 355a47a12beSStefan Roese ori r6,r6,MSR_IS|MSR_DS@l 356a47a12beSStefan Roese lis r7,switch_as@h 357a47a12beSStefan Roese ori r7,r7,switch_as@l 358a47a12beSStefan Roese 359a47a12beSStefan Roese mtspr SPRN_SRR0,r7 360a47a12beSStefan Roese mtspr SPRN_SRR1,r6 361a47a12beSStefan Roese rfi 362a47a12beSStefan Roese 363a47a12beSStefan Roeseswitch_as: 364a47a12beSStefan Roese/* L1 DCache is used for initial RAM */ 365a47a12beSStefan Roese 366a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 367a47a12beSStefan Roese */ 368a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 369a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 370a47a12beSStefan Roese mfspr r2, L1CFG0 371a47a12beSStefan Roese andi. r2, r2, 0x1ff 372a47a12beSStefan Roese /* cache size * 1024 / (2 * L1 line size) */ 373a47a12beSStefan Roese slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 374a47a12beSStefan Roese mtctr r2 375a47a12beSStefan Roese li r0,0 376a47a12beSStefan Roese1: 377a47a12beSStefan Roese dcbz r0,r3 378a47a12beSStefan Roese dcbtls 0,r0,r3 379a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 380a47a12beSStefan Roese bdnz 1b 381a47a12beSStefan Roese 382a47a12beSStefan Roese /* Jump out the last 4K page and continue to 'normal' start */ 383a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 384a47a12beSStefan Roese b _start_cont 385a47a12beSStefan Roese#else 386a47a12beSStefan Roese /* Calculate absolute address in FLASH and jump there */ 387a47a12beSStefan Roese /*--------------------------------------------------------------*/ 388a47a12beSStefan Roese lis r3,CONFIG_SYS_MONITOR_BASE@h 389a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 390a47a12beSStefan Roese addi r3,r3,_start_cont - _start + _START_OFFSET 391a47a12beSStefan Roese mtlr r3 392a47a12beSStefan Roese blr 393a47a12beSStefan Roese#endif 394a47a12beSStefan Roese 395a47a12beSStefan Roese .text 396a47a12beSStefan Roese .globl _start 397a47a12beSStefan Roese_start: 398a47a12beSStefan Roese .long 0x27051956 /* U-BOOT Magic Number */ 399a47a12beSStefan Roese .globl version_string 400a47a12beSStefan Roeseversion_string: 401a47a12beSStefan Roese .ascii U_BOOT_VERSION 402a47a12beSStefan Roese .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" 403a47a12beSStefan Roese .ascii CONFIG_IDENT_STRING, "\0" 404a47a12beSStefan Roese 405a47a12beSStefan Roese .align 4 406a47a12beSStefan Roese .globl _start_cont 407a47a12beSStefan Roese_start_cont: 408a47a12beSStefan Roese /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 409a47a12beSStefan Roese lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 410a47a12beSStefan Roese ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 411a47a12beSStefan Roese 412a47a12beSStefan Roese li r0,0 413a47a12beSStefan Roese stwu r0,-4(r1) 414a47a12beSStefan Roese stwu r0,-4(r1) /* Terminate call chain */ 415a47a12beSStefan Roese 416a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 417a47a12beSStefan Roese lis r0,RESET_VECTOR@h /* Address of reset vector */ 418a47a12beSStefan Roese ori r0,r0,RESET_VECTOR@l 419a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 420a47a12beSStefan Roese stw r0,+12(r1) /* Save return addr (underflow vect) */ 421a47a12beSStefan Roese 422a47a12beSStefan Roese GET_GOT 423a47a12beSStefan Roese bl cpu_init_early_f 424a47a12beSStefan Roese 425a47a12beSStefan Roese /* switch back to AS = 0 */ 426a47a12beSStefan Roese lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 427a47a12beSStefan Roese ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 428a47a12beSStefan Roese mtmsr r3 429a47a12beSStefan Roese isync 430a47a12beSStefan Roese 431a47a12beSStefan Roese bl cpu_init_f 432a47a12beSStefan Roese bl board_init_f 433a47a12beSStefan Roese isync 434a47a12beSStefan Roese 43552ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 43652ebd9c1SPeter Tyser 437a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 438a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 439a47a12beSStefan Roese .globl _start_of_vectors 440a47a12beSStefan Roese_start_of_vectors: 441a47a12beSStefan Roese 442a47a12beSStefan Roese/* Critical input. */ 443a47a12beSStefan Roese CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 444a47a12beSStefan Roese 445a47a12beSStefan Roese/* Machine check */ 446a47a12beSStefan Roese MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 447a47a12beSStefan Roese 448a47a12beSStefan Roese/* Data Storage exception. */ 449a47a12beSStefan Roese STD_EXCEPTION(0x0300, DataStorage, UnknownException) 450a47a12beSStefan Roese 451a47a12beSStefan Roese/* Instruction Storage exception. */ 452a47a12beSStefan Roese STD_EXCEPTION(0x0400, InstStorage, UnknownException) 453a47a12beSStefan Roese 454a47a12beSStefan Roese/* External Interrupt exception. */ 455a47a12beSStefan Roese STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 456a47a12beSStefan Roese 457a47a12beSStefan Roese/* Alignment exception. */ 458a47a12beSStefan Roese . = 0x0600 459a47a12beSStefan RoeseAlignment: 460a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 461a47a12beSStefan Roese mfspr r4,DAR 462a47a12beSStefan Roese stw r4,_DAR(r21) 463a47a12beSStefan Roese mfspr r5,DSISR 464a47a12beSStefan Roese stw r5,_DSISR(r21) 465a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 466a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 467a47a12beSStefan Roese 468a47a12beSStefan Roese/* Program check exception */ 469a47a12beSStefan Roese . = 0x0700 470a47a12beSStefan RoeseProgramCheck: 471a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 472a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 473a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 474a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 475a47a12beSStefan Roese 476a47a12beSStefan Roese /* No FPU on MPC85xx. This exception is not supposed to happen. 477a47a12beSStefan Roese */ 478a47a12beSStefan Roese STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 479a47a12beSStefan Roese 480a47a12beSStefan Roese . = 0x0900 481a47a12beSStefan Roese/* 482a47a12beSStefan Roese * r0 - SYSCALL number 483a47a12beSStefan Roese * r3-... arguments 484a47a12beSStefan Roese */ 485a47a12beSStefan RoeseSystemCall: 486a47a12beSStefan Roese addis r11,r0,0 /* get functions table addr */ 487a47a12beSStefan Roese ori r11,r11,0 /* Note: this code is patched in trap_init */ 488a47a12beSStefan Roese addis r12,r0,0 /* get number of functions */ 489a47a12beSStefan Roese ori r12,r12,0 490a47a12beSStefan Roese 491a47a12beSStefan Roese cmplw 0,r0,r12 492a47a12beSStefan Roese bge 1f 493a47a12beSStefan Roese 494a47a12beSStefan Roese rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 495a47a12beSStefan Roese add r11,r11,r0 496a47a12beSStefan Roese lwz r11,0(r11) 497a47a12beSStefan Roese 498a47a12beSStefan Roese li r20,0xd00-4 /* Get stack pointer */ 499a47a12beSStefan Roese lwz r12,0(r20) 500a47a12beSStefan Roese subi r12,r12,12 /* Adjust stack pointer */ 501a47a12beSStefan Roese li r0,0xc00+_end_back-SystemCall 502a47a12beSStefan Roese cmplw 0,r0,r12 /* Check stack overflow */ 503a47a12beSStefan Roese bgt 1f 504a47a12beSStefan Roese stw r12,0(r20) 505a47a12beSStefan Roese 506a47a12beSStefan Roese mflr r0 507a47a12beSStefan Roese stw r0,0(r12) 508a47a12beSStefan Roese mfspr r0,SRR0 509a47a12beSStefan Roese stw r0,4(r12) 510a47a12beSStefan Roese mfspr r0,SRR1 511a47a12beSStefan Roese stw r0,8(r12) 512a47a12beSStefan Roese 513a47a12beSStefan Roese li r12,0xc00+_back-SystemCall 514a47a12beSStefan Roese mtlr r12 515a47a12beSStefan Roese mtspr SRR0,r11 516a47a12beSStefan Roese 517a47a12beSStefan Roese1: SYNC 518a47a12beSStefan Roese rfi 519a47a12beSStefan Roese_back: 520a47a12beSStefan Roese 521a47a12beSStefan Roese mfmsr r11 /* Disable interrupts */ 522a47a12beSStefan Roese li r12,0 523a47a12beSStefan Roese ori r12,r12,MSR_EE 524a47a12beSStefan Roese andc r11,r11,r12 525a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 526a47a12beSStefan Roese mtmsr r11 527a47a12beSStefan Roese SYNC 528a47a12beSStefan Roese 529a47a12beSStefan Roese li r12,0xd00-4 /* restore regs */ 530a47a12beSStefan Roese lwz r12,0(r12) 531a47a12beSStefan Roese 532a47a12beSStefan Roese lwz r11,0(r12) 533a47a12beSStefan Roese mtlr r11 534a47a12beSStefan Roese lwz r11,4(r12) 535a47a12beSStefan Roese mtspr SRR0,r11 536a47a12beSStefan Roese lwz r11,8(r12) 537a47a12beSStefan Roese mtspr SRR1,r11 538a47a12beSStefan Roese 539a47a12beSStefan Roese addi r12,r12,12 /* Adjust stack pointer */ 540a47a12beSStefan Roese li r20,0xd00-4 541a47a12beSStefan Roese stw r12,0(r20) 542a47a12beSStefan Roese 543a47a12beSStefan Roese SYNC 544a47a12beSStefan Roese rfi 545a47a12beSStefan Roese_end_back: 546a47a12beSStefan Roese 547a47a12beSStefan Roese STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 548a47a12beSStefan Roese STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 549a47a12beSStefan Roese STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 550a47a12beSStefan Roese 551a47a12beSStefan Roese STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 552a47a12beSStefan Roese STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 553a47a12beSStefan Roese 554a47a12beSStefan Roese CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 555a47a12beSStefan Roese 556a47a12beSStefan Roese .globl _end_of_vectors 557a47a12beSStefan Roese_end_of_vectors: 558a47a12beSStefan Roese 559a47a12beSStefan Roese 560a47a12beSStefan Roese . = . + (0x100 - ( . & 0xff )) /* align for debug */ 561a47a12beSStefan Roese 562a47a12beSStefan Roese/* 563a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 564a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 565a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 566a47a12beSStefan Roese */ 567a47a12beSStefan Roese .globl transfer_to_handler 568a47a12beSStefan Roesetransfer_to_handler: 569a47a12beSStefan Roese stw r22,_NIP(r21) 570a47a12beSStefan Roese lis r22,MSR_POW@h 571a47a12beSStefan Roese andc r23,r23,r22 572a47a12beSStefan Roese stw r23,_MSR(r21) 573a47a12beSStefan Roese SAVE_GPR(7, r21) 574a47a12beSStefan Roese SAVE_4GPRS(8, r21) 575a47a12beSStefan Roese SAVE_8GPRS(12, r21) 576a47a12beSStefan Roese SAVE_8GPRS(24, r21) 577a47a12beSStefan Roese 578a47a12beSStefan Roese mflr r23 579a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 580a47a12beSStefan Roese stw r24,TRAP(r21) 581a47a12beSStefan Roese li r22,0 582a47a12beSStefan Roese stw r22,RESULT(r21) 583a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 584a47a12beSStefan Roese 585a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 586a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 587a47a12beSStefan Roese mtspr SRR0,r24 588a47a12beSStefan Roese mtspr SRR1,r20 589a47a12beSStefan Roese mtlr r23 590a47a12beSStefan Roese SYNC 591a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 592a47a12beSStefan Roese 593a47a12beSStefan Roeseint_return: 594a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 595a47a12beSStefan Roese li r4,0 596a47a12beSStefan Roese ori r4,r4,MSR_EE 597a47a12beSStefan Roese andc r28,r28,r4 598a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 599a47a12beSStefan Roese mtmsr r28 600a47a12beSStefan Roese SYNC 601a47a12beSStefan Roese lwz r2,_CTR(r1) 602a47a12beSStefan Roese lwz r0,_LINK(r1) 603a47a12beSStefan Roese mtctr r2 604a47a12beSStefan Roese mtlr r0 605a47a12beSStefan Roese lwz r2,_XER(r1) 606a47a12beSStefan Roese lwz r0,_CCR(r1) 607a47a12beSStefan Roese mtspr XER,r2 608a47a12beSStefan Roese mtcrf 0xFF,r0 609a47a12beSStefan Roese REST_10GPRS(3, r1) 610a47a12beSStefan Roese REST_10GPRS(13, r1) 611a47a12beSStefan Roese REST_8GPRS(23, r1) 612a47a12beSStefan Roese REST_GPR(31, r1) 613a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 614a47a12beSStefan Roese lwz r0,_MSR(r1) 615a47a12beSStefan Roese mtspr SRR0,r2 616a47a12beSStefan Roese mtspr SRR1,r0 617a47a12beSStefan Roese lwz r0,GPR0(r1) 618a47a12beSStefan Roese lwz r2,GPR2(r1) 619a47a12beSStefan Roese lwz r1,GPR1(r1) 620a47a12beSStefan Roese SYNC 621a47a12beSStefan Roese rfi 622a47a12beSStefan Roese 623a47a12beSStefan Roesecrit_return: 624a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 625a47a12beSStefan Roese li r4,0 626a47a12beSStefan Roese ori r4,r4,MSR_EE 627a47a12beSStefan Roese andc r28,r28,r4 628a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 629a47a12beSStefan Roese mtmsr r28 630a47a12beSStefan Roese SYNC 631a47a12beSStefan Roese lwz r2,_CTR(r1) 632a47a12beSStefan Roese lwz r0,_LINK(r1) 633a47a12beSStefan Roese mtctr r2 634a47a12beSStefan Roese mtlr r0 635a47a12beSStefan Roese lwz r2,_XER(r1) 636a47a12beSStefan Roese lwz r0,_CCR(r1) 637a47a12beSStefan Roese mtspr XER,r2 638a47a12beSStefan Roese mtcrf 0xFF,r0 639a47a12beSStefan Roese REST_10GPRS(3, r1) 640a47a12beSStefan Roese REST_10GPRS(13, r1) 641a47a12beSStefan Roese REST_8GPRS(23, r1) 642a47a12beSStefan Roese REST_GPR(31, r1) 643a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 644a47a12beSStefan Roese lwz r0,_MSR(r1) 645a47a12beSStefan Roese mtspr SPRN_CSRR0,r2 646a47a12beSStefan Roese mtspr SPRN_CSRR1,r0 647a47a12beSStefan Roese lwz r0,GPR0(r1) 648a47a12beSStefan Roese lwz r2,GPR2(r1) 649a47a12beSStefan Roese lwz r1,GPR1(r1) 650a47a12beSStefan Roese SYNC 651a47a12beSStefan Roese rfci 652a47a12beSStefan Roese 653a47a12beSStefan Roesemck_return: 654a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 655a47a12beSStefan Roese li r4,0 656a47a12beSStefan Roese ori r4,r4,MSR_EE 657a47a12beSStefan Roese andc r28,r28,r4 658a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 659a47a12beSStefan Roese mtmsr r28 660a47a12beSStefan Roese SYNC 661a47a12beSStefan Roese lwz r2,_CTR(r1) 662a47a12beSStefan Roese lwz r0,_LINK(r1) 663a47a12beSStefan Roese mtctr r2 664a47a12beSStefan Roese mtlr r0 665a47a12beSStefan Roese lwz r2,_XER(r1) 666a47a12beSStefan Roese lwz r0,_CCR(r1) 667a47a12beSStefan Roese mtspr XER,r2 668a47a12beSStefan Roese mtcrf 0xFF,r0 669a47a12beSStefan Roese REST_10GPRS(3, r1) 670a47a12beSStefan Roese REST_10GPRS(13, r1) 671a47a12beSStefan Roese REST_8GPRS(23, r1) 672a47a12beSStefan Roese REST_GPR(31, r1) 673a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 674a47a12beSStefan Roese lwz r0,_MSR(r1) 675a47a12beSStefan Roese mtspr SPRN_MCSRR0,r2 676a47a12beSStefan Roese mtspr SPRN_MCSRR1,r0 677a47a12beSStefan Roese lwz r0,GPR0(r1) 678a47a12beSStefan Roese lwz r2,GPR2(r1) 679a47a12beSStefan Roese lwz r1,GPR1(r1) 680a47a12beSStefan Roese SYNC 681a47a12beSStefan Roese rfmci 682a47a12beSStefan Roese 683a47a12beSStefan Roese/* Cache functions. 684a47a12beSStefan Roese*/ 685a47a12beSStefan Roese.globl invalidate_icache 686a47a12beSStefan Roeseinvalidate_icache: 687a47a12beSStefan Roese mfspr r0,L1CSR1 688a47a12beSStefan Roese ori r0,r0,L1CSR1_ICFI 689a47a12beSStefan Roese msync 690a47a12beSStefan Roese isync 691a47a12beSStefan Roese mtspr L1CSR1,r0 692a47a12beSStefan Roese isync 693a47a12beSStefan Roese blr /* entire I cache */ 694a47a12beSStefan Roese 695a47a12beSStefan Roese.globl invalidate_dcache 696a47a12beSStefan Roeseinvalidate_dcache: 697a47a12beSStefan Roese mfspr r0,L1CSR0 698a47a12beSStefan Roese ori r0,r0,L1CSR0_DCFI 699a47a12beSStefan Roese msync 700a47a12beSStefan Roese isync 701a47a12beSStefan Roese mtspr L1CSR0,r0 702a47a12beSStefan Roese isync 703a47a12beSStefan Roese blr 704a47a12beSStefan Roese 705a47a12beSStefan Roese .globl icache_enable 706a47a12beSStefan Roeseicache_enable: 707a47a12beSStefan Roese mflr r8 708a47a12beSStefan Roese bl invalidate_icache 709a47a12beSStefan Roese mtlr r8 710a47a12beSStefan Roese isync 711a47a12beSStefan Roese mfspr r4,L1CSR1 712a47a12beSStefan Roese ori r4,r4,0x0001 713a47a12beSStefan Roese oris r4,r4,0x0001 714a47a12beSStefan Roese mtspr L1CSR1,r4 715a47a12beSStefan Roese isync 716a47a12beSStefan Roese blr 717a47a12beSStefan Roese 718a47a12beSStefan Roese .globl icache_disable 719a47a12beSStefan Roeseicache_disable: 720a47a12beSStefan Roese mfspr r0,L1CSR1 721a47a12beSStefan Roese lis r3,0 722a47a12beSStefan Roese ori r3,r3,L1CSR1_ICE 723a47a12beSStefan Roese andc r0,r0,r3 724a47a12beSStefan Roese mtspr L1CSR1,r0 725a47a12beSStefan Roese isync 726a47a12beSStefan Roese blr 727a47a12beSStefan Roese 728a47a12beSStefan Roese .globl icache_status 729a47a12beSStefan Roeseicache_status: 730a47a12beSStefan Roese mfspr r3,L1CSR1 731a47a12beSStefan Roese andi. r3,r3,L1CSR1_ICE 732a47a12beSStefan Roese blr 733a47a12beSStefan Roese 734a47a12beSStefan Roese .globl dcache_enable 735a47a12beSStefan Roesedcache_enable: 736a47a12beSStefan Roese mflr r8 737a47a12beSStefan Roese bl invalidate_dcache 738a47a12beSStefan Roese mtlr r8 739a47a12beSStefan Roese isync 740a47a12beSStefan Roese mfspr r0,L1CSR0 741a47a12beSStefan Roese ori r0,r0,0x0001 742a47a12beSStefan Roese oris r0,r0,0x0001 743a47a12beSStefan Roese msync 744a47a12beSStefan Roese isync 745a47a12beSStefan Roese mtspr L1CSR0,r0 746a47a12beSStefan Roese isync 747a47a12beSStefan Roese blr 748a47a12beSStefan Roese 749a47a12beSStefan Roese .globl dcache_disable 750a47a12beSStefan Roesedcache_disable: 751a47a12beSStefan Roese mfspr r3,L1CSR0 752a47a12beSStefan Roese lis r4,0 753a47a12beSStefan Roese ori r4,r4,L1CSR0_DCE 754a47a12beSStefan Roese andc r3,r3,r4 755a47a12beSStefan Roese mtspr L1CSR0,r0 756a47a12beSStefan Roese isync 757a47a12beSStefan Roese blr 758a47a12beSStefan Roese 759a47a12beSStefan Roese .globl dcache_status 760a47a12beSStefan Roesedcache_status: 761a47a12beSStefan Roese mfspr r3,L1CSR0 762a47a12beSStefan Roese andi. r3,r3,L1CSR0_DCE 763a47a12beSStefan Roese blr 764a47a12beSStefan Roese 765a47a12beSStefan Roese .globl get_pir 766a47a12beSStefan Roeseget_pir: 767a47a12beSStefan Roese mfspr r3,PIR 768a47a12beSStefan Roese blr 769a47a12beSStefan Roese 770a47a12beSStefan Roese .globl get_pvr 771a47a12beSStefan Roeseget_pvr: 772a47a12beSStefan Roese mfspr r3,PVR 773a47a12beSStefan Roese blr 774a47a12beSStefan Roese 775a47a12beSStefan Roese .globl get_svr 776a47a12beSStefan Roeseget_svr: 777a47a12beSStefan Roese mfspr r3,SVR 778a47a12beSStefan Roese blr 779a47a12beSStefan Roese 780a47a12beSStefan Roese .globl wr_tcr 781a47a12beSStefan Roesewr_tcr: 782a47a12beSStefan Roese mtspr TCR,r3 783a47a12beSStefan Roese blr 784a47a12beSStefan Roese 785a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 786a47a12beSStefan Roese/* Function: in8 */ 787a47a12beSStefan Roese/* Description: Input 8 bits */ 788a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 789a47a12beSStefan Roese .globl in8 790a47a12beSStefan Roesein8: 791a47a12beSStefan Roese lbz r3,0x0000(r3) 792a47a12beSStefan Roese blr 793a47a12beSStefan Roese 794a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 795a47a12beSStefan Roese/* Function: out8 */ 796a47a12beSStefan Roese/* Description: Output 8 bits */ 797a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 798a47a12beSStefan Roese .globl out8 799a47a12beSStefan Roeseout8: 800a47a12beSStefan Roese stb r4,0x0000(r3) 801a47a12beSStefan Roese sync 802a47a12beSStefan Roese blr 803a47a12beSStefan Roese 804a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 805a47a12beSStefan Roese/* Function: out16 */ 806a47a12beSStefan Roese/* Description: Output 16 bits */ 807a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 808a47a12beSStefan Roese .globl out16 809a47a12beSStefan Roeseout16: 810a47a12beSStefan Roese sth r4,0x0000(r3) 811a47a12beSStefan Roese sync 812a47a12beSStefan Roese blr 813a47a12beSStefan Roese 814a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 815a47a12beSStefan Roese/* Function: out16r */ 816a47a12beSStefan Roese/* Description: Byte reverse and output 16 bits */ 817a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 818a47a12beSStefan Roese .globl out16r 819a47a12beSStefan Roeseout16r: 820a47a12beSStefan Roese sthbrx r4,r0,r3 821a47a12beSStefan Roese sync 822a47a12beSStefan Roese blr 823a47a12beSStefan Roese 824a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 825a47a12beSStefan Roese/* Function: out32 */ 826a47a12beSStefan Roese/* Description: Output 32 bits */ 827a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 828a47a12beSStefan Roese .globl out32 829a47a12beSStefan Roeseout32: 830a47a12beSStefan Roese stw r4,0x0000(r3) 831a47a12beSStefan Roese sync 832a47a12beSStefan Roese blr 833a47a12beSStefan Roese 834a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 835a47a12beSStefan Roese/* Function: out32r */ 836a47a12beSStefan Roese/* Description: Byte reverse and output 32 bits */ 837a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 838a47a12beSStefan Roese .globl out32r 839a47a12beSStefan Roeseout32r: 840a47a12beSStefan Roese stwbrx r4,r0,r3 841a47a12beSStefan Roese sync 842a47a12beSStefan Roese blr 843a47a12beSStefan Roese 844a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 845a47a12beSStefan Roese/* Function: in16 */ 846a47a12beSStefan Roese/* Description: Input 16 bits */ 847a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 848a47a12beSStefan Roese .globl in16 849a47a12beSStefan Roesein16: 850a47a12beSStefan Roese lhz r3,0x0000(r3) 851a47a12beSStefan Roese blr 852a47a12beSStefan Roese 853a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 854a47a12beSStefan Roese/* Function: in16r */ 855a47a12beSStefan Roese/* Description: Input 16 bits and byte reverse */ 856a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 857a47a12beSStefan Roese .globl in16r 858a47a12beSStefan Roesein16r: 859a47a12beSStefan Roese lhbrx r3,r0,r3 860a47a12beSStefan Roese blr 861a47a12beSStefan Roese 862a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 863a47a12beSStefan Roese/* Function: in32 */ 864a47a12beSStefan Roese/* Description: Input 32 bits */ 865a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 866a47a12beSStefan Roese .globl in32 867a47a12beSStefan Roesein32: 868a47a12beSStefan Roese lwz 3,0x0000(3) 869a47a12beSStefan Roese blr 870a47a12beSStefan Roese 871a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 872a47a12beSStefan Roese/* Function: in32r */ 873a47a12beSStefan Roese/* Description: Input 32 bits and byte reverse */ 874a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 875a47a12beSStefan Roese .globl in32r 876a47a12beSStefan Roesein32r: 877a47a12beSStefan Roese lwbrx r3,r0,r3 878a47a12beSStefan Roese blr 879a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 880a47a12beSStefan Roese 881a47a12beSStefan Roese/*------------------------------------------------------------------------------*/ 882a47a12beSStefan Roese 883a47a12beSStefan Roese/* 884a47a12beSStefan Roese * void write_tlb(mas0, mas1, mas2, mas3, mas7) 885a47a12beSStefan Roese */ 886a47a12beSStefan Roese .globl write_tlb 887a47a12beSStefan Roesewrite_tlb: 888a47a12beSStefan Roese mtspr MAS0,r3 889a47a12beSStefan Roese mtspr MAS1,r4 890a47a12beSStefan Roese mtspr MAS2,r5 891a47a12beSStefan Roese mtspr MAS3,r6 892a47a12beSStefan Roese#ifdef CONFIG_ENABLE_36BIT_PHYS 893a47a12beSStefan Roese mtspr MAS7,r7 894a47a12beSStefan Roese#endif 895a47a12beSStefan Roese li r3,0 896a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 897a47a12beSStefan Roese mtspr MAS8,r3 898a47a12beSStefan Roese#endif 899a47a12beSStefan Roese isync 900a47a12beSStefan Roese tlbwe 901a47a12beSStefan Roese msync 902a47a12beSStefan Roese isync 903a47a12beSStefan Roese blr 904a47a12beSStefan Roese 905a47a12beSStefan Roese/* 906a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 907a47a12beSStefan Roese * 908a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 909a47a12beSStefan Roese * after relocating the monitor code. 910a47a12beSStefan Roese * 911a47a12beSStefan Roese * r3 = dest 912a47a12beSStefan Roese * r4 = src 913a47a12beSStefan Roese * r5 = length in bytes 914a47a12beSStefan Roese * r6 = cachelinesize 915a47a12beSStefan Roese */ 916a47a12beSStefan Roese .globl relocate_code 917a47a12beSStefan Roeserelocate_code: 918a47a12beSStefan Roese mr r1,r3 /* Set new stack pointer */ 919a47a12beSStefan Roese mr r9,r4 /* Save copy of Init Data pointer */ 920a47a12beSStefan Roese mr r10,r5 /* Save copy of Destination Address */ 921a47a12beSStefan Roese 922a47a12beSStefan Roese GET_GOT 923a47a12beSStefan Roese mr r3,r5 /* Destination Address */ 924a47a12beSStefan Roese lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 925a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 926a47a12beSStefan Roese lwz r5,GOT(__init_end) 927a47a12beSStefan Roese sub r5,r5,r4 928a47a12beSStefan Roese li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 929a47a12beSStefan Roese 930a47a12beSStefan Roese /* 931a47a12beSStefan Roese * Fix GOT pointer: 932a47a12beSStefan Roese * 933a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 934a47a12beSStefan Roese * 935a47a12beSStefan Roese * Offset: 936a47a12beSStefan Roese */ 937a47a12beSStefan Roese sub r15,r10,r4 938a47a12beSStefan Roese 939a47a12beSStefan Roese /* First our own GOT */ 940a47a12beSStefan Roese add r12,r12,r15 941a47a12beSStefan Roese /* the the one used by the C code */ 942a47a12beSStefan Roese add r30,r30,r15 943a47a12beSStefan Roese 944a47a12beSStefan Roese /* 945a47a12beSStefan Roese * Now relocate code 946a47a12beSStefan Roese */ 947a47a12beSStefan Roese 948a47a12beSStefan Roese cmplw cr1,r3,r4 949a47a12beSStefan Roese addi r0,r5,3 950a47a12beSStefan Roese srwi. r0,r0,2 951a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 952a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 953a47a12beSStefan Roese mtctr r0 954a47a12beSStefan Roese bge cr1,2f 955a47a12beSStefan Roese 956a47a12beSStefan Roese la r8,-4(r4) 957a47a12beSStefan Roese la r7,-4(r3) 958a47a12beSStefan Roese1: lwzu r0,4(r8) 959a47a12beSStefan Roese stwu r0,4(r7) 960a47a12beSStefan Roese bdnz 1b 961a47a12beSStefan Roese b 4f 962a47a12beSStefan Roese 963a47a12beSStefan Roese2: slwi r0,r0,2 964a47a12beSStefan Roese add r8,r4,r0 965a47a12beSStefan Roese add r7,r3,r0 966a47a12beSStefan Roese3: lwzu r0,-4(r8) 967a47a12beSStefan Roese stwu r0,-4(r7) 968a47a12beSStefan Roese bdnz 3b 969a47a12beSStefan Roese 970a47a12beSStefan Roese/* 971a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 972a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 973a47a12beSStefan Roese */ 974a47a12beSStefan Roese4: cmpwi r6,0 975a47a12beSStefan Roese add r5,r3,r5 976a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 977a47a12beSStefan Roese subi r0,r6,1 978a47a12beSStefan Roese andc r3,r3,r0 979a47a12beSStefan Roese mr r4,r3 980a47a12beSStefan Roese5: dcbst 0,r4 981a47a12beSStefan Roese add r4,r4,r6 982a47a12beSStefan Roese cmplw r4,r5 983a47a12beSStefan Roese blt 5b 984a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 985a47a12beSStefan Roese mr r4,r3 986a47a12beSStefan Roese6: icbi 0,r4 987a47a12beSStefan Roese add r4,r4,r6 988a47a12beSStefan Roese cmplw r4,r5 989a47a12beSStefan Roese blt 6b 990a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 991a47a12beSStefan Roese isync 992a47a12beSStefan Roese 993a47a12beSStefan Roese /* 994a47a12beSStefan Roese * Re-point the IVPR at RAM 995a47a12beSStefan Roese */ 996a47a12beSStefan Roese mtspr IVPR,r10 997a47a12beSStefan Roese 998a47a12beSStefan Roese/* 999a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 1000a47a12beSStefan Roese * initialization, now running from RAM. 1001a47a12beSStefan Roese */ 1002a47a12beSStefan Roese 1003a47a12beSStefan Roese addi r0,r10,in_ram - _start + _START_OFFSET 1004a47a12beSStefan Roese mtlr r0 1005a47a12beSStefan Roese blr /* NEVER RETURNS! */ 1006a47a12beSStefan Roese .globl in_ram 1007a47a12beSStefan Roesein_ram: 1008a47a12beSStefan Roese 1009a47a12beSStefan Roese /* 1010a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 1011a47a12beSStefan Roese * 1012a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 1013a47a12beSStefan Roese * already puts a few entries in the table. 1014a47a12beSStefan Roese */ 1015a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 1016a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 1017a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 1018a47a12beSStefan Roese mtctr r0 1019a47a12beSStefan Roese sub r11,r3,r11 1020a47a12beSStefan Roese addi r3,r3,-4 1021a47a12beSStefan Roese1: lwzu r0,4(r3) 1022a47a12beSStefan Roese cmpwi r0,0 1023a47a12beSStefan Roese beq- 2f 1024a47a12beSStefan Roese add r0,r0,r11 1025a47a12beSStefan Roese stw r0,0(r3) 1026a47a12beSStefan Roese2: bdnz 1b 1027a47a12beSStefan Roese 1028a47a12beSStefan Roese /* 1029a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 1030a47a12beSStefan Roese * in case we need to move ourselves again. 1031a47a12beSStefan Roese */ 1032a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 1033a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 1034a47a12beSStefan Roese cmpwi r0,0 1035a47a12beSStefan Roese mtctr r0 1036a47a12beSStefan Roese addi r3,r3,-4 1037a47a12beSStefan Roese beq 4f 1038a47a12beSStefan Roese3: lwzu r4,4(r3) 1039a47a12beSStefan Roese lwzux r0,r4,r11 1040*d1e0b10aSJoakim Tjernlund cmpwi r0,0 1041a47a12beSStefan Roese add r0,r0,r11 1042a47a12beSStefan Roese stw r10,0(r3) 1043*d1e0b10aSJoakim Tjernlund beq- 5f 1044a47a12beSStefan Roese stw r0,0(r4) 1045*d1e0b10aSJoakim Tjernlund5: bdnz 3b 1046a47a12beSStefan Roese4: 1047a47a12beSStefan Roeseclear_bss: 1048a47a12beSStefan Roese /* 1049a47a12beSStefan Roese * Now clear BSS segment 1050a47a12beSStefan Roese */ 1051a47a12beSStefan Roese lwz r3,GOT(__bss_start) 1052a47a12beSStefan Roese lwz r4,GOT(_end) 1053a47a12beSStefan Roese 1054a47a12beSStefan Roese cmplw 0,r3,r4 1055a47a12beSStefan Roese beq 6f 1056a47a12beSStefan Roese 1057a47a12beSStefan Roese li r0,0 1058a47a12beSStefan Roese5: 1059a47a12beSStefan Roese stw r0,0(r3) 1060a47a12beSStefan Roese addi r3,r3,4 1061a47a12beSStefan Roese cmplw 0,r3,r4 1062a47a12beSStefan Roese bne 5b 1063a47a12beSStefan Roese6: 1064a47a12beSStefan Roese 1065a47a12beSStefan Roese mr r3,r9 /* Init Data pointer */ 1066a47a12beSStefan Roese mr r4,r10 /* Destination Address */ 1067a47a12beSStefan Roese bl board_init_r 1068a47a12beSStefan Roese 1069a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 1070a47a12beSStefan Roese /* 1071a47a12beSStefan Roese * Copy exception vector code to low memory 1072a47a12beSStefan Roese * 1073a47a12beSStefan Roese * r3: dest_addr 1074a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 1075a47a12beSStefan Roese */ 1076a47a12beSStefan Roese .globl trap_init 1077a47a12beSStefan Roesetrap_init: 1078a47a12beSStefan Roese mflr r4 /* save link register */ 1079a47a12beSStefan Roese GET_GOT 1080a47a12beSStefan Roese lwz r7,GOT(_start_of_vectors) 1081a47a12beSStefan Roese lwz r8,GOT(_end_of_vectors) 1082a47a12beSStefan Roese 1083a47a12beSStefan Roese li r9,0x100 /* reset vector always at 0x100 */ 1084a47a12beSStefan Roese 1085a47a12beSStefan Roese cmplw 0,r7,r8 1086a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 1087a47a12beSStefan Roese1: 1088a47a12beSStefan Roese lwz r0,0(r7) 1089a47a12beSStefan Roese stw r0,0(r9) 1090a47a12beSStefan Roese addi r7,r7,4 1091a47a12beSStefan Roese addi r9,r9,4 1092a47a12beSStefan Roese cmplw 0,r7,r8 1093a47a12beSStefan Roese bne 1b 1094a47a12beSStefan Roese 1095a47a12beSStefan Roese /* 1096a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 1097a47a12beSStefan Roese */ 1098a47a12beSStefan Roese li r7,.L_CriticalInput - _start + _START_OFFSET 1099a47a12beSStefan Roese bl trap_reloc 1100a47a12beSStefan Roese li r7,.L_MachineCheck - _start + _START_OFFSET 1101a47a12beSStefan Roese bl trap_reloc 1102a47a12beSStefan Roese li r7,.L_DataStorage - _start + _START_OFFSET 1103a47a12beSStefan Roese bl trap_reloc 1104a47a12beSStefan Roese li r7,.L_InstStorage - _start + _START_OFFSET 1105a47a12beSStefan Roese bl trap_reloc 1106a47a12beSStefan Roese li r7,.L_ExtInterrupt - _start + _START_OFFSET 1107a47a12beSStefan Roese bl trap_reloc 1108a47a12beSStefan Roese li r7,.L_Alignment - _start + _START_OFFSET 1109a47a12beSStefan Roese bl trap_reloc 1110a47a12beSStefan Roese li r7,.L_ProgramCheck - _start + _START_OFFSET 1111a47a12beSStefan Roese bl trap_reloc 1112a47a12beSStefan Roese li r7,.L_FPUnavailable - _start + _START_OFFSET 1113a47a12beSStefan Roese bl trap_reloc 1114a47a12beSStefan Roese li r7,.L_Decrementer - _start + _START_OFFSET 1115a47a12beSStefan Roese bl trap_reloc 1116a47a12beSStefan Roese li r7,.L_IntervalTimer - _start + _START_OFFSET 1117a47a12beSStefan Roese li r8,_end_of_vectors - _start + _START_OFFSET 1118a47a12beSStefan Roese2: 1119a47a12beSStefan Roese bl trap_reloc 1120a47a12beSStefan Roese addi r7,r7,0x100 /* next exception vector */ 1121a47a12beSStefan Roese cmplw 0,r7,r8 1122a47a12beSStefan Roese blt 2b 1123a47a12beSStefan Roese 1124a47a12beSStefan Roese lis r7,0x0 1125a47a12beSStefan Roese mtspr IVPR,r7 1126a47a12beSStefan Roese 1127a47a12beSStefan Roese mtlr r4 /* restore link register */ 1128a47a12beSStefan Roese blr 1129a47a12beSStefan Roese 1130a47a12beSStefan Roese.globl unlock_ram_in_cache 1131a47a12beSStefan Roeseunlock_ram_in_cache: 1132a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 1133a47a12beSStefan Roese lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1134a47a12beSStefan Roese ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1135a47a12beSStefan Roese mfspr r4,L1CFG0 1136a47a12beSStefan Roese andi. r4,r4,0x1ff 1137a47a12beSStefan Roese slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1138a47a12beSStefan Roese mtctr r4 1139a47a12beSStefan Roese1: dcbi r0,r3 1140a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1141a47a12beSStefan Roese bdnz 1b 1142a47a12beSStefan Roese sync 1143a47a12beSStefan Roese 1144a47a12beSStefan Roese /* Invalidate the TLB entries for the cache */ 1145a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1146a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1147a47a12beSStefan Roese tlbivax 0,r3 1148a47a12beSStefan Roese addi r3,r3,0x1000 1149a47a12beSStefan Roese tlbivax 0,r3 1150a47a12beSStefan Roese addi r3,r3,0x1000 1151a47a12beSStefan Roese tlbivax 0,r3 1152a47a12beSStefan Roese addi r3,r3,0x1000 1153a47a12beSStefan Roese tlbivax 0,r3 1154a47a12beSStefan Roese isync 1155a47a12beSStefan Roese blr 1156a47a12beSStefan Roese 1157a47a12beSStefan Roese.globl flush_dcache 1158a47a12beSStefan Roeseflush_dcache: 1159a47a12beSStefan Roese mfspr r3,SPRN_L1CFG0 1160a47a12beSStefan Roese 1161a47a12beSStefan Roese rlwinm r5,r3,9,3 /* Extract cache block size */ 1162a47a12beSStefan Roese twlgti r5,1 /* Only 32 and 64 byte cache blocks 1163a47a12beSStefan Roese * are currently defined. 1164a47a12beSStefan Roese */ 1165a47a12beSStefan Roese li r4,32 1166a47a12beSStefan Roese subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1167a47a12beSStefan Roese * log2(number of ways) 1168a47a12beSStefan Roese */ 1169a47a12beSStefan Roese slw r5,r4,r5 /* r5 = cache block size */ 1170a47a12beSStefan Roese 1171a47a12beSStefan Roese rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1172a47a12beSStefan Roese mulli r7,r7,13 /* An 8-way cache will require 13 1173a47a12beSStefan Roese * loads per set. 1174a47a12beSStefan Roese */ 1175a47a12beSStefan Roese slw r7,r7,r6 1176a47a12beSStefan Roese 1177a47a12beSStefan Roese /* save off HID0 and set DCFA */ 1178a47a12beSStefan Roese mfspr r8,SPRN_HID0 1179a47a12beSStefan Roese ori r9,r8,HID0_DCFA@l 1180a47a12beSStefan Roese mtspr SPRN_HID0,r9 1181a47a12beSStefan Roese isync 1182a47a12beSStefan Roese 1183a47a12beSStefan Roese lis r4,0 1184a47a12beSStefan Roese mtctr r7 1185a47a12beSStefan Roese 1186a47a12beSStefan Roese1: lwz r3,0(r4) /* Load... */ 1187a47a12beSStefan Roese add r4,r4,r5 1188a47a12beSStefan Roese bdnz 1b 1189a47a12beSStefan Roese 1190a47a12beSStefan Roese msync 1191a47a12beSStefan Roese lis r4,0 1192a47a12beSStefan Roese mtctr r7 1193a47a12beSStefan Roese 1194a47a12beSStefan Roese1: dcbf 0,r4 /* ...and flush. */ 1195a47a12beSStefan Roese add r4,r4,r5 1196a47a12beSStefan Roese bdnz 1b 1197a47a12beSStefan Roese 1198a47a12beSStefan Roese /* restore HID0 */ 1199a47a12beSStefan Roese mtspr SPRN_HID0,r8 1200a47a12beSStefan Roese isync 1201a47a12beSStefan Roese 1202a47a12beSStefan Roese blr 1203a47a12beSStefan Roese 1204a47a12beSStefan Roese.globl setup_ivors 1205a47a12beSStefan Roesesetup_ivors: 1206a47a12beSStefan Roese 1207a47a12beSStefan Roese#include "fixed_ivor.S" 1208a47a12beSStefan Roese blr 1209a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1210