1a47a12beSStefan Roese/* 245a68135SKumar Gala * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. 3a47a12beSStefan Roese * Copyright (C) 2003 Motorola,Inc. 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards 25a47a12beSStefan Roese * 26a47a12beSStefan Roese * The processor starts at 0xfffffffc and the code is first executed in the 27a47a12beSStefan Roese * last 4K page(0xfffff000-0xffffffff) in flash/rom. 28a47a12beSStefan Roese * 29a47a12beSStefan Roese */ 30a47a12beSStefan Roese 3125ddd1fbSWolfgang Denk#include <asm-offsets.h> 32a47a12beSStefan Roese#include <config.h> 33a47a12beSStefan Roese#include <mpc85xx.h> 34a47a12beSStefan Roese#include <version.h> 35a47a12beSStefan Roese 36a47a12beSStefan Roese#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 37a47a12beSStefan Roese 38a47a12beSStefan Roese#include <ppc_asm.tmpl> 39a47a12beSStefan Roese#include <ppc_defs.h> 40a47a12beSStefan Roese 41a47a12beSStefan Roese#include <asm/cache.h> 42a47a12beSStefan Roese#include <asm/mmu.h> 43a47a12beSStefan Roese 44a47a12beSStefan Roese#undef MSR_KERNEL 45a47a12beSStefan Roese#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 46a47a12beSStefan Roese 47a47a12beSStefan Roese/* 48a47a12beSStefan Roese * Set up GOT: Global Offset Table 49a47a12beSStefan Roese * 50a47a12beSStefan Roese * Use r12 to access the GOT 51a47a12beSStefan Roese */ 52a47a12beSStefan Roese START_GOT 53a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 54a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 55a47a12beSStefan Roese 56a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 57a47a12beSStefan Roese GOT_ENTRY(_start) 58a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 59a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 60a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 61a47a12beSStefan Roese#endif 62a47a12beSStefan Roese 63a47a12beSStefan Roese GOT_ENTRY(__init_end) 6444c6e659SPo-Yu Chuang GOT_ENTRY(__bss_end__) 65a47a12beSStefan Roese GOT_ENTRY(__bss_start) 66a47a12beSStefan Roese END_GOT 67a47a12beSStefan Roese 68a47a12beSStefan Roese/* 69a47a12beSStefan Roese * e500 Startup -- after reset only the last 4KB of the effective 70a47a12beSStefan Roese * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg 71a47a12beSStefan Roese * section is located at THIS LAST page and basically does three 72a47a12beSStefan Roese * things: clear some registers, set up exception tables and 73a47a12beSStefan Roese * add more TLB entries for 'larger spaces'(e.g. the boot rom) to 74a47a12beSStefan Roese * continue the boot procedure. 75a47a12beSStefan Roese 76a47a12beSStefan Roese * Once the boot rom is mapped by TLB entries we can proceed 77a47a12beSStefan Roese * with normal startup. 78a47a12beSStefan Roese * 79a47a12beSStefan Roese */ 80a47a12beSStefan Roese 81a47a12beSStefan Roese .section .bootpg,"ax" 82a47a12beSStefan Roese .globl _start_e500 83a47a12beSStefan Roese 84a47a12beSStefan Roese_start_e500: 85a47a12beSStefan Roese 867065b7d4SRuchika Gupta#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) 877065b7d4SRuchika Gupta /* ISBC uses L2 as stack. 887065b7d4SRuchika Gupta * Disable L2 cache here so that u-boot can enable it later 897065b7d4SRuchika Gupta * as part of it's normal flow 907065b7d4SRuchika Gupta */ 917065b7d4SRuchika Gupta 927065b7d4SRuchika Gupta /* Check if L2 is enabled */ 937065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 947065b7d4SRuchika Gupta lis r2, L2CSR0_L2E@h 957065b7d4SRuchika Gupta ori r2, r2, L2CSR0_L2E@l 967065b7d4SRuchika Gupta and. r4, r3, r2 977065b7d4SRuchika Gupta beq l2_disabled 987065b7d4SRuchika Gupta 997065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1007065b7d4SRuchika Gupta /* Flush L2 cache */ 1017065b7d4SRuchika Gupta lis r2,(L2CSR0_L2FL)@h 1027065b7d4SRuchika Gupta ori r2, r2, (L2CSR0_L2FL)@l 1037065b7d4SRuchika Gupta or r3, r2, r3 1047065b7d4SRuchika Gupta sync 1057065b7d4SRuchika Gupta isync 1067065b7d4SRuchika Gupta mtspr SPRN_L2CSR0,r3 1077065b7d4SRuchika Gupta isync 1087065b7d4SRuchika Gupta1: 1097065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1107065b7d4SRuchika Gupta and. r1, r3, r2 1117065b7d4SRuchika Gupta bne 1b 1127065b7d4SRuchika Gupta 1137065b7d4SRuchika Gupta mfspr r3, SPRN_L2CSR0 1147065b7d4SRuchika Gupta lis r2, L2CSR0_L2E@h 1157065b7d4SRuchika Gupta ori r2, r2, L2CSR0_L2E@l 1167065b7d4SRuchika Gupta andc r4, r3, r2 1177065b7d4SRuchika Gupta sync 1187065b7d4SRuchika Gupta isync 1197065b7d4SRuchika Gupta mtspr SPRN_L2CSR0,r4 1207065b7d4SRuchika Gupta isync 1217065b7d4SRuchika Gupta 1227065b7d4SRuchika Guptal2_disabled: 1237065b7d4SRuchika Gupta#endif 1247065b7d4SRuchika Gupta 125a47a12beSStefan Roese/* clear registers/arrays not reset by hardware */ 126a47a12beSStefan Roese 127a47a12beSStefan Roese /* L1 */ 128a47a12beSStefan Roese li r0,2 129a47a12beSStefan Roese mtspr L1CSR0,r0 /* invalidate d-cache */ 130a47a12beSStefan Roese mtspr L1CSR1,r0 /* invalidate i-cache */ 131a47a12beSStefan Roese 132a47a12beSStefan Roese mfspr r1,DBSR 133a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all valid bits */ 134a47a12beSStefan Roese 135a47a12beSStefan Roese /* 136a47a12beSStefan Roese * Enable L1 Caches early 137a47a12beSStefan Roese * 138a47a12beSStefan Roese */ 139a47a12beSStefan Roese 140a47a12beSStefan Roese#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) 141a47a12beSStefan Roese /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ 142a47a12beSStefan Roese li r2,(32 + 0) 143a47a12beSStefan Roese mtspr L1CSR2,r2 144a47a12beSStefan Roese#endif 145a47a12beSStefan Roese 146a47a12beSStefan Roese /* Enable/invalidate the I-Cache */ 147a47a12beSStefan Roese lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h 148a47a12beSStefan Roese ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l 149a47a12beSStefan Roese mtspr SPRN_L1CSR1,r2 150a47a12beSStefan Roese1: 151a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 152a47a12beSStefan Roese and. r1,r3,r2 153a47a12beSStefan Roese bne 1b 154a47a12beSStefan Roese 155a47a12beSStefan Roese lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h 156a47a12beSStefan Roese ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l 157a47a12beSStefan Roese mtspr SPRN_L1CSR1,r3 158a47a12beSStefan Roese isync 159a47a12beSStefan Roese2: 160a47a12beSStefan Roese mfspr r3,SPRN_L1CSR1 161a47a12beSStefan Roese andi. r1,r3,L1CSR1_ICE@l 162a47a12beSStefan Roese beq 2b 163a47a12beSStefan Roese 164a47a12beSStefan Roese /* Enable/invalidate the D-Cache */ 165a47a12beSStefan Roese lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h 166a47a12beSStefan Roese ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l 167a47a12beSStefan Roese mtspr SPRN_L1CSR0,r2 168a47a12beSStefan Roese1: 169a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 170a47a12beSStefan Roese and. r1,r3,r2 171a47a12beSStefan Roese bne 1b 172a47a12beSStefan Roese 173a47a12beSStefan Roese lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h 174a47a12beSStefan Roese ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l 175a47a12beSStefan Roese mtspr SPRN_L1CSR0,r3 176a47a12beSStefan Roese isync 177a47a12beSStefan Roese2: 178a47a12beSStefan Roese mfspr r3,SPRN_L1CSR0 179a47a12beSStefan Roese andi. r1,r3,L1CSR0_DCE@l 180a47a12beSStefan Roese beq 2b 181a47a12beSStefan Roese 182a47a12beSStefan Roese /* Setup interrupt vectors */ 1830635b09cSHaiying Wang lis r1,CONFIG_SYS_MONITOR_BASE@h 184a47a12beSStefan Roese mtspr IVPR,r1 185a47a12beSStefan Roese 186a47a12beSStefan Roese li r1,0x0100 187a47a12beSStefan Roese mtspr IVOR0,r1 /* 0: Critical input */ 188a47a12beSStefan Roese li r1,0x0200 189a47a12beSStefan Roese mtspr IVOR1,r1 /* 1: Machine check */ 190a47a12beSStefan Roese li r1,0x0300 191a47a12beSStefan Roese mtspr IVOR2,r1 /* 2: Data storage */ 192a47a12beSStefan Roese li r1,0x0400 193a47a12beSStefan Roese mtspr IVOR3,r1 /* 3: Instruction storage */ 194a47a12beSStefan Roese li r1,0x0500 195a47a12beSStefan Roese mtspr IVOR4,r1 /* 4: External interrupt */ 196a47a12beSStefan Roese li r1,0x0600 197a47a12beSStefan Roese mtspr IVOR5,r1 /* 5: Alignment */ 198a47a12beSStefan Roese li r1,0x0700 199a47a12beSStefan Roese mtspr IVOR6,r1 /* 6: Program check */ 200a47a12beSStefan Roese li r1,0x0800 201a47a12beSStefan Roese mtspr IVOR7,r1 /* 7: floating point unavailable */ 202a47a12beSStefan Roese li r1,0x0900 203a47a12beSStefan Roese mtspr IVOR8,r1 /* 8: System call */ 204a47a12beSStefan Roese /* 9: Auxiliary processor unavailable(unsupported) */ 205a47a12beSStefan Roese li r1,0x0a00 206a47a12beSStefan Roese mtspr IVOR10,r1 /* 10: Decrementer */ 207a47a12beSStefan Roese li r1,0x0b00 208a47a12beSStefan Roese mtspr IVOR11,r1 /* 11: Interval timer */ 209a47a12beSStefan Roese li r1,0x0c00 210a47a12beSStefan Roese mtspr IVOR12,r1 /* 12: Watchdog timer */ 211a47a12beSStefan Roese li r1,0x0d00 212a47a12beSStefan Roese mtspr IVOR13,r1 /* 13: Data TLB error */ 213a47a12beSStefan Roese li r1,0x0e00 214a47a12beSStefan Roese mtspr IVOR14,r1 /* 14: Instruction TLB error */ 215a47a12beSStefan Roese li r1,0x0f00 216a47a12beSStefan Roese mtspr IVOR15,r1 /* 15: Debug */ 217a47a12beSStefan Roese 218a47a12beSStefan Roese /* Clear and set up some registers. */ 219a47a12beSStefan Roese li r0,0x0000 220a47a12beSStefan Roese lis r1,0xffff 221a47a12beSStefan Roese mtspr DEC,r0 /* prevent dec exceptions */ 222a47a12beSStefan Roese mttbl r0 /* prevent fit & wdt exceptions */ 223a47a12beSStefan Roese mttbu r0 224a47a12beSStefan Roese mtspr TSR,r1 /* clear all timer exception status */ 225a47a12beSStefan Roese mtspr TCR,r0 /* disable all */ 226a47a12beSStefan Roese mtspr ESR,r0 /* clear exception syndrome register */ 227a47a12beSStefan Roese mtspr MCSR,r0 /* machine check syndrome register */ 228a47a12beSStefan Roese mtxer r0 /* clear integer exception register */ 229a47a12beSStefan Roese 230a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 231a47a12beSStefan Roese mtspr MAS8,r0 /* make sure MAS8 is clear */ 232a47a12beSStefan Roese#endif 233a47a12beSStefan Roese 234a47a12beSStefan Roese /* Enable Time Base and Select Time Base Clock */ 235a47a12beSStefan Roese lis r0,HID0_EMCP@h /* Enable machine check */ 236a47a12beSStefan Roese#if defined(CONFIG_ENABLE_36BIT_PHYS) 237a47a12beSStefan Roese ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ 238a47a12beSStefan Roese#endif 239a47a12beSStefan Roese#ifndef CONFIG_E500MC 240a47a12beSStefan Roese ori r0,r0,HID0_TBEN@l /* Enable Timebase */ 241a47a12beSStefan Roese#endif 242a47a12beSStefan Roese mtspr HID0,r0 243a47a12beSStefan Roese 244a47a12beSStefan Roese#ifndef CONFIG_E500MC 245a47a12beSStefan Roese li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ 246a47a12beSStefan Roese mfspr r3,PVR 247a47a12beSStefan Roese andi. r3,r3, 0xff 248a47a12beSStefan Roese cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ 249a47a12beSStefan Roese blt 1f 250a47a12beSStefan Roese /* Set MBDD bit also */ 251a47a12beSStefan Roese ori r0, r0, HID1_MBDD@l 252a47a12beSStefan Roese1: 253a47a12beSStefan Roese mtspr HID1,r0 254a47a12beSStefan Roese#endif 255a47a12beSStefan Roese 256a47a12beSStefan Roese /* Enable Branch Prediction */ 257a47a12beSStefan Roese#if defined(CONFIG_BTB) 258a47a12beSStefan Roese lis r0,BUCSR_ENABLE@h 259a47a12beSStefan Roese ori r0,r0,BUCSR_ENABLE@l 260a47a12beSStefan Roese mtspr SPRN_BUCSR,r0 261a47a12beSStefan Roese#endif 262a47a12beSStefan Roese 263a47a12beSStefan Roese#if defined(CONFIG_SYS_INIT_DBCR) 264a47a12beSStefan Roese lis r1,0xffff 265a47a12beSStefan Roese ori r1,r1,0xffff 266a47a12beSStefan Roese mtspr DBSR,r1 /* Clear all status bits */ 267a47a12beSStefan Roese lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ 268a47a12beSStefan Roese ori r0,r0,CONFIG_SYS_INIT_DBCR@l 269a47a12beSStefan Roese mtspr DBCR0,r0 270a47a12beSStefan Roese#endif 271a47a12beSStefan Roese 272a47a12beSStefan Roese#ifdef CONFIG_MPC8569 273a47a12beSStefan Roese#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) 274a47a12beSStefan Roese#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) 275a47a12beSStefan Roese 276a47a12beSStefan Roese /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to 277a47a12beSStefan Roese * use address space which is more than 12bits, and it must be done in 278a47a12beSStefan Roese * the 4K boot page. So we set this bit here. 279a47a12beSStefan Roese */ 280a47a12beSStefan Roese 281a47a12beSStefan Roese /* create a temp mapping TLB0[0] for LBCR */ 282a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h 283a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l 284a47a12beSStefan Roese 285a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 286a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 287a47a12beSStefan Roese 288a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h 289a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l 290a47a12beSStefan Roese 291a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 292a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@h 293a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0, 294a47a12beSStefan Roese (MAS3_SX|MAS3_SW|MAS3_SR))@l 295a47a12beSStefan Roese 296a47a12beSStefan Roese mtspr MAS0,r6 297a47a12beSStefan Roese mtspr MAS1,r7 298a47a12beSStefan Roese mtspr MAS2,r8 299a47a12beSStefan Roese mtspr MAS3,r9 300a47a12beSStefan Roese isync 301a47a12beSStefan Roese msync 302a47a12beSStefan Roese tlbwe 303a47a12beSStefan Roese 304a47a12beSStefan Roese /* Set LBCR register */ 305a47a12beSStefan Roese lis r4,CONFIG_SYS_LBCR_ADDR@h 306a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBCR_ADDR@l 307a47a12beSStefan Roese 308a47a12beSStefan Roese lis r5,CONFIG_SYS_LBC_LBCR@h 309a47a12beSStefan Roese ori r5,r5,CONFIG_SYS_LBC_LBCR@l 310a47a12beSStefan Roese stw r5,0(r4) 311a47a12beSStefan Roese isync 312a47a12beSStefan Roese 313a47a12beSStefan Roese /* invalidate this temp TLB */ 314a47a12beSStefan Roese lis r4,CONFIG_SYS_LBC_ADDR@h 315a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_LBC_ADDR@l 316a47a12beSStefan Roese tlbivax 0,r4 317a47a12beSStefan Roese isync 318a47a12beSStefan Roese 319a47a12beSStefan Roese#endif /* CONFIG_MPC8569 */ 320a47a12beSStefan Roese 3216ca88b09STimur Tabi/* 322*72243c01STimur Tabi * Search for the TLB that covers the code we're executing, and shrink it 323*72243c01STimur Tabi * so that it covers only this 4K page. That will ensure that any other 324*72243c01STimur Tabi * TLB we create won't interfere with it. We assume that the TLB exists, 325*72243c01STimur Tabi * which is why we don't check the Valid bit of MAS1. 326*72243c01STimur Tabi * 327*72243c01STimur Tabi * This is necessary, for example, when booting from the on-chip ROM, 328*72243c01STimur Tabi * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. 329*72243c01STimur Tabi * If we don't shrink this TLB now, then we'll accidentally delete it 330*72243c01STimur Tabi * in "purge_old_ccsr_tlb" below. 331*72243c01STimur Tabi */ 332*72243c01STimur Tabi bl nexti /* Find our address */ 333*72243c01STimur Tabinexti: mflr r1 /* R1 = our PC */ 334*72243c01STimur Tabi li r2, 0 335*72243c01STimur Tabi mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ 336*72243c01STimur Tabi isync 337*72243c01STimur Tabi msync 338*72243c01STimur Tabi tlbsx 0, r1 /* This must succeed */ 339*72243c01STimur Tabi 340*72243c01STimur Tabi /* Set the size of the TLB to 4KB */ 341*72243c01STimur Tabi mfspr r3, MAS1 342*72243c01STimur Tabi li r2, 0xF00 343*72243c01STimur Tabi andc r3, r3, r2 /* Clear the TSIZE bits */ 344*72243c01STimur Tabi ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l 345*72243c01STimur Tabi mtspr MAS1, r3 346*72243c01STimur Tabi 347*72243c01STimur Tabi /* 348*72243c01STimur Tabi * Set the base address of the TLB to our PC. We assume that 349*72243c01STimur Tabi * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. 350*72243c01STimur Tabi */ 351*72243c01STimur Tabi lis r3, MAS2_EPN@h 352*72243c01STimur Tabi ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ 353*72243c01STimur Tabi 354*72243c01STimur Tabi and r1, r1, r3 /* Our PC, rounded down to the nearest page */ 355*72243c01STimur Tabi 356*72243c01STimur Tabi mfspr r2, MAS2 357*72243c01STimur Tabi andc r2, r2, r3 358*72243c01STimur Tabi or r2, r2, r1 359*72243c01STimur Tabi mtspr MAS2, r2 /* Set the EPN to our PC base address */ 360*72243c01STimur Tabi 361*72243c01STimur Tabi mfspr r2, MAS3 362*72243c01STimur Tabi andc r2, r2, r3 363*72243c01STimur Tabi or r2, r2, r1 364*72243c01STimur Tabi mtspr MAS3, r2 /* Set the RPN to our PC base address */ 365*72243c01STimur Tabi 366*72243c01STimur Tabi isync 367*72243c01STimur Tabi msync 368*72243c01STimur Tabi tlbwe 369*72243c01STimur Tabi 370*72243c01STimur Tabi/* 3716ca88b09STimur Tabi * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default 3726ca88b09STimur Tabi * location is not where we want it. This typically happens on a 36-bit 3736ca88b09STimur Tabi * system, where we want to move CCSR to near the top of 36-bit address space. 3746ca88b09STimur Tabi * 3756ca88b09STimur Tabi * To move CCSR, we create two temporary TLBs, one for the old location, and 3766ca88b09STimur Tabi * another for the new location. On CoreNet systems, we also need to create 3776ca88b09STimur Tabi * a special, temporary LAW. 3786ca88b09STimur Tabi * 3796ca88b09STimur Tabi * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for 3806ca88b09STimur Tabi * long-term TLBs, so we use TLB0 here. 3816ca88b09STimur Tabi */ 3826ca88b09STimur Tabi#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) 3836ca88b09STimur Tabi 3846ca88b09STimur Tabi#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) 3856ca88b09STimur Tabi#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." 3866ca88b09STimur Tabi#endif 3876ca88b09STimur Tabi 3886ca88b09STimur Tabipurge_old_ccsr_tlb: 3896ca88b09STimur Tabi lis r8, CONFIG_SYS_CCSRBAR@h 3906ca88b09STimur Tabi ori r8, r8, CONFIG_SYS_CCSRBAR@l 3916ca88b09STimur Tabi lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h 3926ca88b09STimur Tabi ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l 3936ca88b09STimur Tabi 3946ca88b09STimur Tabi /* 3956ca88b09STimur Tabi * In a multi-stage boot (e.g. NAND boot), a previous stage may have 3966ca88b09STimur Tabi * created a TLB for CCSR, which will interfere with our relocation 3976ca88b09STimur Tabi * code. Since we're going to create a new TLB for CCSR anyway, 3986ca88b09STimur Tabi * it should be safe to delete this old TLB here. We have to search 3996ca88b09STimur Tabi * for it, though. 4006ca88b09STimur Tabi */ 4016ca88b09STimur Tabi 4026ca88b09STimur Tabi li r1, 0 4036ca88b09STimur Tabi mtspr MAS6, r1 /* Search the current address space and PID */ 404452ad61cSTimur Tabi isync 405452ad61cSTimur Tabi msync 4066ca88b09STimur Tabi tlbsx 0, r8 4076ca88b09STimur Tabi mfspr r1, MAS1 4086ca88b09STimur Tabi andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ 4096ca88b09STimur Tabi beq 1f /* Skip if no TLB found */ 4106ca88b09STimur Tabi 4116ca88b09STimur Tabi rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ 4126ca88b09STimur Tabi mtspr MAS1, r1 413452ad61cSTimur Tabi isync 414452ad61cSTimur Tabi msync 4156ca88b09STimur Tabi tlbwe 4166ca88b09STimur Tabi1: 4176ca88b09STimur Tabi 4186ca88b09STimur Tabicreate_ccsr_new_tlb: 4196ca88b09STimur Tabi /* 4206ca88b09STimur Tabi * Create a TLB for the new location of CCSR. Register R8 is reserved 4216ca88b09STimur Tabi * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). 4226ca88b09STimur Tabi */ 4236ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 4246ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 4256ca88b09STimur Tabi lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h 4266ca88b09STimur Tabi ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l 4276ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 4286ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 4296ca88b09STimur Tabi lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h 4306ca88b09STimur Tabi ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l 4316ca88b09STimur Tabi lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 4326ca88b09STimur Tabi ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 4336ca88b09STimur Tabi mtspr MAS0, r0 4346ca88b09STimur Tabi mtspr MAS1, r1 4356ca88b09STimur Tabi mtspr MAS2, r2 4366ca88b09STimur Tabi mtspr MAS3, r3 4376ca88b09STimur Tabi mtspr MAS7, r7 4386ca88b09STimur Tabi isync 4396ca88b09STimur Tabi msync 4406ca88b09STimur Tabi tlbwe 4416ca88b09STimur Tabi 4426ca88b09STimur Tabi /* 443c2efa0aaSTimur Tabi * Create a TLB for the current location of CCSR. Register R9 is reserved 4446ca88b09STimur Tabi * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). 4456ca88b09STimur Tabi */ 4466ca88b09STimur Tabicreate_ccsr_old_tlb: 4476ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 4486ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 4496ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 4506ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 4516ca88b09STimur Tabi lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h 4526ca88b09STimur Tabi ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l 4536ca88b09STimur Tabi li r7, 0 /* The default CCSR address is always a 32-bit number */ 4546ca88b09STimur Tabi mtspr MAS0, r0 4556ca88b09STimur Tabi /* MAS1 is the same as above */ 4566ca88b09STimur Tabi mtspr MAS2, r2 4576ca88b09STimur Tabi mtspr MAS3, r3 4586ca88b09STimur Tabi mtspr MAS7, r7 4596ca88b09STimur Tabi isync 4606ca88b09STimur Tabi msync 4616ca88b09STimur Tabi tlbwe 4626ca88b09STimur Tabi 46319e43841STimur Tabi /* 46419e43841STimur Tabi * We have a TLB for what we think is the current (old) CCSR. Let's 46519e43841STimur Tabi * verify that, otherwise we won't be able to move it. 46619e43841STimur Tabi * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only 46719e43841STimur Tabi * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. 46819e43841STimur Tabi */ 46919e43841STimur Tabiverify_old_ccsr: 47019e43841STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h 47119e43841STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l 47219e43841STimur Tabi#ifdef CONFIG_FSL_CORENET 47319e43841STimur Tabi lwz r1, 4(r9) /* CCSRBARL */ 47419e43841STimur Tabi#else 47519e43841STimur Tabi lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ 47619e43841STimur Tabi slwi r1, r1, 12 47719e43841STimur Tabi#endif 47819e43841STimur Tabi 47919e43841STimur Tabi cmpl 0, r0, r1 48019e43841STimur Tabi 48119e43841STimur Tabi /* 48219e43841STimur Tabi * If the value we read from CCSRBARL is not what we expect, then 48319e43841STimur Tabi * enter an infinite loop. This will at least allow a debugger to 48419e43841STimur Tabi * halt execution and examine TLBs, etc. There's no point in going 48519e43841STimur Tabi * on. 48619e43841STimur Tabi */ 48719e43841STimur Tabiinfinite_debug_loop: 48819e43841STimur Tabi bne infinite_debug_loop 48919e43841STimur Tabi 4906ca88b09STimur Tabi#ifdef CONFIG_FSL_CORENET 4916ca88b09STimur Tabi 4926ca88b09STimur Tabi#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) 4936ca88b09STimur Tabi#define LAW_EN 0x80000000 4946ca88b09STimur Tabi#define LAW_SIZE_4K 0xb 4956ca88b09STimur Tabi#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) 4966ca88b09STimur Tabi#define CCSRAR_C 0x80000000 /* Commit */ 4976ca88b09STimur Tabi 4986ca88b09STimur Tabicreate_temp_law: 4996ca88b09STimur Tabi /* 5006ca88b09STimur Tabi * On CoreNet systems, we create the temporary LAW using a special LAW 5016ca88b09STimur Tabi * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. 5026ca88b09STimur Tabi */ 5036ca88b09STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 5046ca88b09STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 5056ca88b09STimur Tabi lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 5066ca88b09STimur Tabi ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 5076ca88b09STimur Tabi lis r2, CCSRBAR_LAWAR@h 5086ca88b09STimur Tabi ori r2, r2, CCSRBAR_LAWAR@l 5096ca88b09STimur Tabi 5106ca88b09STimur Tabi stw r0, 0xc00(r9) /* LAWBARH0 */ 5116ca88b09STimur Tabi stw r1, 0xc04(r9) /* LAWBARL0 */ 5126ca88b09STimur Tabi sync 5136ca88b09STimur Tabi stw r2, 0xc08(r9) /* LAWAR0 */ 5146ca88b09STimur Tabi 5156ca88b09STimur Tabi /* 5166ca88b09STimur Tabi * Read back from LAWAR to ensure the update is complete. e500mc 5176ca88b09STimur Tabi * cores also require an isync. 5186ca88b09STimur Tabi */ 5196ca88b09STimur Tabi lwz r0, 0xc08(r9) /* LAWAR0 */ 5206ca88b09STimur Tabi isync 5216ca88b09STimur Tabi 5226ca88b09STimur Tabi /* 5236ca88b09STimur Tabi * Read the current CCSRBARH and CCSRBARL using load word instructions. 5246ca88b09STimur Tabi * Follow this with an isync instruction. This forces any outstanding 5256ca88b09STimur Tabi * accesses to configuration space to completion. 5266ca88b09STimur Tabi */ 5276ca88b09STimur Tabiread_old_ccsrbar: 5286ca88b09STimur Tabi lwz r0, 0(r9) /* CCSRBARH */ 529c2efa0aaSTimur Tabi lwz r0, 4(r9) /* CCSRBARL */ 5306ca88b09STimur Tabi isync 5316ca88b09STimur Tabi 5326ca88b09STimur Tabi /* 5336ca88b09STimur Tabi * Write the new values for CCSRBARH and CCSRBARL to their old 5346ca88b09STimur Tabi * locations. The CCSRBARH has a shadow register. When the CCSRBARH 5356ca88b09STimur Tabi * has a new value written it loads a CCSRBARH shadow register. When 5366ca88b09STimur Tabi * the CCSRBARL is written, the CCSRBARH shadow register contents 5376ca88b09STimur Tabi * along with the CCSRBARL value are loaded into the CCSRBARH and 5386ca88b09STimur Tabi * CCSRBARL registers, respectively. Follow this with a sync 5396ca88b09STimur Tabi * instruction. 5406ca88b09STimur Tabi */ 5416ca88b09STimur Tabiwrite_new_ccsrbar: 5426ca88b09STimur Tabi lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h 5436ca88b09STimur Tabi ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 5446ca88b09STimur Tabi lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 5456ca88b09STimur Tabi ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 5466ca88b09STimur Tabi lis r2, CCSRAR_C@h 5476ca88b09STimur Tabi ori r2, r2, CCSRAR_C@l 5486ca88b09STimur Tabi 5496ca88b09STimur Tabi stw r0, 0(r9) /* Write to CCSRBARH */ 5506ca88b09STimur Tabi sync /* Make sure we write to CCSRBARH first */ 5516ca88b09STimur Tabi stw r1, 4(r9) /* Write to CCSRBARL */ 5526ca88b09STimur Tabi sync 5536ca88b09STimur Tabi 5546ca88b09STimur Tabi /* 5556ca88b09STimur Tabi * Write a 1 to the commit bit (C) of CCSRAR at the old location. 5566ca88b09STimur Tabi * Follow this with a sync instruction. 5576ca88b09STimur Tabi */ 5586ca88b09STimur Tabi stw r2, 8(r9) 5596ca88b09STimur Tabi sync 5606ca88b09STimur Tabi 5616ca88b09STimur Tabi /* Delete the temporary LAW */ 5626ca88b09STimur Tabidelete_temp_law: 5636ca88b09STimur Tabi li r1, 0 5646ca88b09STimur Tabi stw r1, 0xc08(r8) 5656ca88b09STimur Tabi sync 5666ca88b09STimur Tabi stw r1, 0xc00(r8) 5676ca88b09STimur Tabi stw r1, 0xc04(r8) 5686ca88b09STimur Tabi sync 5696ca88b09STimur Tabi 5706ca88b09STimur Tabi#else /* #ifdef CONFIG_FSL_CORENET */ 5716ca88b09STimur Tabi 5726ca88b09STimur Tabiwrite_new_ccsrbar: 5736ca88b09STimur Tabi /* 5746ca88b09STimur Tabi * Read the current value of CCSRBAR using a load word instruction 5756ca88b09STimur Tabi * followed by an isync. This forces all accesses to configuration 5766ca88b09STimur Tabi * space to complete. 5776ca88b09STimur Tabi */ 5786ca88b09STimur Tabi sync 5796ca88b09STimur Tabi lwz r0, 0(r9) 5806ca88b09STimur Tabi isync 5816ca88b09STimur Tabi 5826ca88b09STimur Tabi/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ 5836ca88b09STimur Tabi#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ 5846ca88b09STimur Tabi (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) 5856ca88b09STimur Tabi 5866ca88b09STimur Tabi /* Write the new value to CCSRBAR. */ 5876ca88b09STimur Tabi lis r0, CCSRBAR_PHYS_RS12@h 5886ca88b09STimur Tabi ori r0, r0, CCSRBAR_PHYS_RS12@l 5896ca88b09STimur Tabi stw r0, 0(r9) 5906ca88b09STimur Tabi sync 5916ca88b09STimur Tabi 5926ca88b09STimur Tabi /* 5936ca88b09STimur Tabi * The manual says to perform a load of an address that does not 5946ca88b09STimur Tabi * access configuration space or the on-chip SRAM using an existing TLB, 5956ca88b09STimur Tabi * but that doesn't appear to be necessary. We will do the isync, 5966ca88b09STimur Tabi * though. 5976ca88b09STimur Tabi */ 5986ca88b09STimur Tabi isync 5996ca88b09STimur Tabi 6006ca88b09STimur Tabi /* 6016ca88b09STimur Tabi * Read the contents of CCSRBAR from its new location, followed by 6026ca88b09STimur Tabi * another isync. 6036ca88b09STimur Tabi */ 6046ca88b09STimur Tabi lwz r0, 0(r8) 6056ca88b09STimur Tabi isync 6066ca88b09STimur Tabi 6076ca88b09STimur Tabi#endif /* #ifdef CONFIG_FSL_CORENET */ 6086ca88b09STimur Tabi 6096ca88b09STimur Tabi /* Delete the temporary TLBs */ 6106ca88b09STimur Tabidelete_temp_tlbs: 6116ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h 6126ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l 6136ca88b09STimur Tabi li r1, 0 6146ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h 6156ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l 6166ca88b09STimur Tabi mtspr MAS0, r0 6176ca88b09STimur Tabi mtspr MAS1, r1 6186ca88b09STimur Tabi mtspr MAS2, r2 6196ca88b09STimur Tabi isync 6206ca88b09STimur Tabi msync 6216ca88b09STimur Tabi tlbwe 6226ca88b09STimur Tabi 6236ca88b09STimur Tabi lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h 6246ca88b09STimur Tabi ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l 6256ca88b09STimur Tabi lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h 6266ca88b09STimur Tabi ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l 6276ca88b09STimur Tabi mtspr MAS0, r0 6286ca88b09STimur Tabi mtspr MAS2, r2 6296ca88b09STimur Tabi isync 6306ca88b09STimur Tabi msync 6316ca88b09STimur Tabi tlbwe 6326ca88b09STimur Tabi#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ 6336ca88b09STimur Tabi 6346ca88b09STimur Tabicreate_init_ram_area: 635a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h 636a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l 637a47a12beSStefan Roese 6387065b7d4SRuchika Gupta#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) 639a47a12beSStefan Roese /* create a temp mapping in AS=1 to the 4M boot window */ 640a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h 641a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l 642a47a12beSStefan Roese 6430635b09cSHaiying Wang lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h 6440635b09cSHaiying Wang ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l 645a47a12beSStefan Roese 646a47a12beSStefan Roese /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ 647a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 648a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 6497065b7d4SRuchika Gupta#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) 6507065b7d4SRuchika Gupta /* create a temp mapping in AS = 1 for Flash mapping 6517065b7d4SRuchika Gupta * created by PBL for ISBC code 6527065b7d4SRuchika Gupta */ 6537065b7d4SRuchika Gupta lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 6547065b7d4SRuchika Gupta ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 6557065b7d4SRuchika Gupta 6567065b7d4SRuchika Gupta lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 6577065b7d4SRuchika Gupta ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 6587065b7d4SRuchika Gupta 6597065b7d4SRuchika Gupta lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 6607065b7d4SRuchika Gupta (MAS3_SX|MAS3_SW|MAS3_SR))@h 6617065b7d4SRuchika Gupta ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, 6627065b7d4SRuchika Gupta (MAS3_SX|MAS3_SW|MAS3_SR))@l 663a47a12beSStefan Roese#else 664a47a12beSStefan Roese /* 6650635b09cSHaiying Wang * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main 6660635b09cSHaiying Wang * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. 667a47a12beSStefan Roese */ 668a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h 669a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l 670a47a12beSStefan Roese 6710635b09cSHaiying Wang lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h 6720635b09cSHaiying Wang ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l 673a47a12beSStefan Roese 6740635b09cSHaiying Wang lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 6750635b09cSHaiying Wang ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 676a47a12beSStefan Roese#endif 677a47a12beSStefan Roese 678a47a12beSStefan Roese mtspr MAS0,r6 679a47a12beSStefan Roese mtspr MAS1,r7 680a47a12beSStefan Roese mtspr MAS2,r8 681a47a12beSStefan Roese mtspr MAS3,r9 682a47a12beSStefan Roese isync 683a47a12beSStefan Roese msync 684a47a12beSStefan Roese tlbwe 685a47a12beSStefan Roese 686a47a12beSStefan Roese /* create a temp mapping in AS=1 to the stack */ 687a47a12beSStefan Roese lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h 688a47a12beSStefan Roese ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l 689a47a12beSStefan Roese 690a47a12beSStefan Roese lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h 691a47a12beSStefan Roese ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l 692a47a12beSStefan Roese 693a47a12beSStefan Roese lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h 694a47a12beSStefan Roese ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l 695a47a12beSStefan Roese 696a3f18529Syork#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ 697a3f18529Syork defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) 698a3f18529Syork lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 699a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@h 700a3f18529Syork ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0, 701a3f18529Syork (MAS3_SX|MAS3_SW|MAS3_SR))@l 702a3f18529Syork li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 703a3f18529Syork mtspr MAS7,r10 704a3f18529Syork#else 705a47a12beSStefan Roese lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h 706a47a12beSStefan Roese ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l 707a3f18529Syork#endif 708a47a12beSStefan Roese 709a47a12beSStefan Roese mtspr MAS0,r6 710a47a12beSStefan Roese mtspr MAS1,r7 711a47a12beSStefan Roese mtspr MAS2,r8 712a47a12beSStefan Roese mtspr MAS3,r9 713a47a12beSStefan Roese isync 714a47a12beSStefan Roese msync 715a47a12beSStefan Roese tlbwe 716a47a12beSStefan Roese 717a47a12beSStefan Roese lis r6,MSR_IS|MSR_DS@h 718a47a12beSStefan Roese ori r6,r6,MSR_IS|MSR_DS@l 719a47a12beSStefan Roese lis r7,switch_as@h 720a47a12beSStefan Roese ori r7,r7,switch_as@l 721a47a12beSStefan Roese 722a47a12beSStefan Roese mtspr SPRN_SRR0,r7 723a47a12beSStefan Roese mtspr SPRN_SRR1,r6 724a47a12beSStefan Roese rfi 725a47a12beSStefan Roese 726a47a12beSStefan Roeseswitch_as: 727a47a12beSStefan Roese/* L1 DCache is used for initial RAM */ 728a47a12beSStefan Roese 729a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 730a47a12beSStefan Roese */ 731a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 732a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 733a47a12beSStefan Roese mfspr r2, L1CFG0 734a47a12beSStefan Roese andi. r2, r2, 0x1ff 735a47a12beSStefan Roese /* cache size * 1024 / (2 * L1 line size) */ 736a47a12beSStefan Roese slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 737a47a12beSStefan Roese mtctr r2 738a47a12beSStefan Roese li r0,0 739a47a12beSStefan Roese1: 740a47a12beSStefan Roese dcbz r0,r3 741a47a12beSStefan Roese dcbtls 0,r0,r3 742a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 743a47a12beSStefan Roese bdnz 1b 744a47a12beSStefan Roese 745a47a12beSStefan Roese /* Jump out the last 4K page and continue to 'normal' start */ 746a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 747a47a12beSStefan Roese b _start_cont 748a47a12beSStefan Roese#else 749a47a12beSStefan Roese /* Calculate absolute address in FLASH and jump there */ 750a47a12beSStefan Roese /*--------------------------------------------------------------*/ 751a47a12beSStefan Roese lis r3,CONFIG_SYS_MONITOR_BASE@h 752a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_MONITOR_BASE@l 753a47a12beSStefan Roese addi r3,r3,_start_cont - _start + _START_OFFSET 754a47a12beSStefan Roese mtlr r3 755a47a12beSStefan Roese blr 756a47a12beSStefan Roese#endif 757a47a12beSStefan Roese 758a47a12beSStefan Roese .text 759a47a12beSStefan Roese .globl _start 760a47a12beSStefan Roese_start: 761a47a12beSStefan Roese .long 0x27051956 /* U-BOOT Magic Number */ 762a47a12beSStefan Roese .globl version_string 763a47a12beSStefan Roeseversion_string: 76409c2e90cSAndreas Bießmann .ascii U_BOOT_VERSION_STRING, "\0" 765a47a12beSStefan Roese 766a47a12beSStefan Roese .align 4 767a47a12beSStefan Roese .globl _start_cont 768a47a12beSStefan Roese_start_cont: 769a47a12beSStefan Roese /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ 770a47a12beSStefan Roese lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 771a47a12beSStefan Roese ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 772a47a12beSStefan Roese 773a47a12beSStefan Roese li r0,0 774a47a12beSStefan Roese stwu r0,-4(r1) 775a47a12beSStefan Roese stwu r0,-4(r1) /* Terminate call chain */ 776a47a12beSStefan Roese 777a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 778a47a12beSStefan Roese lis r0,RESET_VECTOR@h /* Address of reset vector */ 779a47a12beSStefan Roese ori r0,r0,RESET_VECTOR@l 780a47a12beSStefan Roese stwu r1,-8(r1) /* Save back chain and move SP */ 781a47a12beSStefan Roese stw r0,+12(r1) /* Save return addr (underflow vect) */ 782a47a12beSStefan Roese 783a47a12beSStefan Roese GET_GOT 784a47a12beSStefan Roese bl cpu_init_early_f 785a47a12beSStefan Roese 786a47a12beSStefan Roese /* switch back to AS = 0 */ 787a47a12beSStefan Roese lis r3,(MSR_CE|MSR_ME|MSR_DE)@h 788a47a12beSStefan Roese ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l 789a47a12beSStefan Roese mtmsr r3 790a47a12beSStefan Roese isync 791a47a12beSStefan Roese 792a47a12beSStefan Roese bl cpu_init_f 793a47a12beSStefan Roese bl board_init_f 794a47a12beSStefan Roese isync 795a47a12beSStefan Roese 79652ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 79752ebd9c1SPeter Tyser 798a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 799a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 800a47a12beSStefan Roese .globl _start_of_vectors 801a47a12beSStefan Roese_start_of_vectors: 802a47a12beSStefan Roese 803a47a12beSStefan Roese/* Critical input. */ 804a47a12beSStefan Roese CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) 805a47a12beSStefan Roese 806a47a12beSStefan Roese/* Machine check */ 807a47a12beSStefan Roese MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 808a47a12beSStefan Roese 809a47a12beSStefan Roese/* Data Storage exception. */ 810a47a12beSStefan Roese STD_EXCEPTION(0x0300, DataStorage, UnknownException) 811a47a12beSStefan Roese 812a47a12beSStefan Roese/* Instruction Storage exception. */ 813a47a12beSStefan Roese STD_EXCEPTION(0x0400, InstStorage, UnknownException) 814a47a12beSStefan Roese 815a47a12beSStefan Roese/* External Interrupt exception. */ 816a47a12beSStefan Roese STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) 817a47a12beSStefan Roese 818a47a12beSStefan Roese/* Alignment exception. */ 819a47a12beSStefan Roese . = 0x0600 820a47a12beSStefan RoeseAlignment: 821a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 822a47a12beSStefan Roese mfspr r4,DAR 823a47a12beSStefan Roese stw r4,_DAR(r21) 824a47a12beSStefan Roese mfspr r5,DSISR 825a47a12beSStefan Roese stw r5,_DSISR(r21) 826a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 827a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 828a47a12beSStefan Roese 829a47a12beSStefan Roese/* Program check exception */ 830a47a12beSStefan Roese . = 0x0700 831a47a12beSStefan RoeseProgramCheck: 832a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 833a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 834a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 835a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 836a47a12beSStefan Roese 837a47a12beSStefan Roese /* No FPU on MPC85xx. This exception is not supposed to happen. 838a47a12beSStefan Roese */ 839a47a12beSStefan Roese STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) 840a47a12beSStefan Roese 841a47a12beSStefan Roese . = 0x0900 842a47a12beSStefan Roese/* 843a47a12beSStefan Roese * r0 - SYSCALL number 844a47a12beSStefan Roese * r3-... arguments 845a47a12beSStefan Roese */ 846a47a12beSStefan RoeseSystemCall: 847a47a12beSStefan Roese addis r11,r0,0 /* get functions table addr */ 848a47a12beSStefan Roese ori r11,r11,0 /* Note: this code is patched in trap_init */ 849a47a12beSStefan Roese addis r12,r0,0 /* get number of functions */ 850a47a12beSStefan Roese ori r12,r12,0 851a47a12beSStefan Roese 852a47a12beSStefan Roese cmplw 0,r0,r12 853a47a12beSStefan Roese bge 1f 854a47a12beSStefan Roese 855a47a12beSStefan Roese rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ 856a47a12beSStefan Roese add r11,r11,r0 857a47a12beSStefan Roese lwz r11,0(r11) 858a47a12beSStefan Roese 859a47a12beSStefan Roese li r20,0xd00-4 /* Get stack pointer */ 860a47a12beSStefan Roese lwz r12,0(r20) 861a47a12beSStefan Roese subi r12,r12,12 /* Adjust stack pointer */ 862a47a12beSStefan Roese li r0,0xc00+_end_back-SystemCall 863a47a12beSStefan Roese cmplw 0,r0,r12 /* Check stack overflow */ 864a47a12beSStefan Roese bgt 1f 865a47a12beSStefan Roese stw r12,0(r20) 866a47a12beSStefan Roese 867a47a12beSStefan Roese mflr r0 868a47a12beSStefan Roese stw r0,0(r12) 869a47a12beSStefan Roese mfspr r0,SRR0 870a47a12beSStefan Roese stw r0,4(r12) 871a47a12beSStefan Roese mfspr r0,SRR1 872a47a12beSStefan Roese stw r0,8(r12) 873a47a12beSStefan Roese 874a47a12beSStefan Roese li r12,0xc00+_back-SystemCall 875a47a12beSStefan Roese mtlr r12 876a47a12beSStefan Roese mtspr SRR0,r11 877a47a12beSStefan Roese 878a47a12beSStefan Roese1: SYNC 879a47a12beSStefan Roese rfi 880a47a12beSStefan Roese_back: 881a47a12beSStefan Roese 882a47a12beSStefan Roese mfmsr r11 /* Disable interrupts */ 883a47a12beSStefan Roese li r12,0 884a47a12beSStefan Roese ori r12,r12,MSR_EE 885a47a12beSStefan Roese andc r11,r11,r12 886a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 887a47a12beSStefan Roese mtmsr r11 888a47a12beSStefan Roese SYNC 889a47a12beSStefan Roese 890a47a12beSStefan Roese li r12,0xd00-4 /* restore regs */ 891a47a12beSStefan Roese lwz r12,0(r12) 892a47a12beSStefan Roese 893a47a12beSStefan Roese lwz r11,0(r12) 894a47a12beSStefan Roese mtlr r11 895a47a12beSStefan Roese lwz r11,4(r12) 896a47a12beSStefan Roese mtspr SRR0,r11 897a47a12beSStefan Roese lwz r11,8(r12) 898a47a12beSStefan Roese mtspr SRR1,r11 899a47a12beSStefan Roese 900a47a12beSStefan Roese addi r12,r12,12 /* Adjust stack pointer */ 901a47a12beSStefan Roese li r20,0xd00-4 902a47a12beSStefan Roese stw r12,0(r20) 903a47a12beSStefan Roese 904a47a12beSStefan Roese SYNC 905a47a12beSStefan Roese rfi 906a47a12beSStefan Roese_end_back: 907a47a12beSStefan Roese 908a47a12beSStefan Roese STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) 909a47a12beSStefan Roese STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) 910a47a12beSStefan Roese STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) 911a47a12beSStefan Roese 912a47a12beSStefan Roese STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) 913a47a12beSStefan Roese STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) 914a47a12beSStefan Roese 915a47a12beSStefan Roese CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) 916a47a12beSStefan Roese 917a47a12beSStefan Roese .globl _end_of_vectors 918a47a12beSStefan Roese_end_of_vectors: 919a47a12beSStefan Roese 920a47a12beSStefan Roese 921a47a12beSStefan Roese . = . + (0x100 - ( . & 0xff )) /* align for debug */ 922a47a12beSStefan Roese 923a47a12beSStefan Roese/* 924a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 925a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 926a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 927a47a12beSStefan Roese */ 928a47a12beSStefan Roese .globl transfer_to_handler 929a47a12beSStefan Roesetransfer_to_handler: 930a47a12beSStefan Roese stw r22,_NIP(r21) 931a47a12beSStefan Roese lis r22,MSR_POW@h 932a47a12beSStefan Roese andc r23,r23,r22 933a47a12beSStefan Roese stw r23,_MSR(r21) 934a47a12beSStefan Roese SAVE_GPR(7, r21) 935a47a12beSStefan Roese SAVE_4GPRS(8, r21) 936a47a12beSStefan Roese SAVE_8GPRS(12, r21) 937a47a12beSStefan Roese SAVE_8GPRS(24, r21) 938a47a12beSStefan Roese 939a47a12beSStefan Roese mflr r23 940a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 941a47a12beSStefan Roese stw r24,TRAP(r21) 942a47a12beSStefan Roese li r22,0 943a47a12beSStefan Roese stw r22,RESULT(r21) 944a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 945a47a12beSStefan Roese 946a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 947a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 948a47a12beSStefan Roese mtspr SRR0,r24 949a47a12beSStefan Roese mtspr SRR1,r20 950a47a12beSStefan Roese mtlr r23 951a47a12beSStefan Roese SYNC 952a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 953a47a12beSStefan Roese 954a47a12beSStefan Roeseint_return: 955a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 956a47a12beSStefan Roese li r4,0 957a47a12beSStefan Roese ori r4,r4,MSR_EE 958a47a12beSStefan Roese andc r28,r28,r4 959a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 960a47a12beSStefan Roese mtmsr r28 961a47a12beSStefan Roese SYNC 962a47a12beSStefan Roese lwz r2,_CTR(r1) 963a47a12beSStefan Roese lwz r0,_LINK(r1) 964a47a12beSStefan Roese mtctr r2 965a47a12beSStefan Roese mtlr r0 966a47a12beSStefan Roese lwz r2,_XER(r1) 967a47a12beSStefan Roese lwz r0,_CCR(r1) 968a47a12beSStefan Roese mtspr XER,r2 969a47a12beSStefan Roese mtcrf 0xFF,r0 970a47a12beSStefan Roese REST_10GPRS(3, r1) 971a47a12beSStefan Roese REST_10GPRS(13, r1) 972a47a12beSStefan Roese REST_8GPRS(23, r1) 973a47a12beSStefan Roese REST_GPR(31, r1) 974a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 975a47a12beSStefan Roese lwz r0,_MSR(r1) 976a47a12beSStefan Roese mtspr SRR0,r2 977a47a12beSStefan Roese mtspr SRR1,r0 978a47a12beSStefan Roese lwz r0,GPR0(r1) 979a47a12beSStefan Roese lwz r2,GPR2(r1) 980a47a12beSStefan Roese lwz r1,GPR1(r1) 981a47a12beSStefan Roese SYNC 982a47a12beSStefan Roese rfi 983a47a12beSStefan Roese 984a47a12beSStefan Roesecrit_return: 985a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 986a47a12beSStefan Roese li r4,0 987a47a12beSStefan Roese ori r4,r4,MSR_EE 988a47a12beSStefan Roese andc r28,r28,r4 989a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 990a47a12beSStefan Roese mtmsr r28 991a47a12beSStefan Roese SYNC 992a47a12beSStefan Roese lwz r2,_CTR(r1) 993a47a12beSStefan Roese lwz r0,_LINK(r1) 994a47a12beSStefan Roese mtctr r2 995a47a12beSStefan Roese mtlr r0 996a47a12beSStefan Roese lwz r2,_XER(r1) 997a47a12beSStefan Roese lwz r0,_CCR(r1) 998a47a12beSStefan Roese mtspr XER,r2 999a47a12beSStefan Roese mtcrf 0xFF,r0 1000a47a12beSStefan Roese REST_10GPRS(3, r1) 1001a47a12beSStefan Roese REST_10GPRS(13, r1) 1002a47a12beSStefan Roese REST_8GPRS(23, r1) 1003a47a12beSStefan Roese REST_GPR(31, r1) 1004a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 1005a47a12beSStefan Roese lwz r0,_MSR(r1) 1006a47a12beSStefan Roese mtspr SPRN_CSRR0,r2 1007a47a12beSStefan Roese mtspr SPRN_CSRR1,r0 1008a47a12beSStefan Roese lwz r0,GPR0(r1) 1009a47a12beSStefan Roese lwz r2,GPR2(r1) 1010a47a12beSStefan Roese lwz r1,GPR1(r1) 1011a47a12beSStefan Roese SYNC 1012a47a12beSStefan Roese rfci 1013a47a12beSStefan Roese 1014a47a12beSStefan Roesemck_return: 1015a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 1016a47a12beSStefan Roese li r4,0 1017a47a12beSStefan Roese ori r4,r4,MSR_EE 1018a47a12beSStefan Roese andc r28,r28,r4 1019a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 1020a47a12beSStefan Roese mtmsr r28 1021a47a12beSStefan Roese SYNC 1022a47a12beSStefan Roese lwz r2,_CTR(r1) 1023a47a12beSStefan Roese lwz r0,_LINK(r1) 1024a47a12beSStefan Roese mtctr r2 1025a47a12beSStefan Roese mtlr r0 1026a47a12beSStefan Roese lwz r2,_XER(r1) 1027a47a12beSStefan Roese lwz r0,_CCR(r1) 1028a47a12beSStefan Roese mtspr XER,r2 1029a47a12beSStefan Roese mtcrf 0xFF,r0 1030a47a12beSStefan Roese REST_10GPRS(3, r1) 1031a47a12beSStefan Roese REST_10GPRS(13, r1) 1032a47a12beSStefan Roese REST_8GPRS(23, r1) 1033a47a12beSStefan Roese REST_GPR(31, r1) 1034a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 1035a47a12beSStefan Roese lwz r0,_MSR(r1) 1036a47a12beSStefan Roese mtspr SPRN_MCSRR0,r2 1037a47a12beSStefan Roese mtspr SPRN_MCSRR1,r0 1038a47a12beSStefan Roese lwz r0,GPR0(r1) 1039a47a12beSStefan Roese lwz r2,GPR2(r1) 1040a47a12beSStefan Roese lwz r1,GPR1(r1) 1041a47a12beSStefan Roese SYNC 1042a47a12beSStefan Roese rfmci 1043a47a12beSStefan Roese 1044a47a12beSStefan Roese/* Cache functions. 1045a47a12beSStefan Roese*/ 10460a9fe8eeSMatthew McClintock.globl flush_icache 10470a9fe8eeSMatthew McClintockflush_icache: 1048a47a12beSStefan Roese.globl invalidate_icache 1049a47a12beSStefan Roeseinvalidate_icache: 1050a47a12beSStefan Roese mfspr r0,L1CSR1 1051a47a12beSStefan Roese ori r0,r0,L1CSR1_ICFI 1052a47a12beSStefan Roese msync 1053a47a12beSStefan Roese isync 1054a47a12beSStefan Roese mtspr L1CSR1,r0 1055a47a12beSStefan Roese isync 1056a47a12beSStefan Roese blr /* entire I cache */ 1057a47a12beSStefan Roese 1058a47a12beSStefan Roese.globl invalidate_dcache 1059a47a12beSStefan Roeseinvalidate_dcache: 1060a47a12beSStefan Roese mfspr r0,L1CSR0 1061a47a12beSStefan Roese ori r0,r0,L1CSR0_DCFI 1062a47a12beSStefan Roese msync 1063a47a12beSStefan Roese isync 1064a47a12beSStefan Roese mtspr L1CSR0,r0 1065a47a12beSStefan Roese isync 1066a47a12beSStefan Roese blr 1067a47a12beSStefan Roese 1068a47a12beSStefan Roese .globl icache_enable 1069a47a12beSStefan Roeseicache_enable: 1070a47a12beSStefan Roese mflr r8 1071a47a12beSStefan Roese bl invalidate_icache 1072a47a12beSStefan Roese mtlr r8 1073a47a12beSStefan Roese isync 1074a47a12beSStefan Roese mfspr r4,L1CSR1 1075a47a12beSStefan Roese ori r4,r4,0x0001 1076a47a12beSStefan Roese oris r4,r4,0x0001 1077a47a12beSStefan Roese mtspr L1CSR1,r4 1078a47a12beSStefan Roese isync 1079a47a12beSStefan Roese blr 1080a47a12beSStefan Roese 1081a47a12beSStefan Roese .globl icache_disable 1082a47a12beSStefan Roeseicache_disable: 1083a47a12beSStefan Roese mfspr r0,L1CSR1 1084a47a12beSStefan Roese lis r3,0 1085a47a12beSStefan Roese ori r3,r3,L1CSR1_ICE 1086a47a12beSStefan Roese andc r0,r0,r3 1087a47a12beSStefan Roese mtspr L1CSR1,r0 1088a47a12beSStefan Roese isync 1089a47a12beSStefan Roese blr 1090a47a12beSStefan Roese 1091a47a12beSStefan Roese .globl icache_status 1092a47a12beSStefan Roeseicache_status: 1093a47a12beSStefan Roese mfspr r3,L1CSR1 1094a47a12beSStefan Roese andi. r3,r3,L1CSR1_ICE 1095a47a12beSStefan Roese blr 1096a47a12beSStefan Roese 1097a47a12beSStefan Roese .globl dcache_enable 1098a47a12beSStefan Roesedcache_enable: 1099a47a12beSStefan Roese mflr r8 1100a47a12beSStefan Roese bl invalidate_dcache 1101a47a12beSStefan Roese mtlr r8 1102a47a12beSStefan Roese isync 1103a47a12beSStefan Roese mfspr r0,L1CSR0 1104a47a12beSStefan Roese ori r0,r0,0x0001 1105a47a12beSStefan Roese oris r0,r0,0x0001 1106a47a12beSStefan Roese msync 1107a47a12beSStefan Roese isync 1108a47a12beSStefan Roese mtspr L1CSR0,r0 1109a47a12beSStefan Roese isync 1110a47a12beSStefan Roese blr 1111a47a12beSStefan Roese 1112a47a12beSStefan Roese .globl dcache_disable 1113a47a12beSStefan Roesedcache_disable: 1114a47a12beSStefan Roese mfspr r3,L1CSR0 1115a47a12beSStefan Roese lis r4,0 1116a47a12beSStefan Roese ori r4,r4,L1CSR0_DCE 1117a47a12beSStefan Roese andc r3,r3,r4 111845a68135SKumar Gala mtspr L1CSR0,r3 1119a47a12beSStefan Roese isync 1120a47a12beSStefan Roese blr 1121a47a12beSStefan Roese 1122a47a12beSStefan Roese .globl dcache_status 1123a47a12beSStefan Roesedcache_status: 1124a47a12beSStefan Roese mfspr r3,L1CSR0 1125a47a12beSStefan Roese andi. r3,r3,L1CSR0_DCE 1126a47a12beSStefan Roese blr 1127a47a12beSStefan Roese 1128a47a12beSStefan Roese .globl get_pir 1129a47a12beSStefan Roeseget_pir: 1130a47a12beSStefan Roese mfspr r3,PIR 1131a47a12beSStefan Roese blr 1132a47a12beSStefan Roese 1133a47a12beSStefan Roese .globl get_pvr 1134a47a12beSStefan Roeseget_pvr: 1135a47a12beSStefan Roese mfspr r3,PVR 1136a47a12beSStefan Roese blr 1137a47a12beSStefan Roese 1138a47a12beSStefan Roese .globl get_svr 1139a47a12beSStefan Roeseget_svr: 1140a47a12beSStefan Roese mfspr r3,SVR 1141a47a12beSStefan Roese blr 1142a47a12beSStefan Roese 1143a47a12beSStefan Roese .globl wr_tcr 1144a47a12beSStefan Roesewr_tcr: 1145a47a12beSStefan Roese mtspr TCR,r3 1146a47a12beSStefan Roese blr 1147a47a12beSStefan Roese 1148a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1149a47a12beSStefan Roese/* Function: in8 */ 1150a47a12beSStefan Roese/* Description: Input 8 bits */ 1151a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1152a47a12beSStefan Roese .globl in8 1153a47a12beSStefan Roesein8: 1154a47a12beSStefan Roese lbz r3,0x0000(r3) 1155a47a12beSStefan Roese blr 1156a47a12beSStefan Roese 1157a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1158a47a12beSStefan Roese/* Function: out8 */ 1159a47a12beSStefan Roese/* Description: Output 8 bits */ 1160a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1161a47a12beSStefan Roese .globl out8 1162a47a12beSStefan Roeseout8: 1163a47a12beSStefan Roese stb r4,0x0000(r3) 1164a47a12beSStefan Roese sync 1165a47a12beSStefan Roese blr 1166a47a12beSStefan Roese 1167a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1168a47a12beSStefan Roese/* Function: out16 */ 1169a47a12beSStefan Roese/* Description: Output 16 bits */ 1170a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1171a47a12beSStefan Roese .globl out16 1172a47a12beSStefan Roeseout16: 1173a47a12beSStefan Roese sth r4,0x0000(r3) 1174a47a12beSStefan Roese sync 1175a47a12beSStefan Roese blr 1176a47a12beSStefan Roese 1177a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1178a47a12beSStefan Roese/* Function: out16r */ 1179a47a12beSStefan Roese/* Description: Byte reverse and output 16 bits */ 1180a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1181a47a12beSStefan Roese .globl out16r 1182a47a12beSStefan Roeseout16r: 1183a47a12beSStefan Roese sthbrx r4,r0,r3 1184a47a12beSStefan Roese sync 1185a47a12beSStefan Roese blr 1186a47a12beSStefan Roese 1187a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1188a47a12beSStefan Roese/* Function: out32 */ 1189a47a12beSStefan Roese/* Description: Output 32 bits */ 1190a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1191a47a12beSStefan Roese .globl out32 1192a47a12beSStefan Roeseout32: 1193a47a12beSStefan Roese stw r4,0x0000(r3) 1194a47a12beSStefan Roese sync 1195a47a12beSStefan Roese blr 1196a47a12beSStefan Roese 1197a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1198a47a12beSStefan Roese/* Function: out32r */ 1199a47a12beSStefan Roese/* Description: Byte reverse and output 32 bits */ 1200a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1201a47a12beSStefan Roese .globl out32r 1202a47a12beSStefan Roeseout32r: 1203a47a12beSStefan Roese stwbrx r4,r0,r3 1204a47a12beSStefan Roese sync 1205a47a12beSStefan Roese blr 1206a47a12beSStefan Roese 1207a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1208a47a12beSStefan Roese/* Function: in16 */ 1209a47a12beSStefan Roese/* Description: Input 16 bits */ 1210a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1211a47a12beSStefan Roese .globl in16 1212a47a12beSStefan Roesein16: 1213a47a12beSStefan Roese lhz r3,0x0000(r3) 1214a47a12beSStefan Roese blr 1215a47a12beSStefan Roese 1216a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1217a47a12beSStefan Roese/* Function: in16r */ 1218a47a12beSStefan Roese/* Description: Input 16 bits and byte reverse */ 1219a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1220a47a12beSStefan Roese .globl in16r 1221a47a12beSStefan Roesein16r: 1222a47a12beSStefan Roese lhbrx r3,r0,r3 1223a47a12beSStefan Roese blr 1224a47a12beSStefan Roese 1225a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1226a47a12beSStefan Roese/* Function: in32 */ 1227a47a12beSStefan Roese/* Description: Input 32 bits */ 1228a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1229a47a12beSStefan Roese .globl in32 1230a47a12beSStefan Roesein32: 1231a47a12beSStefan Roese lwz 3,0x0000(3) 1232a47a12beSStefan Roese blr 1233a47a12beSStefan Roese 1234a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1235a47a12beSStefan Roese/* Function: in32r */ 1236a47a12beSStefan Roese/* Description: Input 32 bits and byte reverse */ 1237a47a12beSStefan Roese/*------------------------------------------------------------------------------- */ 1238a47a12beSStefan Roese .globl in32r 1239a47a12beSStefan Roesein32r: 1240a47a12beSStefan Roese lwbrx r3,r0,r3 1241a47a12beSStefan Roese blr 1242a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1243a47a12beSStefan Roese 1244a47a12beSStefan Roese/*------------------------------------------------------------------------------*/ 1245a47a12beSStefan Roese 1246a47a12beSStefan Roese/* 1247a47a12beSStefan Roese * void write_tlb(mas0, mas1, mas2, mas3, mas7) 1248a47a12beSStefan Roese */ 1249a47a12beSStefan Roese .globl write_tlb 1250a47a12beSStefan Roesewrite_tlb: 1251a47a12beSStefan Roese mtspr MAS0,r3 1252a47a12beSStefan Roese mtspr MAS1,r4 1253a47a12beSStefan Roese mtspr MAS2,r5 1254a47a12beSStefan Roese mtspr MAS3,r6 1255a47a12beSStefan Roese#ifdef CONFIG_ENABLE_36BIT_PHYS 1256a47a12beSStefan Roese mtspr MAS7,r7 1257a47a12beSStefan Roese#endif 1258a47a12beSStefan Roese li r3,0 1259a47a12beSStefan Roese#ifdef CONFIG_SYS_BOOK3E_HV 1260a47a12beSStefan Roese mtspr MAS8,r3 1261a47a12beSStefan Roese#endif 1262a47a12beSStefan Roese isync 1263a47a12beSStefan Roese tlbwe 1264a47a12beSStefan Roese msync 1265a47a12beSStefan Roese isync 1266a47a12beSStefan Roese blr 1267a47a12beSStefan Roese 1268a47a12beSStefan Roese/* 1269a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 1270a47a12beSStefan Roese * 1271a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 1272a47a12beSStefan Roese * after relocating the monitor code. 1273a47a12beSStefan Roese * 1274a47a12beSStefan Roese * r3 = dest 1275a47a12beSStefan Roese * r4 = src 1276a47a12beSStefan Roese * r5 = length in bytes 1277a47a12beSStefan Roese * r6 = cachelinesize 1278a47a12beSStefan Roese */ 1279a47a12beSStefan Roese .globl relocate_code 1280a47a12beSStefan Roeserelocate_code: 1281a47a12beSStefan Roese mr r1,r3 /* Set new stack pointer */ 1282a47a12beSStefan Roese mr r9,r4 /* Save copy of Init Data pointer */ 1283a47a12beSStefan Roese mr r10,r5 /* Save copy of Destination Address */ 1284a47a12beSStefan Roese 1285a47a12beSStefan Roese GET_GOT 1286a47a12beSStefan Roese mr r3,r5 /* Destination Address */ 1287a47a12beSStefan Roese lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1288a47a12beSStefan Roese ori r4,r4,CONFIG_SYS_MONITOR_BASE@l 1289a47a12beSStefan Roese lwz r5,GOT(__init_end) 1290a47a12beSStefan Roese sub r5,r5,r4 1291a47a12beSStefan Roese li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 1292a47a12beSStefan Roese 1293a47a12beSStefan Roese /* 1294a47a12beSStefan Roese * Fix GOT pointer: 1295a47a12beSStefan Roese * 1296a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1297a47a12beSStefan Roese * 1298a47a12beSStefan Roese * Offset: 1299a47a12beSStefan Roese */ 1300a47a12beSStefan Roese sub r15,r10,r4 1301a47a12beSStefan Roese 1302a47a12beSStefan Roese /* First our own GOT */ 1303a47a12beSStefan Roese add r12,r12,r15 1304a47a12beSStefan Roese /* the the one used by the C code */ 1305a47a12beSStefan Roese add r30,r30,r15 1306a47a12beSStefan Roese 1307a47a12beSStefan Roese /* 1308a47a12beSStefan Roese * Now relocate code 1309a47a12beSStefan Roese */ 1310a47a12beSStefan Roese 1311a47a12beSStefan Roese cmplw cr1,r3,r4 1312a47a12beSStefan Roese addi r0,r5,3 1313a47a12beSStefan Roese srwi. r0,r0,2 1314a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 1315a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 1316a47a12beSStefan Roese mtctr r0 1317a47a12beSStefan Roese bge cr1,2f 1318a47a12beSStefan Roese 1319a47a12beSStefan Roese la r8,-4(r4) 1320a47a12beSStefan Roese la r7,-4(r3) 1321a47a12beSStefan Roese1: lwzu r0,4(r8) 1322a47a12beSStefan Roese stwu r0,4(r7) 1323a47a12beSStefan Roese bdnz 1b 1324a47a12beSStefan Roese b 4f 1325a47a12beSStefan Roese 1326a47a12beSStefan Roese2: slwi r0,r0,2 1327a47a12beSStefan Roese add r8,r4,r0 1328a47a12beSStefan Roese add r7,r3,r0 1329a47a12beSStefan Roese3: lwzu r0,-4(r8) 1330a47a12beSStefan Roese stwu r0,-4(r7) 1331a47a12beSStefan Roese bdnz 3b 1332a47a12beSStefan Roese 1333a47a12beSStefan Roese/* 1334a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 1335a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 1336a47a12beSStefan Roese */ 1337a47a12beSStefan Roese4: cmpwi r6,0 1338a47a12beSStefan Roese add r5,r3,r5 1339a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 1340a47a12beSStefan Roese subi r0,r6,1 1341a47a12beSStefan Roese andc r3,r3,r0 1342a47a12beSStefan Roese mr r4,r3 1343a47a12beSStefan Roese5: dcbst 0,r4 1344a47a12beSStefan Roese add r4,r4,r6 1345a47a12beSStefan Roese cmplw r4,r5 1346a47a12beSStefan Roese blt 5b 1347a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 1348a47a12beSStefan Roese mr r4,r3 1349a47a12beSStefan Roese6: icbi 0,r4 1350a47a12beSStefan Roese add r4,r4,r6 1351a47a12beSStefan Roese cmplw r4,r5 1352a47a12beSStefan Roese blt 6b 1353a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 1354a47a12beSStefan Roese isync 1355a47a12beSStefan Roese 1356a47a12beSStefan Roese /* 1357a47a12beSStefan Roese * Re-point the IVPR at RAM 1358a47a12beSStefan Roese */ 1359a47a12beSStefan Roese mtspr IVPR,r10 1360a47a12beSStefan Roese 1361a47a12beSStefan Roese/* 1362a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 1363a47a12beSStefan Roese * initialization, now running from RAM. 1364a47a12beSStefan Roese */ 1365a47a12beSStefan Roese 1366a47a12beSStefan Roese addi r0,r10,in_ram - _start + _START_OFFSET 1367a47a12beSStefan Roese mtlr r0 1368a47a12beSStefan Roese blr /* NEVER RETURNS! */ 1369a47a12beSStefan Roese .globl in_ram 1370a47a12beSStefan Roesein_ram: 1371a47a12beSStefan Roese 1372a47a12beSStefan Roese /* 1373a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 1374a47a12beSStefan Roese * 1375a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 1376a47a12beSStefan Roese * already puts a few entries in the table. 1377a47a12beSStefan Roese */ 1378a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 1379a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 1380a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 1381a47a12beSStefan Roese mtctr r0 1382a47a12beSStefan Roese sub r11,r3,r11 1383a47a12beSStefan Roese addi r3,r3,-4 1384a47a12beSStefan Roese1: lwzu r0,4(r3) 1385a47a12beSStefan Roese cmpwi r0,0 1386a47a12beSStefan Roese beq- 2f 1387a47a12beSStefan Roese add r0,r0,r11 1388a47a12beSStefan Roese stw r0,0(r3) 1389a47a12beSStefan Roese2: bdnz 1b 1390a47a12beSStefan Roese 1391a47a12beSStefan Roese /* 1392a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 1393a47a12beSStefan Roese * in case we need to move ourselves again. 1394a47a12beSStefan Roese */ 1395a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 1396a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 1397a47a12beSStefan Roese cmpwi r0,0 1398a47a12beSStefan Roese mtctr r0 1399a47a12beSStefan Roese addi r3,r3,-4 1400a47a12beSStefan Roese beq 4f 1401a47a12beSStefan Roese3: lwzu r4,4(r3) 1402a47a12beSStefan Roese lwzux r0,r4,r11 1403d1e0b10aSJoakim Tjernlund cmpwi r0,0 1404a47a12beSStefan Roese add r0,r0,r11 140534bbf618SJoakim Tjernlund stw r4,0(r3) 1406d1e0b10aSJoakim Tjernlund beq- 5f 1407a47a12beSStefan Roese stw r0,0(r4) 1408d1e0b10aSJoakim Tjernlund5: bdnz 3b 1409a47a12beSStefan Roese4: 1410a47a12beSStefan Roeseclear_bss: 1411a47a12beSStefan Roese /* 1412a47a12beSStefan Roese * Now clear BSS segment 1413a47a12beSStefan Roese */ 1414a47a12beSStefan Roese lwz r3,GOT(__bss_start) 141544c6e659SPo-Yu Chuang lwz r4,GOT(__bss_end__) 1416a47a12beSStefan Roese 1417a47a12beSStefan Roese cmplw 0,r3,r4 1418a47a12beSStefan Roese beq 6f 1419a47a12beSStefan Roese 1420a47a12beSStefan Roese li r0,0 1421a47a12beSStefan Roese5: 1422a47a12beSStefan Roese stw r0,0(r3) 1423a47a12beSStefan Roese addi r3,r3,4 1424a47a12beSStefan Roese cmplw 0,r3,r4 1425a47a12beSStefan Roese bne 5b 1426a47a12beSStefan Roese6: 1427a47a12beSStefan Roese 1428a47a12beSStefan Roese mr r3,r9 /* Init Data pointer */ 1429a47a12beSStefan Roese mr r4,r10 /* Destination Address */ 1430a47a12beSStefan Roese bl board_init_r 1431a47a12beSStefan Roese 1432a47a12beSStefan Roese#ifndef CONFIG_NAND_SPL 1433a47a12beSStefan Roese /* 1434a47a12beSStefan Roese * Copy exception vector code to low memory 1435a47a12beSStefan Roese * 1436a47a12beSStefan Roese * r3: dest_addr 1437a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 1438a47a12beSStefan Roese */ 1439a47a12beSStefan Roese .globl trap_init 1440a47a12beSStefan Roesetrap_init: 1441a47a12beSStefan Roese mflr r4 /* save link register */ 1442a47a12beSStefan Roese GET_GOT 1443a47a12beSStefan Roese lwz r7,GOT(_start_of_vectors) 1444a47a12beSStefan Roese lwz r8,GOT(_end_of_vectors) 1445a47a12beSStefan Roese 1446a47a12beSStefan Roese li r9,0x100 /* reset vector always at 0x100 */ 1447a47a12beSStefan Roese 1448a47a12beSStefan Roese cmplw 0,r7,r8 1449a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 1450a47a12beSStefan Roese1: 1451a47a12beSStefan Roese lwz r0,0(r7) 1452a47a12beSStefan Roese stw r0,0(r9) 1453a47a12beSStefan Roese addi r7,r7,4 1454a47a12beSStefan Roese addi r9,r9,4 1455a47a12beSStefan Roese cmplw 0,r7,r8 1456a47a12beSStefan Roese bne 1b 1457a47a12beSStefan Roese 1458a47a12beSStefan Roese /* 1459a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 1460a47a12beSStefan Roese */ 1461a47a12beSStefan Roese li r7,.L_CriticalInput - _start + _START_OFFSET 1462a47a12beSStefan Roese bl trap_reloc 1463a47a12beSStefan Roese li r7,.L_MachineCheck - _start + _START_OFFSET 1464a47a12beSStefan Roese bl trap_reloc 1465a47a12beSStefan Roese li r7,.L_DataStorage - _start + _START_OFFSET 1466a47a12beSStefan Roese bl trap_reloc 1467a47a12beSStefan Roese li r7,.L_InstStorage - _start + _START_OFFSET 1468a47a12beSStefan Roese bl trap_reloc 1469a47a12beSStefan Roese li r7,.L_ExtInterrupt - _start + _START_OFFSET 1470a47a12beSStefan Roese bl trap_reloc 1471a47a12beSStefan Roese li r7,.L_Alignment - _start + _START_OFFSET 1472a47a12beSStefan Roese bl trap_reloc 1473a47a12beSStefan Roese li r7,.L_ProgramCheck - _start + _START_OFFSET 1474a47a12beSStefan Roese bl trap_reloc 1475a47a12beSStefan Roese li r7,.L_FPUnavailable - _start + _START_OFFSET 1476a47a12beSStefan Roese bl trap_reloc 1477a47a12beSStefan Roese li r7,.L_Decrementer - _start + _START_OFFSET 1478a47a12beSStefan Roese bl trap_reloc 1479a47a12beSStefan Roese li r7,.L_IntervalTimer - _start + _START_OFFSET 1480a47a12beSStefan Roese li r8,_end_of_vectors - _start + _START_OFFSET 1481a47a12beSStefan Roese2: 1482a47a12beSStefan Roese bl trap_reloc 1483a47a12beSStefan Roese addi r7,r7,0x100 /* next exception vector */ 1484a47a12beSStefan Roese cmplw 0,r7,r8 1485a47a12beSStefan Roese blt 2b 1486a47a12beSStefan Roese 1487a47a12beSStefan Roese lis r7,0x0 1488a47a12beSStefan Roese mtspr IVPR,r7 1489a47a12beSStefan Roese 1490a47a12beSStefan Roese mtlr r4 /* restore link register */ 1491a47a12beSStefan Roese blr 1492a47a12beSStefan Roese 1493a47a12beSStefan Roese.globl unlock_ram_in_cache 1494a47a12beSStefan Roeseunlock_ram_in_cache: 1495a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 1496a47a12beSStefan Roese lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h 1497a47a12beSStefan Roese ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l 1498a47a12beSStefan Roese mfspr r4,L1CFG0 1499a47a12beSStefan Roese andi. r4,r4,0x1ff 1500a47a12beSStefan Roese slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) 1501a47a12beSStefan Roese mtctr r4 1502a47a12beSStefan Roese1: dcbi r0,r3 1503a47a12beSStefan Roese addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 1504a47a12beSStefan Roese bdnz 1b 1505a47a12beSStefan Roese sync 1506a47a12beSStefan Roese 1507a47a12beSStefan Roese /* Invalidate the TLB entries for the cache */ 1508a47a12beSStefan Roese lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 1509a47a12beSStefan Roese ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 1510a47a12beSStefan Roese tlbivax 0,r3 1511a47a12beSStefan Roese addi r3,r3,0x1000 1512a47a12beSStefan Roese tlbivax 0,r3 1513a47a12beSStefan Roese addi r3,r3,0x1000 1514a47a12beSStefan Roese tlbivax 0,r3 1515a47a12beSStefan Roese addi r3,r3,0x1000 1516a47a12beSStefan Roese tlbivax 0,r3 1517a47a12beSStefan Roese isync 1518a47a12beSStefan Roese blr 1519a47a12beSStefan Roese 1520a47a12beSStefan Roese.globl flush_dcache 1521a47a12beSStefan Roeseflush_dcache: 1522a47a12beSStefan Roese mfspr r3,SPRN_L1CFG0 1523a47a12beSStefan Roese 1524a47a12beSStefan Roese rlwinm r5,r3,9,3 /* Extract cache block size */ 1525a47a12beSStefan Roese twlgti r5,1 /* Only 32 and 64 byte cache blocks 1526a47a12beSStefan Roese * are currently defined. 1527a47a12beSStefan Roese */ 1528a47a12beSStefan Roese li r4,32 1529a47a12beSStefan Roese subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1530a47a12beSStefan Roese * log2(number of ways) 1531a47a12beSStefan Roese */ 1532a47a12beSStefan Roese slw r5,r4,r5 /* r5 = cache block size */ 1533a47a12beSStefan Roese 1534a47a12beSStefan Roese rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1535a47a12beSStefan Roese mulli r7,r7,13 /* An 8-way cache will require 13 1536a47a12beSStefan Roese * loads per set. 1537a47a12beSStefan Roese */ 1538a47a12beSStefan Roese slw r7,r7,r6 1539a47a12beSStefan Roese 1540a47a12beSStefan Roese /* save off HID0 and set DCFA */ 1541a47a12beSStefan Roese mfspr r8,SPRN_HID0 1542a47a12beSStefan Roese ori r9,r8,HID0_DCFA@l 1543a47a12beSStefan Roese mtspr SPRN_HID0,r9 1544a47a12beSStefan Roese isync 1545a47a12beSStefan Roese 1546a47a12beSStefan Roese lis r4,0 1547a47a12beSStefan Roese mtctr r7 1548a47a12beSStefan Roese 1549a47a12beSStefan Roese1: lwz r3,0(r4) /* Load... */ 1550a47a12beSStefan Roese add r4,r4,r5 1551a47a12beSStefan Roese bdnz 1b 1552a47a12beSStefan Roese 1553a47a12beSStefan Roese msync 1554a47a12beSStefan Roese lis r4,0 1555a47a12beSStefan Roese mtctr r7 1556a47a12beSStefan Roese 1557a47a12beSStefan Roese1: dcbf 0,r4 /* ...and flush. */ 1558a47a12beSStefan Roese add r4,r4,r5 1559a47a12beSStefan Roese bdnz 1b 1560a47a12beSStefan Roese 1561a47a12beSStefan Roese /* restore HID0 */ 1562a47a12beSStefan Roese mtspr SPRN_HID0,r8 1563a47a12beSStefan Roese isync 1564a47a12beSStefan Roese 1565a47a12beSStefan Roese blr 1566a47a12beSStefan Roese 1567a47a12beSStefan Roese.globl setup_ivors 1568a47a12beSStefan Roesesetup_ivors: 1569a47a12beSStefan Roese 1570a47a12beSStefan Roese#include "fixed_ivor.S" 1571a47a12beSStefan Roese blr 1572a47a12beSStefan Roese#endif /* !CONFIG_NAND_SPL */ 1573