17865f4b0SMasahiro Yamadaif ARCH_SOCFPGA 27865f4b0SMasahiro Yamada 3f0fb4fa7SDalon Westergreenconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 4f0fb4fa7SDalon Westergreen default 0xa2 5f0fb4fa7SDalon Westergreen 6cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5 7cd9b7317SMarek Vasut bool 8ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 9cd9b7317SMarek Vasut 10d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10 11d89e979cSLey Foon Tan bool 12901af3e9STien Fong Chee select ALTERA_SDRAM 1358008cbaSMichal Simek select SPL_BOARD_INIT if SPL 14934aec71SMarek Vasut select CLK 15934aec71SMarek Vasut select SPL_CLK if SPL 16fe88c2feSMarek Vasut select DM_I2C 178145c1c2SMarek Vasut select DM_RESET 188145c1c2SMarek Vasut select SPL_DM_RESET if SPL 19d6a61da4SMarek Vasut select REGMAP 20d6a61da4SMarek Vasut select SPL_REGMAP if SPL 21d6a61da4SMarek Vasut select SYSCON 22d6a61da4SMarek Vasut select SPL_SYSCON if SPL 23d6a61da4SMarek Vasut select ETH_DESIGNWARE_SOCFPGA 24d89e979cSLey Foon Tan 25cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5 26cd9b7317SMarek Vasut bool 27ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 28ed77aeb5SDinh Nguyen 29ed77aeb5SDinh Nguyenconfig TARGET_SOCFPGA_GEN5 30ed77aeb5SDinh Nguyen bool 31707cd012SLey Foon Tan select ALTERA_SDRAM 32cd9b7317SMarek Vasut 33a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10 34a684729aSLey Foon Tan bool 35a684729aSLey Foon Tan select ARMV8_MULTIENTRY 36a684729aSLey Foon Tan select ARMV8_SET_SMPEN 3758008cbaSMichal Simek select ARMV8_SPIN_TABLE 38*bd558171SAng, Chee Hong select FPGA_STRATIX10 39a684729aSLey Foon Tan 407865f4b0SMasahiro Yamadachoice 417865f4b0SMasahiro Yamada prompt "Altera SOCFPGA board select" 42a26cd049SJoe Hershberger optional 437865f4b0SMasahiro Yamada 44d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10_SOCDK 45d89e979cSLey Foon Tan bool "Altera SOCFPGA SoCDK (Arria 10)" 46d89e979cSLey Foon Tan select TARGET_SOCFPGA_ARRIA10 47d89e979cSLey Foon Tan 48cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5_SOCDK 49cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Arria V)" 50cd9b7317SMarek Vasut select TARGET_SOCFPGA_ARRIA5 517865f4b0SMasahiro Yamada 52cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 53cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Cyclone V)" 54cd9b7317SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 557865f4b0SMasahiro Yamada 567fb46430SMarek Vasutconfig TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 577fb46430SMarek Vasut bool "Devboards DBM-SoC1 (Cyclone V)" 587fb46430SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 597fb46430SMarek Vasut 60856b30daSMarek Vasutconfig TARGET_SOCFPGA_EBV_SOCRATES 61856b30daSMarek Vasut bool "EBV SoCrates (Cyclone V)" 62856b30daSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 63856b30daSMarek Vasut 6435546f6fSPavel Machekconfig TARGET_SOCFPGA_IS1 6535546f6fSPavel Machek bool "IS1 (Cyclone V)" 6635546f6fSPavel Machek select TARGET_SOCFPGA_CYCLONE5 6735546f6fSPavel Machek 68569a191aSMarek Vasutconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 69569a191aSMarek Vasut bool "samtec VIN|ING FPGA (Cyclone V)" 70e5ec4815STom Rini select BOARD_LATE_INIT 71569a191aSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 72569a191aSMarek Vasut 73cf0a8dabSMarek Vasutconfig TARGET_SOCFPGA_SR1500 74cf0a8dabSMarek Vasut bool "SR1500 (Cyclone V)" 75cf0a8dabSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 76cf0a8dabSMarek Vasut 77a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10_SOCDK 78a684729aSLey Foon Tan bool "Intel SOCFPGA SoCDK (Stratix 10)" 79a684729aSLey Foon Tan select TARGET_SOCFPGA_STRATIX10 80a684729aSLey Foon Tan 8155c7a765SDinh Nguyenconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 8255c7a765SDinh Nguyen bool "Terasic DE0-Nano-Atlas (Cyclone V)" 8355c7a765SDinh Nguyen select TARGET_SOCFPGA_CYCLONE5 8455c7a765SDinh Nguyen 856bd041f0SDalon Westergreenconfig TARGET_SOCFPGA_TERASIC_DE10_NANO 866bd041f0SDalon Westergreen bool "Terasic DE10-Nano (Cyclone V)" 876bd041f0SDalon Westergreen select TARGET_SOCFPGA_CYCLONE5 886bd041f0SDalon Westergreen 89e9c847c3SAnatolij Gustschinconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 90e9c847c3SAnatolij Gustschin bool "Terasic DE1-SoC (Cyclone V)" 91e9c847c3SAnatolij Gustschin select TARGET_SOCFPGA_CYCLONE5 92e9c847c3SAnatolij Gustschin 93952caa28SMarek Vasutconfig TARGET_SOCFPGA_TERASIC_SOCKIT 94952caa28SMarek Vasut bool "Terasic SoCkit (Cyclone V)" 95952caa28SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 96952caa28SMarek Vasut 977865f4b0SMasahiro Yamadaendchoice 987865f4b0SMasahiro Yamada 997865f4b0SMasahiro Yamadaconfig SYS_BOARD 100f0892401SMarek Vasut default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 101d89e979cSLey Foon Tan default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 102f0892401SMarek Vasut default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1037fb46430SMarek Vasut default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 10455c7a765SDinh Nguyen default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 105e9c847c3SAnatolij Gustschin default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1066bd041f0SDalon Westergreen default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 10735546f6fSPavel Machek default "is1" if TARGET_SOCFPGA_IS1 108952caa28SMarek Vasut default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 109856b30daSMarek Vasut default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 110ae9996c8SStefan Roese default "sr1500" if TARGET_SOCFPGA_SR1500 111a684729aSLey Foon Tan default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 112569a191aSMarek Vasut default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1137865f4b0SMasahiro Yamada 1147865f4b0SMasahiro Yamadaconfig SYS_VENDOR 115cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 116d89e979cSLey Foon Tan default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 117cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 118a684729aSLey Foon Tan default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 1197fb46430SMarek Vasut default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 120856b30daSMarek Vasut default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 121569a191aSMarek Vasut default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 12255c7a765SDinh Nguyen default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 123e9c847c3SAnatolij Gustschin default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1246bd041f0SDalon Westergreen default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 125952caa28SMarek Vasut default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 1267865f4b0SMasahiro Yamada 1277865f4b0SMasahiro Yamadaconfig SYS_SOC 1287865f4b0SMasahiro Yamada default "socfpga" 1297865f4b0SMasahiro Yamada 1307865f4b0SMasahiro Yamadaconfig SYS_CONFIG_NAME 1313cbc7b87SDinh Nguyen default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 132d89e979cSLey Foon Tan default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 1333cbc7b87SDinh Nguyen default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1347fb46430SMarek Vasut default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 13555c7a765SDinh Nguyen default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 136e9c847c3SAnatolij Gustschin default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1376bd041f0SDalon Westergreen default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 13835546f6fSPavel Machek default "socfpga_is1" if TARGET_SOCFPGA_IS1 139952caa28SMarek Vasut default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 140856b30daSMarek Vasut default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 141ae9996c8SStefan Roese default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 142a684729aSLey Foon Tan default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 143569a191aSMarek Vasut default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1447865f4b0SMasahiro Yamada 1457865f4b0SMasahiro Yamadaendif 146