13f781edcSryan_chen#include <dt-bindings/clock/ast2500-clock.h> 2c93adc08Smaxims@google.com#include <dt-bindings/reset/ast2500-reset.h> 314e4b149Smaxims@google.com 414e4b149Smaxims@google.com#include "ast2500.dtsi" 514e4b149Smaxims@google.com 614e4b149Smaxims@google.com/ { 714e4b149Smaxims@google.com scu: clock-controller@1e6e2000 { 814e4b149Smaxims@google.com compatible = "aspeed,ast2500-scu"; 914e4b149Smaxims@google.com reg = <0x1e6e2000 0x1000>; 1014e4b149Smaxims@google.com u-boot,dm-pre-reloc; 1114e4b149Smaxims@google.com #clock-cells = <1>; 1214e4b149Smaxims@google.com #reset-cells = <1>; 1314e4b149Smaxims@google.com }; 1414e4b149Smaxims@google.com 15c93adc08Smaxims@google.com rst: reset-controller { 16c93adc08Smaxims@google.com u-boot,dm-pre-reloc; 17c93adc08Smaxims@google.com compatible = "aspeed,ast2500-reset"; 18c93adc08Smaxims@google.com aspeed,wdt = <&wdt1>; 19c93adc08Smaxims@google.com #reset-cells = <1>; 20c93adc08Smaxims@google.com }; 21c93adc08Smaxims@google.com 2214e4b149Smaxims@google.com sdrammc: sdrammc@1e6e0000 { 2314e4b149Smaxims@google.com u-boot,dm-pre-reloc; 2414e4b149Smaxims@google.com compatible = "aspeed,ast2500-sdrammc"; 2514e4b149Smaxims@google.com reg = <0x1e6e0000 0x174 2614e4b149Smaxims@google.com 0x1e6e0200 0x1d4 >; 27c93adc08Smaxims@google.com #reset-cells = <1>; 28f0d895afSryan_chen clocks = <&scu ASPEED_CLK_MPLL>; 29*39283ea7Sryan_chen resets = <&rst ASPEED_RESET_SDRAM>; 3014e4b149Smaxims@google.com }; 3114e4b149Smaxims@google.com 3214e4b149Smaxims@google.com ahb { 3314e4b149Smaxims@google.com u-boot,dm-pre-reloc; 3414e4b149Smaxims@google.com 3514e4b149Smaxims@google.com apb { 3614e4b149Smaxims@google.com u-boot,dm-pre-reloc; 3714e4b149Smaxims@google.com }; 3814e4b149Smaxims@google.com 39d5c16d00Smaxims@google.com }; 40d5c16d00Smaxims@google.com}; 41d5c16d00Smaxims@google.com 42d5c16d00Smaxims@google.com&timer { 43d5c16d00Smaxims@google.com u-boot,dm-pre-reloc; 4414e4b149Smaxims@google.com}; 45