1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-defs.h" 27 #include "qemu/cpu-float.h" 28 #include "qom/object.h" 29 #include "qemu/int128.h" 30 #include "cpu_bits.h" 31 #include "cpu_cfg.h" 32 #include "qapi/qapi-types-common.h" 33 #include "cpu-qom.h" 34 35 #define TCG_GUEST_DEFAULT_MO 0 36 37 /* 38 * RISC-V-specific extra insn start words: 39 * 1: Original instruction opcode 40 */ 41 #define TARGET_INSN_START_EXTRA_WORDS 1 42 43 #define RV(x) ((target_ulong)1 << (x - 'A')) 44 45 /* 46 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 47 * when adding new MISA bits here. 48 */ 49 #define RVI RV('I') 50 #define RVE RV('E') /* E and I are mutually exclusive */ 51 #define RVM RV('M') 52 #define RVA RV('A') 53 #define RVF RV('F') 54 #define RVD RV('D') 55 #define RVV RV('V') 56 #define RVC RV('C') 57 #define RVS RV('S') 58 #define RVU RV('U') 59 #define RVH RV('H') 60 #define RVJ RV('J') 61 #define RVG RV('G') 62 63 extern const uint32_t misa_bits[]; 64 const char *riscv_get_misa_ext_name(uint32_t bit); 65 const char *riscv_get_misa_ext_description(uint32_t bit); 66 67 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 68 69 /* Privileged specification version */ 70 enum { 71 PRIV_VERSION_1_10_0 = 0, 72 PRIV_VERSION_1_11_0, 73 PRIV_VERSION_1_12_0, 74 75 PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, 76 }; 77 78 #define VEXT_VERSION_1_00_0 0x00010000 79 80 enum { 81 TRANSLATE_SUCCESS, 82 TRANSLATE_FAIL, 83 TRANSLATE_PMP_FAIL, 84 TRANSLATE_G_STAGE_FAIL 85 }; 86 87 /* Extension context status */ 88 typedef enum { 89 EXT_STATUS_DISABLED = 0, 90 EXT_STATUS_INITIAL, 91 EXT_STATUS_CLEAN, 92 EXT_STATUS_DIRTY, 93 } RISCVExtStatus; 94 95 #define MMU_USER_IDX 3 96 97 #define MAX_RISCV_PMPS (16) 98 99 #if !defined(CONFIG_USER_ONLY) 100 #include "pmp.h" 101 #include "debug.h" 102 #endif 103 104 #define RV_VLEN_MAX 1024 105 #define RV_MAX_MHPMEVENTS 32 106 #define RV_MAX_MHPMCOUNTERS 32 107 108 FIELD(VTYPE, VLMUL, 0, 3) 109 FIELD(VTYPE, VSEW, 3, 3) 110 FIELD(VTYPE, VTA, 6, 1) 111 FIELD(VTYPE, VMA, 7, 1) 112 FIELD(VTYPE, VEDIV, 8, 2) 113 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 114 115 typedef struct PMUCTRState { 116 /* Current value of a counter */ 117 target_ulong mhpmcounter_val; 118 /* Current value of a counter in RV32 */ 119 target_ulong mhpmcounterh_val; 120 /* Snapshot values of counter */ 121 target_ulong mhpmcounter_prev; 122 /* Snapshort value of a counter in RV32 */ 123 target_ulong mhpmcounterh_prev; 124 bool started; 125 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 126 target_ulong irq_overflow_left; 127 } PMUCTRState; 128 129 struct CPUArchState { 130 target_ulong gpr[32]; 131 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 132 133 /* vector coprocessor state. */ 134 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 135 target_ulong vxrm; 136 target_ulong vxsat; 137 target_ulong vl; 138 target_ulong vstart; 139 target_ulong vtype; 140 bool vill; 141 142 target_ulong pc; 143 target_ulong load_res; 144 target_ulong load_val; 145 146 /* Floating-Point state */ 147 uint64_t fpr[32]; /* assume both F and D extensions */ 148 target_ulong frm; 149 float_status fp_status; 150 151 target_ulong badaddr; 152 target_ulong bins; 153 154 target_ulong guest_phys_fault_addr; 155 156 target_ulong priv_ver; 157 target_ulong bext_ver; 158 target_ulong vext_ver; 159 160 /* RISCVMXL, but uint32_t for vmstate migration */ 161 uint32_t misa_mxl; /* current mxl */ 162 uint32_t misa_mxl_max; /* max mxl for this cpu */ 163 uint32_t misa_ext; /* current extensions */ 164 uint32_t misa_ext_mask; /* max ext for this cpu */ 165 uint32_t xl; /* current xlen */ 166 167 /* 128-bit helpers upper part return value */ 168 target_ulong retxh; 169 170 target_ulong jvt; 171 172 #ifdef CONFIG_USER_ONLY 173 uint32_t elf_flags; 174 #endif 175 176 #ifndef CONFIG_USER_ONLY 177 target_ulong priv; 178 /* This contains QEMU specific information about the virt state. */ 179 bool virt_enabled; 180 target_ulong geilen; 181 uint64_t resetvec; 182 183 target_ulong mhartid; 184 /* 185 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 186 * For RV64 this is a 64-bit mstatus. 187 */ 188 uint64_t mstatus; 189 190 uint64_t mip; 191 /* 192 * MIP contains the software writable version of SEIP ORed with the 193 * external interrupt value. The MIP register is always up-to-date. 194 * To keep track of the current source, we also save booleans of the values 195 * here. 196 */ 197 bool external_seip; 198 bool software_seip; 199 200 uint64_t miclaim; 201 202 uint64_t mie; 203 uint64_t mideleg; 204 205 /* 206 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 207 * alias of mie[i] and needs to be maintained separatly. 208 */ 209 uint64_t sie; 210 211 /* 212 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 213 * alias of sie[i] (mie[i]) and needs to be maintained separatly. 214 */ 215 uint64_t vsie; 216 217 target_ulong satp; /* since: priv-1.10.0 */ 218 target_ulong stval; 219 target_ulong medeleg; 220 221 target_ulong stvec; 222 target_ulong sepc; 223 target_ulong scause; 224 225 target_ulong mtvec; 226 target_ulong mepc; 227 target_ulong mcause; 228 target_ulong mtval; /* since: priv-1.10.0 */ 229 230 /* Machine and Supervisor interrupt priorities */ 231 uint8_t miprio[64]; 232 uint8_t siprio[64]; 233 234 /* AIA CSRs */ 235 target_ulong miselect; 236 target_ulong siselect; 237 uint64_t mvien; 238 uint64_t mvip; 239 240 /* Hypervisor CSRs */ 241 target_ulong hstatus; 242 target_ulong hedeleg; 243 uint64_t hideleg; 244 target_ulong hcounteren; 245 target_ulong htval; 246 target_ulong htinst; 247 target_ulong hgatp; 248 target_ulong hgeie; 249 target_ulong hgeip; 250 uint64_t htimedelta; 251 uint64_t hvien; 252 253 /* 254 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 255 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 256 * maintain in hvip. 257 */ 258 uint64_t hvip; 259 260 /* Hypervisor controlled virtual interrupt priorities */ 261 target_ulong hvictl; 262 uint8_t hviprio[64]; 263 264 /* Upper 64-bits of 128-bit CSRs */ 265 uint64_t mscratchh; 266 uint64_t sscratchh; 267 268 /* Virtual CSRs */ 269 /* 270 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 271 * For RV64 this is a 64-bit vsstatus. 272 */ 273 uint64_t vsstatus; 274 target_ulong vstvec; 275 target_ulong vsscratch; 276 target_ulong vsepc; 277 target_ulong vscause; 278 target_ulong vstval; 279 target_ulong vsatp; 280 281 /* AIA VS-mode CSRs */ 282 target_ulong vsiselect; 283 284 target_ulong mtval2; 285 target_ulong mtinst; 286 287 /* HS Backup CSRs */ 288 target_ulong stvec_hs; 289 target_ulong sscratch_hs; 290 target_ulong sepc_hs; 291 target_ulong scause_hs; 292 target_ulong stval_hs; 293 target_ulong satp_hs; 294 uint64_t mstatus_hs; 295 296 /* 297 * Signals whether the current exception occurred with two-stage address 298 * translation active. 299 */ 300 bool two_stage_lookup; 301 /* 302 * Signals whether the current exception occurred while doing two-stage 303 * address translation for the VS-stage page table walk. 304 */ 305 bool two_stage_indirect_lookup; 306 307 target_ulong scounteren; 308 target_ulong mcounteren; 309 310 target_ulong mcountinhibit; 311 312 /* PMU counter state */ 313 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 314 315 /* PMU event selector configured values. First three are unused */ 316 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 317 318 /* PMU event selector configured values for RV32 */ 319 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 320 321 target_ulong sscratch; 322 target_ulong mscratch; 323 324 /* Sstc CSRs */ 325 uint64_t stimecmp; 326 327 uint64_t vstimecmp; 328 329 /* physical memory protection */ 330 pmp_table_t pmp_state; 331 target_ulong mseccfg; 332 333 /* trigger module */ 334 target_ulong trigger_cur; 335 target_ulong tdata1[RV_MAX_TRIGGERS]; 336 target_ulong tdata2[RV_MAX_TRIGGERS]; 337 target_ulong tdata3[RV_MAX_TRIGGERS]; 338 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 339 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 340 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 341 int64_t last_icount; 342 bool itrigger_enabled; 343 344 /* machine specific rdtime callback */ 345 uint64_t (*rdtime_fn)(void *); 346 void *rdtime_fn_arg; 347 348 /* machine specific AIA ireg read-modify-write callback */ 349 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 350 ((((__xlen) & 0xff) << 24) | \ 351 (((__vgein) & 0x3f) << 20) | \ 352 (((__virt) & 0x1) << 18) | \ 353 (((__priv) & 0x3) << 16) | \ 354 (__isel & 0xffff)) 355 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 356 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 357 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 358 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 359 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 360 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 361 target_ulong *val, target_ulong new_val, target_ulong write_mask); 362 void *aia_ireg_rmw_fn_arg[4]; 363 364 /* True if in debugger mode. */ 365 bool debugger; 366 367 /* 368 * CSRs for PointerMasking extension 369 */ 370 target_ulong mmte; 371 target_ulong mpmmask; 372 target_ulong mpmbase; 373 target_ulong spmmask; 374 target_ulong spmbase; 375 target_ulong upmmask; 376 target_ulong upmbase; 377 378 /* CSRs for execution environment configuration */ 379 uint64_t menvcfg; 380 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 381 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 382 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 383 target_ulong senvcfg; 384 uint64_t henvcfg; 385 #endif 386 target_ulong cur_pmmask; 387 target_ulong cur_pmbase; 388 389 /* Fields from here on are preserved across CPU reset. */ 390 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 391 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 392 bool vstime_irq; 393 394 hwaddr kernel_addr; 395 hwaddr fdt_addr; 396 397 #ifdef CONFIG_KVM 398 /* kvm timer */ 399 bool kvm_timer_dirty; 400 uint64_t kvm_timer_time; 401 uint64_t kvm_timer_compare; 402 uint64_t kvm_timer_state; 403 uint64_t kvm_timer_frequency; 404 #endif /* CONFIG_KVM */ 405 }; 406 407 /* 408 * RISCVCPU: 409 * @env: #CPURISCVState 410 * 411 * A RISCV CPU. 412 */ 413 struct ArchCPU { 414 CPUState parent_obj; 415 416 CPURISCVState env; 417 418 char *dyn_csr_xml; 419 char *dyn_vreg_xml; 420 421 /* Configuration Settings */ 422 RISCVCPUConfig cfg; 423 424 QEMUTimer *pmu_timer; 425 /* A bitmask of Available programmable counters */ 426 uint32_t pmu_avail_ctrs; 427 /* Mapping of events to counters */ 428 GHashTable *pmu_event_ctr_map; 429 }; 430 431 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 432 { 433 return (env->misa_ext & ext) != 0; 434 } 435 436 #include "cpu_user.h" 437 438 extern const char * const riscv_int_regnames[]; 439 extern const char * const riscv_int_regnamesh[]; 440 extern const char * const riscv_fpr_regnames[]; 441 442 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 443 void riscv_cpu_do_interrupt(CPUState *cpu); 444 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 445 int cpuid, DumpState *s); 446 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 447 int cpuid, DumpState *s); 448 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 449 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 450 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 451 uint8_t riscv_cpu_default_priority(int irq); 452 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 453 int riscv_cpu_mirq_pending(CPURISCVState *env); 454 int riscv_cpu_sirq_pending(CPURISCVState *env); 455 int riscv_cpu_vsirq_pending(CPURISCVState *env); 456 bool riscv_cpu_fp_enabled(CPURISCVState *env); 457 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 458 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 459 bool riscv_cpu_vector_enabled(CPURISCVState *env); 460 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 461 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 462 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 463 MMUAccessType access_type, 464 int mmu_idx, uintptr_t retaddr); 465 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 466 MMUAccessType access_type, int mmu_idx, 467 bool probe, uintptr_t retaddr); 468 char *riscv_isa_string(RISCVCPU *cpu); 469 void riscv_cpu_list(void); 470 471 #define cpu_list riscv_cpu_list 472 #define cpu_mmu_index riscv_cpu_mmu_index 473 474 #ifndef CONFIG_USER_ONLY 475 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 476 vaddr addr, unsigned size, 477 MMUAccessType access_type, 478 int mmu_idx, MemTxAttrs attrs, 479 MemTxResult response, uintptr_t retaddr); 480 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 481 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 482 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 483 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 484 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 485 uint64_t value); 486 void riscv_cpu_interrupt(CPURISCVState *env); 487 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 488 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 489 void *arg); 490 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 491 int (*rmw_fn)(void *arg, 492 target_ulong reg, 493 target_ulong *val, 494 target_ulong new_val, 495 target_ulong write_mask), 496 void *rmw_fn_arg); 497 498 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 499 #endif 500 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 501 502 void riscv_translate_init(void); 503 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 504 uint32_t exception, uintptr_t pc); 505 506 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 507 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 508 509 #include "exec/cpu-all.h" 510 511 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 512 FIELD(TB_FLAGS, FS, 3, 2) 513 /* Vector flags */ 514 FIELD(TB_FLAGS, VS, 5, 2) 515 FIELD(TB_FLAGS, LMUL, 7, 3) 516 FIELD(TB_FLAGS, SEW, 10, 3) 517 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 518 FIELD(TB_FLAGS, VILL, 14, 1) 519 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 520 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 521 FIELD(TB_FLAGS, XL, 16, 2) 522 /* If PointerMasking should be applied */ 523 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 524 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 525 FIELD(TB_FLAGS, VTA, 20, 1) 526 FIELD(TB_FLAGS, VMA, 21, 1) 527 /* Native debug itrigger */ 528 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 529 /* Virtual mode enabled */ 530 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 531 FIELD(TB_FLAGS, PRIV, 24, 2) 532 FIELD(TB_FLAGS, AXL, 26, 2) 533 534 #ifdef TARGET_RISCV32 535 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 536 #else 537 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 538 { 539 return env->misa_mxl; 540 } 541 #endif 542 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 543 544 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 545 { 546 return &env_archcpu(env)->cfg; 547 } 548 549 #if !defined(CONFIG_USER_ONLY) 550 static inline int cpu_address_mode(CPURISCVState *env) 551 { 552 int mode = env->priv; 553 554 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 555 mode = get_field(env->mstatus, MSTATUS_MPP); 556 } 557 return mode; 558 } 559 560 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 561 { 562 RISCVMXL xl = env->misa_mxl; 563 /* 564 * When emulating a 32-bit-only cpu, use RV32. 565 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 566 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 567 * back to RV64 for lower privs. 568 */ 569 if (xl != MXL_RV32) { 570 switch (mode) { 571 case PRV_M: 572 break; 573 case PRV_U: 574 xl = get_field(env->mstatus, MSTATUS64_UXL); 575 break; 576 default: /* PRV_S */ 577 xl = get_field(env->mstatus, MSTATUS64_SXL); 578 break; 579 } 580 } 581 return xl; 582 } 583 #endif 584 585 #if defined(TARGET_RISCV32) 586 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 587 #else 588 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 589 { 590 #if !defined(CONFIG_USER_ONLY) 591 return cpu_get_xl(env, env->priv); 592 #else 593 return env->misa_mxl; 594 #endif 595 } 596 #endif 597 598 #if defined(TARGET_RISCV32) 599 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 600 #else 601 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 602 { 603 #ifdef CONFIG_USER_ONLY 604 return env->xl; 605 #else 606 int mode = cpu_address_mode(env); 607 608 return cpu_get_xl(env, mode); 609 #endif 610 } 611 #endif 612 613 static inline int riscv_cpu_xlen(CPURISCVState *env) 614 { 615 return 16 << env->xl; 616 } 617 618 #ifdef TARGET_RISCV32 619 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 620 #else 621 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 622 { 623 #ifdef CONFIG_USER_ONLY 624 return env->misa_mxl; 625 #else 626 return get_field(env->mstatus, MSTATUS64_SXL); 627 #endif 628 } 629 #endif 630 631 /* 632 * Encode LMUL to lmul as follows: 633 * LMUL vlmul lmul 634 * 1 000 0 635 * 2 001 1 636 * 4 010 2 637 * 8 011 3 638 * - 100 - 639 * 1/8 101 -3 640 * 1/4 110 -2 641 * 1/2 111 -1 642 * 643 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 644 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 645 * => VLMAX = vlen >> (1 + 3 - (-3)) 646 * = 256 >> 7 647 * = 2 648 */ 649 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 650 { 651 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 652 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 653 return cpu->cfg.vlen >> (sew + 3 - lmul); 654 } 655 656 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 657 uint64_t *cs_base, uint32_t *pflags); 658 659 void riscv_cpu_update_mask(CPURISCVState *env); 660 661 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 662 target_ulong *ret_value, 663 target_ulong new_value, target_ulong write_mask); 664 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 665 target_ulong *ret_value, 666 target_ulong new_value, 667 target_ulong write_mask); 668 669 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 670 target_ulong val) 671 { 672 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 673 } 674 675 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 676 { 677 target_ulong val = 0; 678 riscv_csrrw(env, csrno, &val, 0, 0); 679 return val; 680 } 681 682 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 683 int csrno); 684 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 685 target_ulong *ret_value); 686 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 687 target_ulong new_value); 688 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 689 target_ulong *ret_value, 690 target_ulong new_value, 691 target_ulong write_mask); 692 693 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 694 Int128 *ret_value, 695 Int128 new_value, Int128 write_mask); 696 697 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 698 Int128 *ret_value); 699 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 700 Int128 new_value); 701 702 typedef struct { 703 const char *name; 704 riscv_csr_predicate_fn predicate; 705 riscv_csr_read_fn read; 706 riscv_csr_write_fn write; 707 riscv_csr_op_fn op; 708 riscv_csr_read128_fn read128; 709 riscv_csr_write128_fn write128; 710 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 711 uint32_t min_priv_ver; 712 } riscv_csr_operations; 713 714 /* CSR function table constants */ 715 enum { 716 CSR_TABLE_SIZE = 0x1000 717 }; 718 719 /* 720 * The event id are encoded based on the encoding specified in the 721 * SBI specification v0.3 722 */ 723 724 enum riscv_pmu_event_idx { 725 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 726 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 727 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 728 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 729 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 730 }; 731 732 /* used by tcg/tcg-cpu.c*/ 733 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 734 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 735 void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); 736 737 typedef struct RISCVCPUMultiExtConfig { 738 const char *name; 739 uint32_t offset; 740 bool enabled; 741 } RISCVCPUMultiExtConfig; 742 743 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 744 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 745 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 746 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 747 extern Property riscv_cpu_options[]; 748 749 typedef struct isa_ext_data { 750 const char *name; 751 int min_version; 752 int ext_enable_offset; 753 } RISCVIsaExtData; 754 extern const RISCVIsaExtData isa_edata_arr[]; 755 char *riscv_cpu_get_name(RISCVCPU *cpu); 756 757 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 758 void riscv_add_satp_mode_properties(Object *obj); 759 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 760 761 /* CSR function table */ 762 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 763 764 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 765 766 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 767 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 768 769 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 770 771 uint8_t satp_mode_max_from_map(uint32_t map); 772 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 773 774 #endif /* RISCV_CPU_H */ 775