1 #ifndef TARGET_ARM_TRANSLATE_H 2 #define TARGET_ARM_TRANSLATE_H 3 4 #include "exec/translator.h" 5 #include "exec/helper-gen.h" 6 #include "internals.h" 7 8 9 /* internal defines */ 10 11 /* 12 * Save pc_save across a branch, so that we may restore the value from 13 * before the branch at the point the label is emitted. 14 */ 15 typedef struct DisasLabel { 16 TCGLabel *label; 17 target_ulong pc_save; 18 } DisasLabel; 19 20 typedef struct DisasContext { 21 DisasContextBase base; 22 const ARMISARegisters *isar; 23 24 /* The address of the current instruction being translated. */ 25 target_ulong pc_curr; 26 /* 27 * For CF_PCREL, the full value of cpu_pc is not known 28 * (although the page offset is known). For convenience, the 29 * translation loop uses the full virtual address that triggered 30 * the translation, from base.pc_start through pc_curr. 31 * For efficiency, we do not update cpu_pc for every instruction. 32 * Instead, pc_save has the value of pc_curr at the time of the 33 * last update to cpu_pc, which allows us to compute the addend 34 * needed to bring cpu_pc current: pc_curr - pc_save. 35 * If cpu_pc now contains the destination of an indirect branch, 36 * pc_save contains -1 to indicate that relative updates are no 37 * longer possible. 38 */ 39 target_ulong pc_save; 40 target_ulong page_start; 41 uint32_t insn; 42 /* Nonzero if this instruction has been conditionally skipped. */ 43 int condjmp; 44 /* The label that will be jumped to when the instruction is skipped. */ 45 DisasLabel condlabel; 46 /* Thumb-2 conditional execution bits. */ 47 int condexec_mask; 48 int condexec_cond; 49 /* M-profile ECI/ICI exception-continuable instruction state */ 50 int eci; 51 /* 52 * trans_ functions for insns which are continuable should set this true 53 * after decode (ie after any UNDEF checks) 54 */ 55 bool eci_handled; 56 int sctlr_b; 57 MemOp be_data; 58 #if !defined(CONFIG_USER_ONLY) 59 int user; 60 #endif 61 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ 62 uint8_t tbii; /* TBI1|TBI0 for insns */ 63 uint8_t tbid; /* TBI1|TBI0 for data */ 64 uint8_t tcma; /* TCMA1|TCMA0 for MTE */ 65 bool ns; /* Use non-secure CPREG bank on access */ 66 int fp_excp_el; /* FP exception EL or 0 if enabled */ 67 int sve_excp_el; /* SVE exception EL or 0 if enabled */ 68 int sme_excp_el; /* SME exception EL or 0 if enabled */ 69 int vl; /* current vector length in bytes */ 70 int svl; /* current streaming vector length in bytes */ 71 bool vfp_enabled; /* FP enabled via FPSCR.EN */ 72 int vec_len; 73 int vec_stride; 74 bool v7m_handler_mode; 75 bool v8m_secure; /* true if v8M and we're in Secure mode */ 76 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ 77 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ 78 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ 79 bool v7m_lspact; /* FPCCR.LSPACT set */ 80 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI 81 * so that top level loop can generate correct syndrome information. 82 */ 83 uint32_t svc_imm; 84 int current_el; 85 GHashTable *cp_regs; 86 uint64_t features; /* CPU features bits */ 87 bool aarch64; 88 bool thumb; 89 /* Because unallocated encodings generate different exception syndrome 90 * information from traps due to FP being disabled, we can't do a single 91 * "is fp access disabled" check at a high level in the decode tree. 92 * To help in catching bugs where the access check was forgotten in some 93 * code path, we set this flag when the access check is done, and assert 94 * that it is set at the point where we actually touch the FP regs. 95 */ 96 bool fp_access_checked; 97 bool sve_access_checked; 98 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub 99 * single-step support). 100 */ 101 bool ss_active; 102 bool pstate_ss; 103 /* True if the insn just emitted was a load-exclusive instruction 104 * (necessary for syndrome information for single step exceptions), 105 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. 106 */ 107 bool is_ldex; 108 /* True if AccType_UNPRIV should be used for LDTR et al */ 109 bool unpriv; 110 /* True if v8.3-PAuth is active. */ 111 bool pauth_active; 112 /* True if v8.5-MTE access to tags is enabled. */ 113 bool ata; 114 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ 115 bool mte_active[2]; 116 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ 117 bool bt; 118 /* True if any CP15 access is trapped by HSTR_EL2 */ 119 bool hstr_active; 120 /* True if memory operations require alignment */ 121 bool align_mem; 122 /* True if PSTATE.IL is set */ 123 bool pstate_il; 124 /* True if PSTATE.SM is set. */ 125 bool pstate_sm; 126 /* True if PSTATE.ZA is set. */ 127 bool pstate_za; 128 /* True if non-streaming insns should raise an SME Streaming exception. */ 129 bool sme_trap_nonstreaming; 130 /* True if the current instruction is non-streaming. */ 131 bool is_nonstreaming; 132 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ 133 bool mve_no_pred; 134 /* True if fine-grained traps are active */ 135 bool fgt_active; 136 /* True if fine-grained trap on ERET is enabled */ 137 bool fgt_eret; 138 /* True if fine-grained trap on SVC is enabled */ 139 bool fgt_svc; 140 /* 141 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. 142 * < 0, set by the current instruction. 143 */ 144 int8_t btype; 145 /* A copy of cpu->dcz_blocksize. */ 146 uint8_t dcz_blocksize; 147 /* True if this page is guarded. */ 148 bool guarded_page; 149 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ 150 int c15_cpar; 151 /* TCG op of the current insn_start. */ 152 TCGOp *insn_start; 153 } DisasContext; 154 155 typedef struct DisasCompare { 156 TCGCond cond; 157 TCGv_i32 value; 158 } DisasCompare; 159 160 /* Share the TCG temporaries common between 32 and 64 bit modes. */ 161 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; 162 extern TCGv_i64 cpu_exclusive_addr; 163 extern TCGv_i64 cpu_exclusive_val; 164 165 /* 166 * Constant expanders for the decoders. 167 */ 168 169 static inline int negate(DisasContext *s, int x) 170 { 171 return -x; 172 } 173 174 static inline int plus_1(DisasContext *s, int x) 175 { 176 return x + 1; 177 } 178 179 static inline int plus_2(DisasContext *s, int x) 180 { 181 return x + 2; 182 } 183 184 static inline int plus_12(DisasContext *s, int x) 185 { 186 return x + 12; 187 } 188 189 static inline int times_2(DisasContext *s, int x) 190 { 191 return x * 2; 192 } 193 194 static inline int times_4(DisasContext *s, int x) 195 { 196 return x * 4; 197 } 198 199 static inline int times_2_plus_1(DisasContext *s, int x) 200 { 201 return x * 2 + 1; 202 } 203 204 static inline int rsub_64(DisasContext *s, int x) 205 { 206 return 64 - x; 207 } 208 209 static inline int rsub_32(DisasContext *s, int x) 210 { 211 return 32 - x; 212 } 213 214 static inline int rsub_16(DisasContext *s, int x) 215 { 216 return 16 - x; 217 } 218 219 static inline int rsub_8(DisasContext *s, int x) 220 { 221 return 8 - x; 222 } 223 224 static inline int shl_12(DisasContext *s, int x) 225 { 226 return x << 12; 227 } 228 229 static inline int neon_3same_fp_size(DisasContext *s, int x) 230 { 231 /* Convert 0==fp32, 1==fp16 into a MO_* value */ 232 return MO_32 - x; 233 } 234 235 static inline int arm_dc_feature(DisasContext *dc, int feature) 236 { 237 return (dc->features & (1ULL << feature)) != 0; 238 } 239 240 static inline int get_mem_index(DisasContext *s) 241 { 242 return arm_to_core_mmu_idx(s->mmu_idx); 243 } 244 245 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) 246 { 247 /* We don't need to save all of the syndrome so we mask and shift 248 * out unneeded bits to help the sleb128 encoder do a better job. 249 */ 250 syn &= ARM_INSN_START_WORD2_MASK; 251 syn >>= ARM_INSN_START_WORD2_SHIFT; 252 253 /* We check and clear insn_start_idx to catch multiple updates. */ 254 assert(s->insn_start != NULL); 255 tcg_set_insn_start_param(s->insn_start, 2, syn); 256 s->insn_start = NULL; 257 } 258 259 static inline int curr_insn_len(DisasContext *s) 260 { 261 return s->base.pc_next - s->pc_curr; 262 } 263 264 /* is_jmp field values */ 265 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 266 /* CPU state was modified dynamically; exit to main loop for interrupts. */ 267 #define DISAS_UPDATE_EXIT DISAS_TARGET_1 268 /* These instructions trap after executing, so the A32/T32 decoder must 269 * defer them until after the conditional execution state has been updated. 270 * WFI also needs special handling when single-stepping. 271 */ 272 #define DISAS_WFI DISAS_TARGET_2 273 #define DISAS_SWI DISAS_TARGET_3 274 /* WFE */ 275 #define DISAS_WFE DISAS_TARGET_4 276 #define DISAS_HVC DISAS_TARGET_5 277 #define DISAS_SMC DISAS_TARGET_6 278 #define DISAS_YIELD DISAS_TARGET_7 279 /* M profile branch which might be an exception return (and so needs 280 * custom end-of-TB code) 281 */ 282 #define DISAS_BX_EXCRET DISAS_TARGET_8 283 /* 284 * For instructions which want an immediate exit to the main loop, as opposed 285 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this 286 * doesn't write the PC on exiting the translation loop so you need to ensure 287 * something (gen_a64_update_pc or runtime helper) has done so before we reach 288 * return from cpu_tb_exec. 289 */ 290 #define DISAS_EXIT DISAS_TARGET_9 291 /* CPU state was modified dynamically; no need to exit, but do not chain. */ 292 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 293 294 #ifdef TARGET_AARCH64 295 void a64_translate_init(void); 296 void gen_a64_update_pc(DisasContext *s, target_long diff); 297 extern const TranslatorOps aarch64_translator_ops; 298 #else 299 static inline void a64_translate_init(void) 300 { 301 } 302 303 static inline void gen_a64_update_pc(DisasContext *s, target_long diff) 304 { 305 } 306 #endif 307 308 void arm_test_cc(DisasCompare *cmp, int cc); 309 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); 310 void arm_gen_test_cc(int cc, TCGLabel *label); 311 MemOp pow2_align(unsigned i); 312 void unallocated_encoding(DisasContext *s); 313 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, 314 uint32_t syn, uint32_t target_el); 315 void gen_exception_insn(DisasContext *s, target_long pc_diff, 316 int excp, uint32_t syn); 317 318 /* Return state of Alternate Half-precision flag, caller frees result */ 319 static inline TCGv_i32 get_ahp_flag(void) 320 { 321 TCGv_i32 ret = tcg_temp_new_i32(); 322 323 tcg_gen_ld_i32(ret, cpu_env, 324 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); 325 tcg_gen_extract_i32(ret, ret, 26, 1); 326 327 return ret; 328 } 329 330 /* Set bits within PSTATE. */ 331 static inline void set_pstate_bits(uint32_t bits) 332 { 333 TCGv_i32 p = tcg_temp_new_i32(); 334 335 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 336 337 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 338 tcg_gen_ori_i32(p, p, bits); 339 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 340 } 341 342 /* Clear bits within PSTATE. */ 343 static inline void clear_pstate_bits(uint32_t bits) 344 { 345 TCGv_i32 p = tcg_temp_new_i32(); 346 347 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 348 349 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 350 tcg_gen_andi_i32(p, p, ~bits); 351 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 352 } 353 354 /* If the singlestep state is Active-not-pending, advance to Active-pending. */ 355 static inline void gen_ss_advance(DisasContext *s) 356 { 357 if (s->ss_active) { 358 s->pstate_ss = 0; 359 clear_pstate_bits(PSTATE_SS); 360 } 361 } 362 363 /* Generate an architectural singlestep exception */ 364 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) 365 { 366 /* Fill in the same_el field of the syndrome in the helper. */ 367 uint32_t syn = syn_swstep(false, isv, ex); 368 gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); 369 } 370 371 /* 372 * Given a VFP floating point constant encoded into an 8 bit immediate in an 373 * instruction, expand it to the actual constant value of the specified 374 * size, as per the VFPExpandImm() pseudocode in the Arm ARM. 375 */ 376 uint64_t vfp_expand_imm(int size, uint8_t imm8); 377 378 /* Vector operations shared between ARM and AArch64. */ 379 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 380 uint32_t opr_sz, uint32_t max_sz); 381 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 382 uint32_t opr_sz, uint32_t max_sz); 383 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 384 uint32_t opr_sz, uint32_t max_sz); 385 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 386 uint32_t opr_sz, uint32_t max_sz); 387 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 388 uint32_t opr_sz, uint32_t max_sz); 389 390 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 391 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 392 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 393 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 394 395 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 396 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 397 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 398 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 399 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 400 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 401 402 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 403 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 404 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 405 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 406 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 407 408 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 409 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 410 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 411 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 412 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 413 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 414 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 415 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 416 417 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 418 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 419 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 420 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 421 422 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 423 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 424 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 425 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 426 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 427 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 428 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 429 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 430 431 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 432 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 433 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 434 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 435 436 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 437 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 438 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 439 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 440 441 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 442 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 443 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 444 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 445 446 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 447 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 448 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 449 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 450 451 /* 452 * Forward to the isar_feature_* tests given a DisasContext pointer. 453 */ 454 #define dc_isar_feature(name, ctx) \ 455 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) 456 457 /* Note that the gvec expanders operate on offsets + sizes. */ 458 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); 459 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, 460 uint32_t, uint32_t); 461 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, 462 uint32_t, uint32_t, uint32_t); 463 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, 464 uint32_t, uint32_t, uint32_t); 465 466 /* Function prototype for gen_ functions for calling Neon helpers */ 467 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); 468 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); 469 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); 470 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 471 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, 472 TCGv_i32, TCGv_i32); 473 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); 474 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); 475 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); 476 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); 477 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); 478 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); 479 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); 480 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); 481 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); 482 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); 483 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); 484 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 485 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 486 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); 487 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); 488 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); 489 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); 490 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 491 492 /** 493 * arm_tbflags_from_tb: 494 * @tb: the TranslationBlock 495 * 496 * Extract the flag values from @tb. 497 */ 498 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) 499 { 500 return (CPUARMTBFlags){ tb->flags, tb->cs_base }; 501 } 502 503 /* 504 * Enum for argument to fpstatus_ptr(). 505 */ 506 typedef enum ARMFPStatusFlavour { 507 FPST_FPCR, 508 FPST_FPCR_F16, 509 FPST_STD, 510 FPST_STD_F16, 511 } ARMFPStatusFlavour; 512 513 /** 514 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field 515 * 516 * We have multiple softfloat float_status fields in the Arm CPU state struct 517 * (see the comment in cpu.h for details). Return a TCGv_ptr which has 518 * been set up to point to the requested field in the CPU state struct. 519 * The options are: 520 * 521 * FPST_FPCR 522 * for non-FP16 operations controlled by the FPCR 523 * FPST_FPCR_F16 524 * for operations controlled by the FPCR where FPCR.FZ16 is to be used 525 * FPST_STD 526 * for A32/T32 Neon operations using the "standard FPSCR value" 527 * FPST_STD_F16 528 * as FPST_STD, but where FPCR.FZ16 is to be used 529 */ 530 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) 531 { 532 TCGv_ptr statusptr = tcg_temp_new_ptr(); 533 int offset; 534 535 switch (flavour) { 536 case FPST_FPCR: 537 offset = offsetof(CPUARMState, vfp.fp_status); 538 break; 539 case FPST_FPCR_F16: 540 offset = offsetof(CPUARMState, vfp.fp_status_f16); 541 break; 542 case FPST_STD: 543 offset = offsetof(CPUARMState, vfp.standard_fp_status); 544 break; 545 case FPST_STD_F16: 546 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16); 547 break; 548 default: 549 g_assert_not_reached(); 550 } 551 tcg_gen_addi_ptr(statusptr, cpu_env, offset); 552 return statusptr; 553 } 554 555 /** 556 * finalize_memop: 557 * @s: DisasContext 558 * @opc: size+sign+align of the memory operation 559 * 560 * Build the complete MemOp for a memory operation, including alignment 561 * and endianness. 562 * 563 * If (op & MO_AMASK) then the operation already contains the required 564 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally 565 * unaligned operation, e.g. for AccType_NORMAL. 566 * 567 * In the latter case, there are configuration bits that require alignment, 568 * and this is applied here. Note that there is no way to indicate that 569 * no alignment should ever be enforced; this must be handled manually. 570 */ 571 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) 572 { 573 if (s->align_mem && !(opc & MO_AMASK)) { 574 opc |= MO_ALIGN; 575 } 576 return opc | s->be_data; 577 } 578 579 /** 580 * asimd_imm_const: Expand an encoded SIMD constant value 581 * 582 * Expand a SIMD constant value. This is essentially the pseudocode 583 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for 584 * VMVN and VBIC (when cmode < 14 && op == 1). 585 * 586 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; 587 * callers must catch this; we return the 64-bit constant value defined 588 * for AArch64. 589 * 590 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but 591 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; 592 * we produce an immediate constant value of 0 in these cases. 593 */ 594 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); 595 596 /* 597 * gen_disas_label: 598 * Create a label and cache a copy of pc_save. 599 */ 600 static inline DisasLabel gen_disas_label(DisasContext *s) 601 { 602 return (DisasLabel){ 603 .label = gen_new_label(), 604 .pc_save = s->pc_save, 605 }; 606 } 607 608 /* 609 * set_disas_label: 610 * Emit a label and restore the cached copy of pc_save. 611 */ 612 static inline void set_disas_label(DisasContext *s, DisasLabel l) 613 { 614 gen_set_label(l.label); 615 s->pc_save = l.pc_save; 616 } 617 618 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) 619 { 620 TCGv_ptr ret = tcg_temp_new_ptr(); 621 gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key)); 622 return ret; 623 } 624 625 /* 626 * Set and reset rounding mode around another operation. 627 */ 628 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst) 629 { 630 TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode)); 631 TCGv_i32 old = tcg_temp_new_i32(); 632 633 gen_helper_set_rmode(old, new, fpst); 634 return old; 635 } 636 637 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst) 638 { 639 gen_helper_set_rmode(old, old, fpst); 640 } 641 642 /* 643 * Helpers for implementing sets of trans_* functions. 644 * Defer the implementation of NAME to FUNC, with optional extra arguments. 645 */ 646 #define TRANS(NAME, FUNC, ...) \ 647 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 648 { return FUNC(s, __VA_ARGS__); } 649 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ 650 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 651 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 652 653 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ 654 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 655 { \ 656 s->is_nonstreaming = true; \ 657 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ 658 } 659 660 #endif /* TARGET_ARM_TRANSLATE_H */ 661