1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics 5 * 6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 28 #ifndef XICS_H 29 #define XICS_H 30 31 #include "hw/qdev.h" 32 33 #define XICS_IPI 0x2 34 #define XICS_BUID 0x1 35 #define XICS_IRQ_BASE (XICS_BUID << 12) 36 37 /* 38 * We currently only support one BUID which is our interrupt base 39 * (the kernel implementation supports more but we don't exploit 40 * that yet) 41 */ 42 typedef struct ICPStateClass ICPStateClass; 43 typedef struct ICPState ICPState; 44 typedef struct PnvICPState PnvICPState; 45 typedef struct ICSStateClass ICSStateClass; 46 typedef struct ICSState ICSState; 47 typedef struct ICSIRQState ICSIRQState; 48 typedef struct XICSFabric XICSFabric; 49 50 #define TYPE_ICP "icp" 51 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) 52 53 #define TYPE_PNV_ICP "pnv-icp" 54 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP) 55 56 #define ICP_CLASS(klass) \ 57 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) 58 #define ICP_GET_CLASS(obj) \ 59 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) 60 61 struct ICPStateClass { 62 DeviceClass parent_class; 63 64 DeviceRealize parent_realize; 65 }; 66 67 struct ICPState { 68 /*< private >*/ 69 DeviceState parent_obj; 70 /*< public >*/ 71 CPUState *cs; 72 ICSState *xirr_owner; 73 uint32_t xirr; 74 uint8_t pending_priority; 75 uint8_t mfrr; 76 qemu_irq output; 77 78 XICSFabric *xics; 79 }; 80 81 #define ICP_PROP_XICS "xics" 82 #define ICP_PROP_CPU "cpu" 83 84 struct PnvICPState { 85 ICPState parent_obj; 86 87 MemoryRegion mmio; 88 uint32_t links[3]; 89 }; 90 91 #define TYPE_ICS_BASE "ics-base" 92 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE) 93 94 /* Retain ics for sPAPR for migration from existing sPAPR guests */ 95 #define TYPE_ICS_SIMPLE "ics" 96 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) 97 98 #define TYPE_ICS_KVM "icskvm" 99 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM) 100 101 #define ICS_BASE_CLASS(klass) \ 102 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE) 103 #define ICS_BASE_GET_CLASS(obj) \ 104 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE) 105 106 struct ICSStateClass { 107 DeviceClass parent_class; 108 109 DeviceRealize parent_realize; 110 DeviceReset parent_reset; 111 112 void (*reject)(ICSState *s, uint32_t irq); 113 void (*resend)(ICSState *s); 114 void (*eoi)(ICSState *s, uint32_t irq); 115 }; 116 117 struct ICSState { 118 /*< private >*/ 119 DeviceState parent_obj; 120 /*< public >*/ 121 uint32_t nr_irqs; 122 uint32_t offset; 123 ICSIRQState *irqs; 124 XICSFabric *xics; 125 }; 126 127 #define ICS_PROP_XICS "xics" 128 129 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) 130 { 131 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); 132 } 133 134 struct ICSIRQState { 135 uint32_t server; 136 uint8_t priority; 137 uint8_t saved_priority; 138 #define XICS_STATUS_ASSERTED 0x1 139 #define XICS_STATUS_SENT 0x2 140 #define XICS_STATUS_REJECTED 0x4 141 #define XICS_STATUS_MASKED_PENDING 0x8 142 #define XICS_STATUS_PRESENTED 0x10 143 #define XICS_STATUS_QUEUED 0x20 144 uint8_t status; 145 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */ 146 #define XICS_FLAGS_IRQ_LSI 0x1 147 #define XICS_FLAGS_IRQ_MSI 0x2 148 #define XICS_FLAGS_IRQ_MASK 0x3 149 uint8_t flags; 150 }; 151 152 struct XICSFabric { 153 Object parent; 154 }; 155 156 #define TYPE_XICS_FABRIC "xics-fabric" 157 #define XICS_FABRIC(obj) \ 158 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC) 159 #define XICS_FABRIC_CLASS(klass) \ 160 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC) 161 #define XICS_FABRIC_GET_CLASS(obj) \ 162 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC) 163 164 typedef struct XICSFabricClass { 165 InterfaceClass parent; 166 ICSState *(*ics_get)(XICSFabric *xi, int irq); 167 void (*ics_resend)(XICSFabric *xi); 168 ICPState *(*icp_get)(XICSFabric *xi, int server); 169 } XICSFabricClass; 170 171 ICPState *xics_icp_get(XICSFabric *xi, int server); 172 173 /* Internal XICS interfaces */ 174 void icp_set_cppr(ICPState *icp, uint8_t cppr); 175 void icp_set_mfrr(ICPState *icp, uint8_t mfrr); 176 uint32_t icp_accept(ICPState *ss); 177 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr); 178 void icp_eoi(ICPState *icp, uint32_t xirr); 179 180 void ics_simple_write_xive(ICSState *ics, int nr, int server, 181 uint8_t priority, uint8_t saved_priority); 182 void ics_simple_set_irq(void *opaque, int srcno, int val); 183 void ics_kvm_set_irq(void *opaque, int srcno, int val); 184 185 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); 186 void icp_pic_print_info(ICPState *icp, Monitor *mon); 187 void ics_pic_print_info(ICSState *ics, Monitor *mon); 188 189 void ics_resend(ICSState *ics); 190 void icp_resend(ICPState *ss); 191 192 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, 193 Error **errp); 194 195 /* KVM */ 196 void icp_get_kvm_state(ICPState *icp); 197 int icp_set_kvm_state(ICPState *icp); 198 void icp_synchronize_state(ICPState *icp); 199 void icp_kvm_realize(DeviceState *dev, Error **errp); 200 201 void ics_get_kvm_state(ICSState *ics); 202 int ics_set_kvm_state(ICSState *ics); 203 void ics_synchronize_state(ICSState *ics); 204 205 #endif /* XICS_H */ 206