1 /*
2 * QEMU emulation of an RISC-V IOMMU Platform Device
3 *
4 * Copyright (C) 2022-2023 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "hw/irq.h"
21 #include "hw/pci/pci_bus.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/sysbus.h"
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
26 #include "qemu/host-utils.h"
27 #include "qemu/module.h"
28 #include "qom/object.h"
29 #include "exec/exec-all.h"
30 #include "trace.h"
31
32 #include "riscv-iommu.h"
33
34 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
35
36 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5
37
38 /* RISC-V IOMMU System Platform Device Emulation */
39
40 struct RISCVIOMMUStateSys {
41 SysBusDevice parent;
42 uint64_t addr;
43 uint32_t base_irq;
44 DeviceState *irqchip;
45 RISCVIOMMUState iommu;
46
47 /* Wired int support */
48 qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
49
50 /* Memory Regions for MSIX table and pending bit entries. */
51 MemoryRegion msix_table_mmio;
52 MemoryRegion msix_pba_mmio;
53 uint8_t *msix_table;
54 uint8_t *msix_pba;
55 };
56
57 struct RISCVIOMMUSysClass {
58 /*< public >*/
59 DeviceRealize parent_realize;
60 ResettablePhases parent_phases;
61 };
62
msix_table_mmio_read(void * opaque,hwaddr addr,unsigned size)63 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
64 unsigned size)
65 {
66 RISCVIOMMUStateSys *s = opaque;
67
68 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
69 return pci_get_long(s->msix_table + addr);
70 }
71
msix_table_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)72 static void msix_table_mmio_write(void *opaque, hwaddr addr,
73 uint64_t val, unsigned size)
74 {
75 RISCVIOMMUStateSys *s = opaque;
76
77 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
78 pci_set_long(s->msix_table + addr, val);
79 }
80
81 static const MemoryRegionOps msix_table_mmio_ops = {
82 .read = msix_table_mmio_read,
83 .write = msix_table_mmio_write,
84 .endianness = DEVICE_LITTLE_ENDIAN,
85 .valid = {
86 .min_access_size = 4,
87 .max_access_size = 8,
88 },
89 .impl = {
90 .max_access_size = 4,
91 },
92 };
93
msix_pba_mmio_read(void * opaque,hwaddr addr,unsigned size)94 static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
95 unsigned size)
96 {
97 RISCVIOMMUStateSys *s = opaque;
98
99 return pci_get_long(s->msix_pba + addr);
100 }
101
msix_pba_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)102 static void msix_pba_mmio_write(void *opaque, hwaddr addr,
103 uint64_t val, unsigned size)
104 {
105 }
106
107 static const MemoryRegionOps msix_pba_mmio_ops = {
108 .read = msix_pba_mmio_read,
109 .write = msix_pba_mmio_write,
110 .endianness = DEVICE_LITTLE_ENDIAN,
111 .valid = {
112 .min_access_size = 4,
113 .max_access_size = 8,
114 },
115 .impl = {
116 .max_access_size = 4,
117 },
118 };
119
riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys * s,uint32_t n_vectors)120 static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s,
121 uint32_t n_vectors)
122 {
123 RISCVIOMMUState *iommu = &s->iommu;
124 uint32_t table_size = n_vectors * PCI_MSIX_ENTRY_SIZE;
125 uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG;
126 uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8;
127 uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256;
128
129 s->msix_table = g_malloc0(table_size);
130 s->msix_pba = g_malloc0(pba_size);
131
132 memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops,
133 s, "msix-table", table_size);
134 memory_region_add_subregion(&iommu->regs_mr, table_offset,
135 &s->msix_table_mmio);
136
137 memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s,
138 "msix-pba", pba_size);
139 memory_region_add_subregion(&iommu->regs_mr, pba_offset,
140 &s->msix_pba_mmio);
141 }
142
riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys * s,uint32_t vector)143 static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
144 uint32_t vector)
145 {
146 uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
147 uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
148 uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
149 MemTxResult result;
150
151 address_space_stl_le(&address_space_memory, msi_addr,
152 msi_data, MEMTXATTRS_UNSPECIFIED, &result);
153 trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
154 }
155
riscv_iommu_sysdev_notify(RISCVIOMMUState * iommu,unsigned vector)156 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
157 unsigned vector)
158 {
159 RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
160 uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
161
162 if (fctl & RISCV_IOMMU_FCTL_WSI) {
163 qemu_irq_pulse(s->irqs[vector]);
164 trace_riscv_iommu_sys_irq_sent(vector);
165 return;
166 }
167
168 riscv_iommu_sysdev_send_MSI(s, vector);
169 }
170
riscv_iommu_sys_realize(DeviceState * dev,Error ** errp)171 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
172 {
173 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev);
174 SysBusDevice *sysdev = SYS_BUS_DEVICE(s);
175 PCIBus *pci_bus;
176 qemu_irq irq;
177
178 qdev_realize(DEVICE(&s->iommu), NULL, errp);
179 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
180 if (s->addr) {
181 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
182 }
183
184 pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL);
185 if (pci_bus) {
186 riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
187 }
188
189 s->iommu.notify = riscv_iommu_sysdev_notify;
190
191 /* 4 IRQs are defined starting from s->base_irq */
192 for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
193 sysbus_init_irq(sysdev, &s->irqs[i]);
194 irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
195 sysbus_connect_irq(sysdev, i, irq);
196 }
197
198 riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS);
199 }
200
riscv_iommu_sys_init(Object * obj)201 static void riscv_iommu_sys_init(Object *obj)
202 {
203 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj);
204 RISCVIOMMUState *iommu = &s->iommu;
205
206 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
207 qdev_alias_all_properties(DEVICE(iommu), obj);
208
209 iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
210 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
211 }
212
213 static const Property riscv_iommu_sys_properties[] = {
214 DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
215 DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
216 DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
217 TYPE_DEVICE, DeviceState *),
218 };
219
riscv_iommu_sys_reset_hold(Object * obj,ResetType type)220 static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type)
221 {
222 RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj);
223 RISCVIOMMUState *iommu = &sys->iommu;
224
225 riscv_iommu_reset(iommu);
226
227 trace_riscv_iommu_sys_reset_hold(type);
228 }
229
riscv_iommu_sys_class_init(ObjectClass * klass,void * data)230 static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
231 {
232 DeviceClass *dc = DEVICE_CLASS(klass);
233 ResettableClass *rc = RESETTABLE_CLASS(klass);
234
235 rc->phases.hold = riscv_iommu_sys_reset_hold;
236
237 dc->realize = riscv_iommu_sys_realize;
238 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
239 device_class_set_props(dc, riscv_iommu_sys_properties);
240 }
241
242 static const TypeInfo riscv_iommu_sys = {
243 .name = TYPE_RISCV_IOMMU_SYS,
244 .parent = TYPE_SYS_BUS_DEVICE,
245 .class_init = riscv_iommu_sys_class_init,
246 .instance_init = riscv_iommu_sys_init,
247 .instance_size = sizeof(RISCVIOMMUStateSys),
248 };
249
riscv_iommu_register_sys(void)250 static void riscv_iommu_register_sys(void)
251 {
252 type_register_static(&riscv_iommu_sys);
253 }
254
255 type_init(riscv_iommu_register_sys)
256