1 /*
2 * ASPEED Ast27x0 TSP SoC
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "hw/qdev-clock.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18
19 #define AST2700_TSP_RAM_SIZE (32 * MiB)
20
21 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
22 [ASPEED_DEV_SRAM] = 0x00000000,
23 [ASPEED_DEV_INTC] = 0x72100000,
24 [ASPEED_DEV_SCU] = 0x72C02000,
25 [ASPEED_DEV_SCUIO] = 0x74C02000,
26 [ASPEED_DEV_UART0] = 0x74C33000,
27 [ASPEED_DEV_UART1] = 0x74C33100,
28 [ASPEED_DEV_UART2] = 0x74C33200,
29 [ASPEED_DEV_UART3] = 0x74C33300,
30 [ASPEED_DEV_UART4] = 0x72C1A000,
31 [ASPEED_DEV_INTCIO] = 0x74C18000,
32 [ASPEED_DEV_IPC0] = 0x72C1C000,
33 [ASPEED_DEV_IPC1] = 0x74C39000,
34 [ASPEED_DEV_UART5] = 0x74C33400,
35 [ASPEED_DEV_UART6] = 0x74C33500,
36 [ASPEED_DEV_UART7] = 0x74C33600,
37 [ASPEED_DEV_UART8] = 0x74C33700,
38 [ASPEED_DEV_UART9] = 0x74C33800,
39 [ASPEED_DEV_UART10] = 0x74C33900,
40 [ASPEED_DEV_UART11] = 0x74C33A00,
41 [ASPEED_DEV_UART12] = 0x74C33B00,
42 [ASPEED_DEV_TIMER1] = 0x72C10000,
43 };
44
45 static const int aspeed_soc_ast27x0a0tsp_irqmap[] = {
46 [ASPEED_DEV_SCU] = 12,
47 [ASPEED_DEV_UART0] = 132,
48 [ASPEED_DEV_UART1] = 132,
49 [ASPEED_DEV_UART2] = 132,
50 [ASPEED_DEV_UART3] = 132,
51 [ASPEED_DEV_UART4] = 8,
52 [ASPEED_DEV_UART5] = 132,
53 [ASPEED_DEV_UART6] = 132,
54 [ASPEED_DEV_UART7] = 132,
55 [ASPEED_DEV_UART8] = 132,
56 [ASPEED_DEV_UART9] = 132,
57 [ASPEED_DEV_UART10] = 132,
58 [ASPEED_DEV_UART11] = 132,
59 [ASPEED_DEV_UART12] = 132,
60 [ASPEED_DEV_TIMER1] = 16,
61 };
62
63 static const int aspeed_soc_ast27x0a1tsp_irqmap[] = {
64 [ASPEED_DEV_SCU] = 12,
65 [ASPEED_DEV_UART0] = 164,
66 [ASPEED_DEV_UART1] = 164,
67 [ASPEED_DEV_UART2] = 164,
68 [ASPEED_DEV_UART3] = 164,
69 [ASPEED_DEV_UART4] = 8,
70 [ASPEED_DEV_UART5] = 164,
71 [ASPEED_DEV_UART6] = 164,
72 [ASPEED_DEV_UART7] = 164,
73 [ASPEED_DEV_UART8] = 164,
74 [ASPEED_DEV_UART9] = 164,
75 [ASPEED_DEV_UART10] = 164,
76 [ASPEED_DEV_UART11] = 164,
77 [ASPEED_DEV_UART12] = 164,
78 [ASPEED_DEV_TIMER1] = 16,
79 };
80
81 /* TSPINT 164 */
82 static const int ast2700_tsp132_tsp164_intcmap[] = {
83 [ASPEED_DEV_UART0] = 7,
84 [ASPEED_DEV_UART1] = 8,
85 [ASPEED_DEV_UART2] = 9,
86 [ASPEED_DEV_UART3] = 10,
87 [ASPEED_DEV_UART5] = 11,
88 [ASPEED_DEV_UART6] = 12,
89 [ASPEED_DEV_UART7] = 13,
90 [ASPEED_DEV_UART8] = 14,
91 [ASPEED_DEV_UART9] = 15,
92 [ASPEED_DEV_UART10] = 16,
93 [ASPEED_DEV_UART11] = 17,
94 [ASPEED_DEV_UART12] = 18,
95 };
96
97 struct nvic_intc_irq_info {
98 int irq;
99 int intc_idx;
100 int orgate_idx;
101 const int *ptr;
102 };
103
104 static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
105 {160, 1, 0, NULL},
106 {161, 1, 1, NULL},
107 {162, 1, 2, NULL},
108 {163, 1, 3, NULL},
109 {164, 1, 4, ast2700_tsp132_tsp164_intcmap},
110 {165, 1, 5, NULL},
111 {166, 1, 6, NULL},
112 {167, 1, 7, NULL},
113 {168, 1, 8, NULL},
114 {169, 1, 9, NULL},
115 {128, 0, 1, NULL},
116 {129, 0, 2, NULL},
117 {130, 0, 3, NULL},
118 {131, 0, 4, NULL},
119 {132, 0, 5, ast2700_tsp132_tsp164_intcmap},
120 {133, 0, 6, NULL},
121 {134, 0, 7, NULL},
122 {135, 0, 8, NULL},
123 {136, 0, 9, NULL},
124 };
125
aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState * s,int dev)126 static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState *s, int dev)
127 {
128 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
129 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
130
131 int or_idx;
132 int idx;
133 int i;
134
135 for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
136 if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
137 assert(ast2700_tsp_intcmap[i].ptr);
138 or_idx = ast2700_tsp_intcmap[i].orgate_idx;
139 idx = ast2700_tsp_intcmap[i].intc_idx;
140 return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
141 ast2700_tsp_intcmap[i].ptr[dev]);
142 }
143 }
144
145 return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
146 }
147
aspeed_soc_ast27x0a0tsp_init(Object * obj)148 static void aspeed_soc_ast27x0a0tsp_init(Object *obj)
149 {
150 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
151 AspeedSoCState *s = ASPEED_SOC(obj);
152 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
153 char socname[8];
154 char typename[64];
155 int i;
156
157 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
158 g_assert_not_reached();
159 }
160
161 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
162
163 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
164
165 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
166 object_initialize_child(obj, "scu", &s->scu, typename);
167 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
168
169 for (i = 0; i < sc->uarts_num; i++) {
170 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
171 }
172
173 object_initialize_child(obj, "intc0", &a->intc[0],
174 TYPE_ASPEED_2700TSP_INTC);
175 object_initialize_child(obj, "intc1", &a->intc[1],
176 TYPE_ASPEED_2700TSP_INTCIO);
177
178 object_initialize_child(obj, "timerctrl", &s->timerctrl,
179 TYPE_UNIMPLEMENTED_DEVICE);
180 object_initialize_child(obj, "ipc0", &a->ipc[0],
181 TYPE_UNIMPLEMENTED_DEVICE);
182 object_initialize_child(obj, "ipc1", &a->ipc[1],
183 TYPE_UNIMPLEMENTED_DEVICE);
184 object_initialize_child(obj, "scuio", &a->scuio,
185 TYPE_UNIMPLEMENTED_DEVICE);
186 }
187
aspeed_soc_ast27x0a1tsp_init(Object * obj)188 static void aspeed_soc_ast27x0a1tsp_init(Object *obj)
189 {
190 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
191 AspeedSoCState *s = ASPEED_SOC(obj);
192 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
193 char socname[8];
194 char typename[64];
195 int i;
196
197 if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
198 g_assert_not_reached();
199 }
200
201 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
202
203 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
204
205 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
206 object_initialize_child(obj, "scu", &s->scu, typename);
207 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
208
209 for (i = 0; i < sc->uarts_num; i++) {
210 object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
211 }
212
213 object_initialize_child(obj, "intc0", &a->intc[0],
214 TYPE_ASPEED_2700TSP_INTC);
215 object_initialize_child(obj, "intc1", &a->intc[1],
216 TYPE_ASPEED_2700TSP_INTCIO);
217
218 object_initialize_child(obj, "timerctrl", &s->timerctrl,
219 TYPE_UNIMPLEMENTED_DEVICE);
220 object_initialize_child(obj, "ipc0", &a->ipc[0],
221 TYPE_UNIMPLEMENTED_DEVICE);
222 object_initialize_child(obj, "ipc1", &a->ipc[1],
223 TYPE_UNIMPLEMENTED_DEVICE);
224 object_initialize_child(obj, "scuio", &a->scuio,
225 TYPE_UNIMPLEMENTED_DEVICE);
226 }
227
aspeed_soc_ast27x0tsp_realize(DeviceState * dev_soc,Error ** errp)228 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
229 {
230 Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
231 AspeedSoCState *s = ASPEED_SOC(dev_soc);
232 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
233 DeviceState *armv7m;
234 Error *err = NULL;
235 g_autofree char *sram_name = NULL;
236 int i;
237
238 if (!clock_has_source(s->sysclk)) {
239 error_setg(errp, "sysclk clock must be wired up by the board code");
240 return;
241 }
242
243 /* AST27X0 TSP Core */
244 armv7m = DEVICE(&a->armv7m);
245 qdev_prop_set_uint32(armv7m, "num-irq", 256);
246 qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
247 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
248 object_property_set_link(OBJECT(&a->armv7m), "memory",
249 OBJECT(s->memory), &error_abort);
250 sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
251
252 sram_name = g_strdup_printf("aspeed.dram.%d",
253 CPU(a->armv7m.cpu)->cpu_index);
254
255 if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
256 &err)) {
257 return;
258 }
259 memory_region_add_subregion(s->memory,
260 sc->memmap[ASPEED_DEV_SRAM],
261 &s->sram);
262
263 /* SCU */
264 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
265 return;
266 }
267 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
268
269 /* INTC */
270 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
271 return;
272 }
273
274 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
275 sc->memmap[ASPEED_DEV_INTC]);
276
277 /* INTCIO */
278 if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
279 return;
280 }
281
282 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
283 sc->memmap[ASPEED_DEV_INTCIO]);
284
285 /* irq source orgates -> INTC */
286 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
287 qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
288 qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
289 }
290 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
291 assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
292 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
293 qdev_get_gpio_in(DEVICE(&a->armv7m),
294 ast2700_tsp_intcmap[i].irq));
295 }
296 /* irq source orgates -> INTC */
297 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
298 qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
299 qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
300 }
301 /* INTCIO -> INTC */
302 for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
303 sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
304 qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
305 }
306 /* UART */
307 if (!aspeed_soc_uart_realize(s, errp)) {
308 return;
309 }
310
311 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
312 "aspeed.timerctrl",
313 sc->memmap[ASPEED_DEV_TIMER1], 0x200);
314 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
315 "aspeed.ipc0",
316 sc->memmap[ASPEED_DEV_IPC0], 0x1000);
317 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
318 "aspeed.ipc1",
319 sc->memmap[ASPEED_DEV_IPC1], 0x1000);
320 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
321 "aspeed.scuio",
322 sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
323 }
324
aspeed_soc_ast27x0a0tsp_class_init(ObjectClass * klass,void * data)325 static void aspeed_soc_ast27x0a0tsp_class_init(ObjectClass *klass, void *data)
326 {
327 static const char * const valid_cpu_types[] = {
328 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
329 NULL
330 };
331 DeviceClass *dc = DEVICE_CLASS(klass);
332 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
333
334 /* Reason: The Aspeed SoC can only be instantiated from a board */
335 dc->user_creatable = false;
336 dc->realize = aspeed_soc_ast27x0tsp_realize;
337
338 sc->valid_cpu_types = valid_cpu_types;
339 sc->silicon_rev = AST2700_A0_SILICON_REV;
340 sc->sram_size = AST2700_TSP_RAM_SIZE;
341 sc->spis_num = 0;
342 sc->ehcis_num = 0;
343 sc->wdts_num = 0;
344 sc->macs_num = 0;
345 sc->uarts_num = 13;
346 sc->uarts_base = ASPEED_DEV_UART0;
347 sc->irqmap = aspeed_soc_ast27x0a0tsp_irqmap;
348 sc->memmap = aspeed_soc_ast27x0tsp_memmap;
349 sc->num_cpus = 1;
350 sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
351 }
352
aspeed_soc_ast27x0a1tsp_class_init(ObjectClass * klass,void * data)353 static void aspeed_soc_ast27x0a1tsp_class_init(ObjectClass *klass, void *data)
354 {
355 static const char * const valid_cpu_types[] = {
356 ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
357 NULL
358 };
359 DeviceClass *dc = DEVICE_CLASS(klass);
360 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
361
362 /* Reason: The Aspeed SoC can only be instantiated from a board */
363 dc->user_creatable = false;
364 dc->realize = aspeed_soc_ast27x0tsp_realize;
365
366 sc->valid_cpu_types = valid_cpu_types;
367 sc->silicon_rev = AST2700_A1_SILICON_REV;
368 sc->sram_size = AST2700_TSP_RAM_SIZE;
369 sc->spis_num = 0;
370 sc->ehcis_num = 0;
371 sc->wdts_num = 0;
372 sc->macs_num = 0;
373 sc->uarts_num = 13;
374 sc->uarts_base = ASPEED_DEV_UART0;
375 sc->irqmap = aspeed_soc_ast27x0a1tsp_irqmap;
376 sc->memmap = aspeed_soc_ast27x0tsp_memmap;
377 sc->num_cpus = 1;
378 sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
379 }
380
381 static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
382 {
383 .name = TYPE_ASPEED27X0TSP_SOC,
384 .parent = TYPE_ASPEED_SOC,
385 .instance_size = sizeof(Aspeed27x0TSPSoCState),
386 .abstract = true,
387 }, {
388 .name = "ast2700tsp-a0",
389 .parent = TYPE_ASPEED27X0TSP_SOC,
390 .instance_init = aspeed_soc_ast27x0a0tsp_init,
391 .class_init = aspeed_soc_ast27x0a0tsp_class_init,
392 }, {
393 .name = "ast2700tsp-a1",
394 .parent = TYPE_ASPEED27X0TSP_SOC,
395 .instance_init = aspeed_soc_ast27x0a1tsp_init,
396 .class_init = aspeed_soc_ast27x0a1tsp_class_init,
397 },
398 };
399
400 DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
401