1/* 2 * QEMU float support 3 * 4 * The code in this source file is derived from release 2a of the SoftFloat 5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and 6 * some later contributions) are provided under that license, as detailed below. 7 * It has subsequently been modified by contributors to the QEMU Project, 8 * so some portions are provided under: 9 * the SoftFloat-2a license 10 * the BSD license 11 * GPL-v2-or-later 12 * 13 * Any future contributions to this file after December 1st 2014 will be 14 * taken to be licensed under the Softfloat-2a license unless specifically 15 * indicated otherwise. 16 */ 17 18/* 19=============================================================================== 20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point 21Arithmetic Package, Release 2a. 22 23Written by John R. Hauser. This work was made possible in part by the 24International Computer Science Institute, located at Suite 600, 1947 Center 25Street, Berkeley, California 94704. Funding was partially provided by the 26National Science Foundation under grant MIP-9311980. The original version 27of this code was written as part of a project to build a fixed-point vector 28processor in collaboration with the University of California at Berkeley, 29overseen by Profs. Nelson Morgan and John Wawrzynek. More information 30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ 31arithmetic/SoftFloat.html'. 32 33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort 34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT 35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO 36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY 37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE. 38 39Derivative works are acceptable, even for commercial purposes, so long as 40(1) they include prominent notice that the work is derivative, and (2) they 41include prominent notice akin to these four paragraphs for those parts of 42this code that are retained. 43 44=============================================================================== 45*/ 46 47/* BSD licensing: 48 * Copyright (c) 2006, Fabrice Bellard 49 * All rights reserved. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions are met: 53 * 54 * 1. Redistributions of source code must retain the above copyright notice, 55 * this list of conditions and the following disclaimer. 56 * 57 * 2. Redistributions in binary form must reproduce the above copyright notice, 58 * this list of conditions and the following disclaimer in the documentation 59 * and/or other materials provided with the distribution. 60 * 61 * 3. Neither the name of the copyright holder nor the names of its contributors 62 * may be used to endorse or promote products derived from this software without 63 * specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 78/* Portions of this work are licensed under the terms of the GNU GPL, 79 * version 2 or later. See the COPYING file in the top-level directory. 80 */ 81 82/* 83 * Define whether architecture deviates from IEEE in not supporting 84 * signaling NaNs (so all NaNs are treated as quiet). 85 */ 86static inline bool no_signaling_nans(float_status *status) 87{ 88#if defined(TARGET_XTENSA) 89 return status->no_signaling_nans; 90#else 91 return false; 92#endif 93} 94 95/* Define how the architecture discriminates signaling NaNs. 96 * This done with the most significant bit of the fraction. 97 * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 98 * the msb must be zero. MIPS is (so far) unique in supporting both the 99 * 2008 revision and backward compatibility with their original choice. 100 * Thus for MIPS we must make the choice at runtime. 101 */ 102static inline bool snan_bit_is_one(float_status *status) 103{ 104#if defined(TARGET_MIPS) 105 return status->snan_bit_is_one; 106#elif defined(TARGET_HPPA) || defined(TARGET_SH4) 107 return 1; 108#else 109 return 0; 110#endif 111} 112 113/*---------------------------------------------------------------------------- 114| For the deconstructed floating-point with fraction FRAC, return true 115| if the fraction represents a signalling NaN; otherwise false. 116*----------------------------------------------------------------------------*/ 117 118static bool parts_is_snan_frac(uint64_t frac, float_status *status) 119{ 120 if (no_signaling_nans(status)) { 121 return false; 122 } else { 123 bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); 124 return msb == snan_bit_is_one(status); 125 } 126} 127 128/*---------------------------------------------------------------------------- 129| The pattern for a default generated deconstructed floating-point NaN. 130*----------------------------------------------------------------------------*/ 131 132static void parts64_default_nan(FloatParts64 *p, float_status *status) 133{ 134 bool sign = 0; 135 uint64_t frac; 136 137#if defined(TARGET_SPARC) || defined(TARGET_M68K) 138 /* !snan_bit_is_one, set all bits */ 139 frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; 140#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ 141 || defined(TARGET_MICROBLAZE) 142 /* !snan_bit_is_one, set sign and msb */ 143 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 144 sign = 1; 145#elif defined(TARGET_HPPA) 146 /* snan_bit_is_one, set msb-1. */ 147 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); 148#elif defined(TARGET_HEXAGON) 149 sign = 1; 150 frac = ~0ULL; 151#else 152 /* 153 * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, 154 * S390, SH4, TriCore, and Xtensa. Our other supported targets 155 * do not have floating-point. 156 */ 157 if (snan_bit_is_one(status)) { 158 /* set all bits other than msb */ 159 frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; 160 } else { 161 /* set msb */ 162 frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); 163 } 164#endif 165 166 *p = (FloatParts64) { 167 .cls = float_class_qnan, 168 .sign = sign, 169 .exp = INT_MAX, 170 .frac = frac 171 }; 172} 173 174static void parts128_default_nan(FloatParts128 *p, float_status *status) 175{ 176 /* 177 * Extrapolate from the choices made by parts64_default_nan to fill 178 * in the quad-floating format. If the low bit is set, assume we 179 * want to set all non-snan bits. 180 */ 181 FloatParts64 p64; 182 parts64_default_nan(&p64, status); 183 184 *p = (FloatParts128) { 185 .cls = float_class_qnan, 186 .sign = p64.sign, 187 .exp = INT_MAX, 188 .frac_hi = p64.frac, 189 .frac_lo = -(p64.frac & 1) 190 }; 191} 192 193/*---------------------------------------------------------------------------- 194| Returns a quiet NaN from a signalling NaN for the deconstructed 195| floating-point parts. 196*----------------------------------------------------------------------------*/ 197 198static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) 199{ 200 g_assert(!no_signaling_nans(status)); 201 202 /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ 203 if (snan_bit_is_one(status)) { 204 frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); 205 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); 206 } else { 207 frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); 208 } 209 return frac; 210} 211 212static void parts64_silence_nan(FloatParts64 *p, float_status *status) 213{ 214 p->frac = parts_silence_nan_frac(p->frac, status); 215 p->cls = float_class_qnan; 216} 217 218static void parts128_silence_nan(FloatParts128 *p, float_status *status) 219{ 220 p->frac_hi = parts_silence_nan_frac(p->frac_hi, status); 221 p->cls = float_class_qnan; 222} 223 224/*---------------------------------------------------------------------------- 225| The pattern for a default generated extended double-precision NaN. 226*----------------------------------------------------------------------------*/ 227floatx80 floatx80_default_nan(float_status *status) 228{ 229 floatx80 r; 230 231 /* None of the targets that have snan_bit_is_one use floatx80. */ 232 assert(!snan_bit_is_one(status)); 233#if defined(TARGET_M68K) 234 r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); 235 r.high = 0x7FFF; 236#else 237 /* X86 */ 238 r.low = UINT64_C(0xC000000000000000); 239 r.high = 0xFFFF; 240#endif 241 return r; 242} 243 244/*---------------------------------------------------------------------------- 245| The pattern for a default generated extended double-precision inf. 246*----------------------------------------------------------------------------*/ 247 248#define floatx80_infinity_high 0x7FFF 249#if defined(TARGET_M68K) 250#define floatx80_infinity_low UINT64_C(0x0000000000000000) 251#else 252#define floatx80_infinity_low UINT64_C(0x8000000000000000) 253#endif 254 255const floatx80 floatx80_infinity 256 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); 257 258/*---------------------------------------------------------------------------- 259| Returns 1 if the half-precision floating-point value `a' is a quiet 260| NaN; otherwise returns 0. 261*----------------------------------------------------------------------------*/ 262 263bool float16_is_quiet_nan(float16 a_, float_status *status) 264{ 265 if (no_signaling_nans(status)) { 266 return float16_is_any_nan(a_); 267 } else { 268 uint16_t a = float16_val(a_); 269 if (snan_bit_is_one(status)) { 270 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 271 } else { 272 273 return ((a >> 9) & 0x3F) == 0x3F; 274 } 275 } 276} 277 278/*---------------------------------------------------------------------------- 279| Returns 1 if the bfloat16 value `a' is a quiet 280| NaN; otherwise returns 0. 281*----------------------------------------------------------------------------*/ 282 283bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) 284{ 285 if (no_signaling_nans(status)) { 286 return bfloat16_is_any_nan(a_); 287 } else { 288 uint16_t a = a_; 289 if (snan_bit_is_one(status)) { 290 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 291 } else { 292 return ((a >> 6) & 0x1FF) == 0x1FF; 293 } 294 } 295} 296 297/*---------------------------------------------------------------------------- 298| Returns 1 if the half-precision floating-point value `a' is a signaling 299| NaN; otherwise returns 0. 300*----------------------------------------------------------------------------*/ 301 302bool float16_is_signaling_nan(float16 a_, float_status *status) 303{ 304 if (no_signaling_nans(status)) { 305 return 0; 306 } else { 307 uint16_t a = float16_val(a_); 308 if (snan_bit_is_one(status)) { 309 return ((a >> 9) & 0x3F) == 0x3F; 310 } else { 311 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); 312 } 313 } 314} 315 316/*---------------------------------------------------------------------------- 317| Returns 1 if the bfloat16 value `a' is a signaling 318| NaN; otherwise returns 0. 319*----------------------------------------------------------------------------*/ 320 321bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) 322{ 323 if (no_signaling_nans(status)) { 324 return 0; 325 } else { 326 uint16_t a = a_; 327 if (snan_bit_is_one(status)) { 328 return ((a >> 6) & 0x1FF) == 0x1FF; 329 } else { 330 return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F); 331 } 332 } 333} 334 335/*---------------------------------------------------------------------------- 336| Returns 1 if the single-precision floating-point value `a' is a quiet 337| NaN; otherwise returns 0. 338*----------------------------------------------------------------------------*/ 339 340bool float32_is_quiet_nan(float32 a_, float_status *status) 341{ 342 if (no_signaling_nans(status)) { 343 return float32_is_any_nan(a_); 344 } else { 345 uint32_t a = float32_val(a_); 346 if (snan_bit_is_one(status)) { 347 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 348 } else { 349 return ((uint32_t)(a << 1) >= 0xFF800000); 350 } 351 } 352} 353 354/*---------------------------------------------------------------------------- 355| Returns 1 if the single-precision floating-point value `a' is a signaling 356| NaN; otherwise returns 0. 357*----------------------------------------------------------------------------*/ 358 359bool float32_is_signaling_nan(float32 a_, float_status *status) 360{ 361 if (no_signaling_nans(status)) { 362 return 0; 363 } else { 364 uint32_t a = float32_val(a_); 365 if (snan_bit_is_one(status)) { 366 return ((uint32_t)(a << 1) >= 0xFF800000); 367 } else { 368 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); 369 } 370 } 371} 372 373/*---------------------------------------------------------------------------- 374| Select which NaN to propagate for a two-input operation. 375| IEEE754 doesn't specify all the details of this, so the 376| algorithm is target-specific. 377| The routine is passed various bits of information about the 378| two NaNs and should return 0 to select NaN a and 1 for NaN b. 379| Note that signalling NaNs are always squashed to quiet NaNs 380| by the caller, by calling floatXX_silence_nan() before 381| returning them. 382| 383| aIsLargerSignificand is only valid if both a and b are NaNs 384| of some kind, and is true if a has the larger significand, 385| or if both a and b have the same significand but a is 386| positive but b is negative. It is only needed for the x87 387| tie-break rule. 388*----------------------------------------------------------------------------*/ 389 390static int pickNaN(FloatClass a_cls, FloatClass b_cls, 391 bool aIsLargerSignificand, float_status *status) 392{ 393 /* 394 * We guarantee not to require the target to tell us how to 395 * pick a NaN if we're always returning the default NaN. 396 * But if we're not in default-NaN mode then the target must 397 * specify via set_float_2nan_prop_rule(). 398 */ 399 assert(!status->default_nan_mode); 400 401 switch (status->float_2nan_prop_rule) { 402 case float_2nan_prop_s_ab: 403 if (is_snan(a_cls)) { 404 return 0; 405 } else if (is_snan(b_cls)) { 406 return 1; 407 } else if (is_qnan(a_cls)) { 408 return 0; 409 } else { 410 return 1; 411 } 412 break; 413 case float_2nan_prop_s_ba: 414 if (is_snan(b_cls)) { 415 return 1; 416 } else if (is_snan(a_cls)) { 417 return 0; 418 } else if (is_qnan(b_cls)) { 419 return 1; 420 } else { 421 return 0; 422 } 423 break; 424 case float_2nan_prop_ab: 425 if (is_nan(a_cls)) { 426 return 0; 427 } else { 428 return 1; 429 } 430 break; 431 case float_2nan_prop_ba: 432 if (is_nan(b_cls)) { 433 return 1; 434 } else { 435 return 0; 436 } 437 break; 438 case float_2nan_prop_x87: 439 /* 440 * This implements x87 NaN propagation rules: 441 * SNaN + QNaN => return the QNaN 442 * two SNaNs => return the one with the larger significand, silenced 443 * two QNaNs => return the one with the larger significand 444 * SNaN and a non-NaN => return the SNaN, silenced 445 * QNaN and a non-NaN => return the QNaN 446 * 447 * If we get down to comparing significands and they are the same, 448 * return the NaN with the positive sign bit (if any). 449 */ 450 if (is_snan(a_cls)) { 451 if (is_snan(b_cls)) { 452 return aIsLargerSignificand ? 0 : 1; 453 } 454 return is_qnan(b_cls) ? 1 : 0; 455 } else if (is_qnan(a_cls)) { 456 if (is_snan(b_cls) || !is_qnan(b_cls)) { 457 return 0; 458 } else { 459 return aIsLargerSignificand ? 0 : 1; 460 } 461 } else { 462 return 1; 463 } 464 default: 465 g_assert_not_reached(); 466 } 467} 468 469/*---------------------------------------------------------------------------- 470| Select which NaN to propagate for a three-input operation. 471| For the moment we assume that no CPU needs the 'larger significand' 472| information. 473| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN 474*----------------------------------------------------------------------------*/ 475static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, 476 bool infzero, float_status *status) 477{ 478#if defined(TARGET_ARM) 479 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns 480 * the default NaN 481 */ 482 if (infzero && is_qnan(c_cls)) { 483 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 484 return 3; 485 } 486 487 /* This looks different from the ARM ARM pseudocode, because the ARM ARM 488 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. 489 */ 490 if (is_snan(c_cls)) { 491 return 2; 492 } else if (is_snan(a_cls)) { 493 return 0; 494 } else if (is_snan(b_cls)) { 495 return 1; 496 } else if (is_qnan(c_cls)) { 497 return 2; 498 } else if (is_qnan(a_cls)) { 499 return 0; 500 } else { 501 return 1; 502 } 503#elif defined(TARGET_MIPS) 504 if (snan_bit_is_one(status)) { 505 /* 506 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 507 * case sets InvalidOp and returns the default NaN 508 */ 509 if (infzero) { 510 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 511 return 3; 512 } 513 /* Prefer sNaN over qNaN, in the a, b, c order. */ 514 if (is_snan(a_cls)) { 515 return 0; 516 } else if (is_snan(b_cls)) { 517 return 1; 518 } else if (is_snan(c_cls)) { 519 return 2; 520 } else if (is_qnan(a_cls)) { 521 return 0; 522 } else if (is_qnan(b_cls)) { 523 return 1; 524 } else { 525 return 2; 526 } 527 } else { 528 /* 529 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 530 * case sets InvalidOp and returns the input value 'c' 531 */ 532 if (infzero) { 533 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 534 return 2; 535 } 536 /* Prefer sNaN over qNaN, in the c, a, b order. */ 537 if (is_snan(c_cls)) { 538 return 2; 539 } else if (is_snan(a_cls)) { 540 return 0; 541 } else if (is_snan(b_cls)) { 542 return 1; 543 } else if (is_qnan(c_cls)) { 544 return 2; 545 } else if (is_qnan(a_cls)) { 546 return 0; 547 } else { 548 return 1; 549 } 550 } 551#elif defined(TARGET_LOONGARCH64) 552 /* 553 * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) 554 * case sets InvalidOp and returns the input value 'c' 555 */ 556 if (infzero) { 557 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 558 return 2; 559 } 560 /* Prefer sNaN over qNaN, in the c, a, b order. */ 561 if (is_snan(c_cls)) { 562 return 2; 563 } else if (is_snan(a_cls)) { 564 return 0; 565 } else if (is_snan(b_cls)) { 566 return 1; 567 } else if (is_qnan(c_cls)) { 568 return 2; 569 } else if (is_qnan(a_cls)) { 570 return 0; 571 } else { 572 return 1; 573 } 574#elif defined(TARGET_PPC) 575 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 576 * to return an input NaN if we have one (ie c) rather than generating 577 * a default NaN 578 */ 579 if (infzero) { 580 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 581 return 2; 582 } 583 584 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; 585 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 586 */ 587 if (is_nan(a_cls)) { 588 return 0; 589 } else if (is_nan(c_cls)) { 590 return 2; 591 } else { 592 return 1; 593 } 594#elif defined(TARGET_RISCV) 595 /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ 596 if (infzero) { 597 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 598 } 599 return 3; /* default NaN */ 600#elif defined(TARGET_SPARC) 601 /* For (inf,0,nan) return c. */ 602 if (infzero) { 603 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 604 return 2; 605 } 606 /* Prefer SNaN over QNaN, order C, B, A. */ 607 if (is_snan(c_cls)) { 608 return 2; 609 } else if (is_snan(b_cls)) { 610 return 1; 611 } else if (is_snan(a_cls)) { 612 return 0; 613 } else if (is_qnan(c_cls)) { 614 return 2; 615 } else if (is_qnan(b_cls)) { 616 return 1; 617 } else { 618 return 0; 619 } 620#elif defined(TARGET_XTENSA) 621 /* 622 * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns 623 * an input NaN if we have one (ie c). 624 */ 625 if (infzero) { 626 float_raise(float_flag_invalid | float_flag_invalid_imz, status); 627 return 2; 628 } 629 if (status->use_first_nan) { 630 if (is_nan(a_cls)) { 631 return 0; 632 } else if (is_nan(b_cls)) { 633 return 1; 634 } else { 635 return 2; 636 } 637 } else { 638 if (is_nan(c_cls)) { 639 return 2; 640 } else if (is_nan(b_cls)) { 641 return 1; 642 } else { 643 return 0; 644 } 645 } 646#else 647 /* A default implementation: prefer a to b to c. 648 * This is unlikely to actually match any real implementation. 649 */ 650 if (is_nan(a_cls)) { 651 return 0; 652 } else if (is_nan(b_cls)) { 653 return 1; 654 } else { 655 return 2; 656 } 657#endif 658} 659 660/*---------------------------------------------------------------------------- 661| Returns 1 if the double-precision floating-point value `a' is a quiet 662| NaN; otherwise returns 0. 663*----------------------------------------------------------------------------*/ 664 665bool float64_is_quiet_nan(float64 a_, float_status *status) 666{ 667 if (no_signaling_nans(status)) { 668 return float64_is_any_nan(a_); 669 } else { 670 uint64_t a = float64_val(a_); 671 if (snan_bit_is_one(status)) { 672 return (((a >> 51) & 0xFFF) == 0xFFE) 673 && (a & 0x0007FFFFFFFFFFFFULL); 674 } else { 675 return ((a << 1) >= 0xFFF0000000000000ULL); 676 } 677 } 678} 679 680/*---------------------------------------------------------------------------- 681| Returns 1 if the double-precision floating-point value `a' is a signaling 682| NaN; otherwise returns 0. 683*----------------------------------------------------------------------------*/ 684 685bool float64_is_signaling_nan(float64 a_, float_status *status) 686{ 687 if (no_signaling_nans(status)) { 688 return 0; 689 } else { 690 uint64_t a = float64_val(a_); 691 if (snan_bit_is_one(status)) { 692 return ((a << 1) >= 0xFFF0000000000000ULL); 693 } else { 694 return (((a >> 51) & 0xFFF) == 0xFFE) 695 && (a & UINT64_C(0x0007FFFFFFFFFFFF)); 696 } 697 } 698} 699 700/*---------------------------------------------------------------------------- 701| Returns 1 if the extended double-precision floating-point value `a' is a 702| quiet NaN; otherwise returns 0. This slightly differs from the same 703| function for other types as floatx80 has an explicit bit. 704*----------------------------------------------------------------------------*/ 705 706int floatx80_is_quiet_nan(floatx80 a, float_status *status) 707{ 708 if (no_signaling_nans(status)) { 709 return floatx80_is_any_nan(a); 710 } else { 711 if (snan_bit_is_one(status)) { 712 uint64_t aLow; 713 714 aLow = a.low & ~0x4000000000000000ULL; 715 return ((a.high & 0x7FFF) == 0x7FFF) 716 && (aLow << 1) 717 && (a.low == aLow); 718 } else { 719 return ((a.high & 0x7FFF) == 0x7FFF) 720 && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); 721 } 722 } 723} 724 725/*---------------------------------------------------------------------------- 726| Returns 1 if the extended double-precision floating-point value `a' is a 727| signaling NaN; otherwise returns 0. This slightly differs from the same 728| function for other types as floatx80 has an explicit bit. 729*----------------------------------------------------------------------------*/ 730 731int floatx80_is_signaling_nan(floatx80 a, float_status *status) 732{ 733 if (no_signaling_nans(status)) { 734 return 0; 735 } else { 736 if (snan_bit_is_one(status)) { 737 return ((a.high & 0x7FFF) == 0x7FFF) 738 && ((a.low << 1) >= 0x8000000000000000ULL); 739 } else { 740 uint64_t aLow; 741 742 aLow = a.low & ~UINT64_C(0x4000000000000000); 743 return ((a.high & 0x7FFF) == 0x7FFF) 744 && (uint64_t)(aLow << 1) 745 && (a.low == aLow); 746 } 747 } 748} 749 750/*---------------------------------------------------------------------------- 751| Returns a quiet NaN from a signalling NaN for the extended double-precision 752| floating point value `a'. 753*----------------------------------------------------------------------------*/ 754 755floatx80 floatx80_silence_nan(floatx80 a, float_status *status) 756{ 757 /* None of the targets that have snan_bit_is_one use floatx80. */ 758 assert(!snan_bit_is_one(status)); 759 a.low |= UINT64_C(0xC000000000000000); 760 return a; 761} 762 763/*---------------------------------------------------------------------------- 764| Takes two extended double-precision floating-point values `a' and `b', one 765| of which is a NaN, and returns the appropriate NaN result. If either `a' or 766| `b' is a signaling NaN, the invalid exception is raised. 767*----------------------------------------------------------------------------*/ 768 769floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) 770{ 771 bool aIsLargerSignificand; 772 FloatClass a_cls, b_cls; 773 774 /* This is not complete, but is good enough for pickNaN. */ 775 a_cls = (!floatx80_is_any_nan(a) 776 ? float_class_normal 777 : floatx80_is_signaling_nan(a, status) 778 ? float_class_snan 779 : float_class_qnan); 780 b_cls = (!floatx80_is_any_nan(b) 781 ? float_class_normal 782 : floatx80_is_signaling_nan(b, status) 783 ? float_class_snan 784 : float_class_qnan); 785 786 if (is_snan(a_cls) || is_snan(b_cls)) { 787 float_raise(float_flag_invalid, status); 788 } 789 790 if (status->default_nan_mode) { 791 return floatx80_default_nan(status); 792 } 793 794 if (a.low < b.low) { 795 aIsLargerSignificand = 0; 796 } else if (b.low < a.low) { 797 aIsLargerSignificand = 1; 798 } else { 799 aIsLargerSignificand = (a.high < b.high) ? 1 : 0; 800 } 801 802 if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { 803 if (is_snan(b_cls)) { 804 return floatx80_silence_nan(b, status); 805 } 806 return b; 807 } else { 808 if (is_snan(a_cls)) { 809 return floatx80_silence_nan(a, status); 810 } 811 return a; 812 } 813} 814 815/*---------------------------------------------------------------------------- 816| Returns 1 if the quadruple-precision floating-point value `a' is a quiet 817| NaN; otherwise returns 0. 818*----------------------------------------------------------------------------*/ 819 820bool float128_is_quiet_nan(float128 a, float_status *status) 821{ 822 if (no_signaling_nans(status)) { 823 return float128_is_any_nan(a); 824 } else { 825 if (snan_bit_is_one(status)) { 826 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 827 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); 828 } else { 829 return ((a.high << 1) >= 0xFFFF000000000000ULL) 830 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 831 } 832 } 833} 834 835/*---------------------------------------------------------------------------- 836| Returns 1 if the quadruple-precision floating-point value `a' is a 837| signaling NaN; otherwise returns 0. 838*----------------------------------------------------------------------------*/ 839 840bool float128_is_signaling_nan(float128 a, float_status *status) 841{ 842 if (no_signaling_nans(status)) { 843 return 0; 844 } else { 845 if (snan_bit_is_one(status)) { 846 return ((a.high << 1) >= 0xFFFF000000000000ULL) 847 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); 848 } else { 849 return (((a.high >> 47) & 0xFFFF) == 0xFFFE) 850 && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); 851 } 852 } 853} 854