1 /**
2 * Copyright (C) 2017 IBM Corporation
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include "cfam_access.hpp"
17 #include "ext_interface.hpp"
18 #include "p9_cfam.hpp"
19 #include "registration.hpp"
20 #include "targeting.hpp"
21
22 #include <phosphor-logging/log.hpp>
23
24 namespace openpower
25 {
26 namespace p9
27 {
28
29 using namespace phosphor::logging;
30 using namespace openpower::cfam::access;
31 using namespace openpower::cfam::p9;
32 using namespace openpower::targeting;
33
34 /**
35 * @brief Starts the self boot engine on P9 position 0 to kick off a boot.
36 * @return void
37 */
startHost()38 void startHost()
39 {
40 Targeting targets;
41 const auto& master = *(targets.begin());
42
43 log<level::INFO>("Running P9 procedure startHost",
44 entry("NUM_PROCS=%d", targets.size()));
45
46 // Ensure asynchronous clock mode is set
47 writeReg(master, P9_LL_MODE_REG, 0x00000001);
48
49 // Clock mux select override
50 for (const auto& t : targets)
51 {
52 writeRegWithMask(t, P9_ROOT_CTRL8, 0x0000000C, 0x0000000C);
53 }
54
55 // Enable P9 checkstop to be reported to the BMC
56
57 // Setup FSI2PIB to report checkstop
58 writeReg(master, P9_FSI_A_SI1S, 0x20000000);
59
60 // Enable Xstop/ATTN interrupt
61 writeReg(master, P9_FSI2PIB_TRUE_MASK, 0x60000000);
62
63 // Arm it
64 writeReg(master, P9_FSI2PIB_INTERRUPT, 0xFFFFFFFF);
65
66 // Kick off the SBE to start the boot
67
68 // Choose seeprom side to boot from
69 cfam_data_t sbeSide = 0;
70 if (getBootCount() > 0)
71 {
72 sbeSide = 0;
73 log<level::INFO>("Setting SBE seeprom side to 0",
74 entry("SBE_SIDE_SELECT=%d", 0));
75 }
76 else
77 {
78 sbeSide = 0x00004000;
79 log<level::INFO>("Setting SBE seeprom side to 1",
80 entry("SBE_SIDE_SELECT=%d", 1));
81 }
82 // Bit 17 of the ctrl status reg indicates sbe seeprom boot side
83 // 0 -> Side 0, 1 -> Side 1
84 writeRegWithMask(master, P9_SBE_CTRL_STATUS, sbeSide, 0x00004000);
85
86 // Ensure SBE start bit is 0 to handle warm reboot scenarios
87 writeRegWithMask(master, P9_CBS_CS, 0x00000000, 0x80000000);
88
89 // Start the SBE
90 writeRegWithMask(master, P9_CBS_CS, 0x80000000, 0x80000000);
91 }
92
93 REGISTER_PROCEDURE("startHost", startHost)
94
95 } // namespace p9
96 } // namespace openpower
97